[PATCH v2 00/14] Enable USB3 for Qualcomm IPQ5018 and IPQ5332

[PATCH v2 00/14] Enable USB3 for Qualcomm IPQ5018 and IPQ5332

[George Moussalem via B4 Relay]

Patch series adds Qualcomm 22ull Super-Speed USB UNIPHY driver support
present in Qualcomm IPQ5018 and IPQ5332 SoC which is required to enable
USB3. This PHY is interfaced with SNPS DWC3 USB and SNPS DWC PCIe.
Either one of the interface can use it via the mux selection present in
the TCSR register. Current patch series adds the support for UNIPHY with
DWC3 USB.

---
Changes in v2:
- Rebased on top of master tree
- Included support for IPQ5018
- Changed bindings filename to match compatible string
- Dropped items from compatible list in bindings file
- Added required block in bindings file
- Removed double space of reset property in example in bindings file
- Added branching logic based on compatible string to define the right
  clocks per SoC in bindings file
- Renamed phy driver to phy-qcom-uniphy-usb-ss-22ull.c
- Added missing error handling uniphy_usb_init in phy driver
- Changed to use devm_clk_hw_register_fixed_rate to register fixed rate
  pipe clock
- Changed to use devm_of_clk_add_hw_provider to register clock provider
- Release exclusive get of vdd and changed to devm_regulator_get as the
  regulator supply is also acquired by the m31 USB2 phy driver
- Inlined acquisition of clocks to phy probe function
- Use reverse xmas tree sorting of variables in phy driver probe
- Moved USB mux selection away from phy init to probe as it needs to be
  set before the controller is taken out of reset.
- Flattened the USB controller nodes in line with latest bindings and
  flattened driver approach for both SoCs.
- Set clock frequencies in IPQ5018 controller node to ensure they're
  parented correctly and override any freqs set by the bootloader.
- Removed patch to add usb phy node for IPQ5332 as the pcie0 phy shares
  the same MMIO as the usb3 phy. Hence, chose the approach to override
  the compatible string of said node and assign the right clocks, reset,
  and related properties upon enabling it as a USB3 phy instead of
  adding a new node with the same unit and reg address space.
- Link to v1: https://lore.kernel.org/r/20230929084209.3033093-1-quic_ipkumar@quicinc.com

---
George Moussalem (7):
      arm64: dts: qcom: ipq5018: Add USB Super-Speed PHY node
      arm64: dts: qcom: ipq5332: Flatten usb controller node
      arm64: dts: qcom: ipq5018: Flatten usb controller node
      dt-bindings: usb: qcom,snps-dwc3: Add clocks for USB3 on Qualcomm IPQ5018
      arm64: dts: qcom: ipq5018: Add clocks required for USB3 support
      arm64: dts: qcom: ipq5018: Add Super-Speed UNIPHY to USB node
      arm64: dts: qcom: ipq5018: Enable USB Super-Speed PHY

Praveenkumar I (7):
      dt-bindings: phy: Document the Qualcomm IPQ5332 UNIPHY USB Super-speed PHY
      phy: qcom: Introduce Qualcomm IPQ5332 Super-Speed USB UNIPHY driver
      dt-bindings: usb: qcom,snps-dwc3: Add clocks for USB3 on Qualcomm IPQ5332
      arm64: dts: qcom: ipq5332: Add clocks required for USB3 support
      arm64: dts: qcom: ipq5332: Add Super-Speed UNIPHY to USB node
      arm64: dts: qcom: ipq5332: Enable USB Super-Speed PHY
      arm64: defconfig: Enable qcom USB UNIPHY driver

 .../phy/qcom,ipq5332-uniphy-usb-ss-phy.yaml        | 111 ++++++++
 .../devicetree/bindings/usb/qcom,snps-dwc3.yaml    |  41 ++-
 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts     |  18 +-
 arch/arm64/boot/dts/qcom/ipq5018.dtsi              |  82 +++---
 arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts        |  23 +-
 arch/arm64/boot/dts/qcom/ipq5332.dtsi              |  57 ++--
 arch/arm64/configs/defconfig                       |   1 +
 drivers/phy/qualcomm/Kconfig                       |  10 +
 drivers/phy/qualcomm/Makefile                      |   1 +
 .../phy/qualcomm/phy-qcom-uniphy-usb-ss-22ull.c    | 304 +++++++++++++++++++++
 10 files changed, 577 insertions(+), 71 deletions(-)
---
base-commit: 7b6a23be392e99e7a4cf72325697315460cf2a20
change-id: 20260803-ipq5018-usb3-4b289b1ed16e

Best regards,
-- 
George Moussalem <george.moussalem@outlook.com>



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[PATCH v2 01/14] dt-bindings: phy: Document the Qualcomm IPQ5332 UNIPHY USB Super-speed PHY

[George Moussalem via B4 Relay]

From: Praveenkumar I <quic_ipkumar@quicinc.com>

Document the Qualcomm USB3 22ull UNIPHY present in the IPQ5018 and
IPQ5332 SoCs.

Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 .../phy/qcom,ipq5332-uniphy-usb-ss-phy.yaml        | 111 +++++++++++++++++++++
 1 file changed, 111 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-usb-ss-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-usb-ss-phy.yaml
new file mode 100644
index 000000000000..cc9eccac51dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-usb-ss-phy.yaml
@@ -0,0 +1,111 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-usb-ss-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm UNIPHY USB Super-Speed 22ull PHY
+
+maintainers:
+  - Praveenkumar I <quic_ipkumar@quicinc.com>
+  - Varadarajan Narayanan <quic_varada@quicinc.com>
+
+description:
+  USB Super-Speed UNIPHY found in Qualcomm IPQ5018 & IPQ5332 SoCs.
+
+properties:
+  compatible:
+    enum:
+      - qcom,ipq5018-uniphy-usb-ss-phy
+      - qcom,ipq5332-uniphy-usb-ss-phy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 2
+    maxItems: 3
+
+  resets:
+    maxItems: 1
+
+  vdd-supply:
+    description:
+      Phandle to 5V regulator supply to PHY digital circuit.
+
+  qcom,phy-usb-mux-sel:
+    description: |
+      Mux selection for USB PHY. The USB3 and PCIe PHY pads are muxed and the
+      mux selection is done via a register in TCSR syscon.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle of TCSR syscon
+          - description: offset of PHY mux selection register
+
+  "#clock-cells":
+    const: 0
+
+  "#phy-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+  - vdd-supply
+  - qcom,phy-usb-mux-sel
+  - "#clock-cells"
+  - "#phy-cells"
+
+additionalProperties: false
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,ipq5018-uniphy-usb-ss-phy
+    then:
+      properties:
+        clocks:
+          items:
+            - description: USB3 PHY CFG AHB clock
+            - description: USB3 pipe clock
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,ipq5332-uniphy-usb-ss-phy
+    then:
+      properties:
+        clocks:
+          items:
+            - description: Shared PCIe/USB3 PHY AHB clock
+            - description: USB3 PHY CFG AHB clock
+            - description: USB3 pipe clock
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
+
+    phy@4b0000 {
+        compatible = "qcom,ipq5332-uniphy-usb-ss-phy";
+        reg = <0x4b0000 0x800>;
+
+        clocks = <&gcc GCC_PCIE3X1_PHY_AHB_CLK>,
+                 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+                 <&gcc GCC_USB0_PIPE_CLK>;
+        resets = <&gcc GCC_USB0_PHY_BCR>;
+
+        #clock-cells = <0>;
+        #phy-cells = <0>;
+
+        qcom,phy-usb-mux-sel = <&tcsr 0x10540>;
+
+        vdd-supply = <&regulator_fixed_5p0>;
+    };

-- 
2.53.0



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[PATCH v2 02/14] phy: qcom: Introduce Qualcomm IPQ5332 Super-Speed USB UNIPHY driver

[George Moussalem via B4 Relay]

From: Praveenkumar I <quic_ipkumar@quicinc.com>

Adds Qualcomm 22ull Super-Speed USB UNIPHY driver support which is
present in Qualcomm IPQ5018 & IPQ5332 SoCs.

This PHY is interfaced with SNPS DWC3 USB and SNPS DWC PCIe. Either one
of the interface can use the it and selection is done via mux present in
TCSR register. By default, the PHY is configured for PCIe interface and
needs this driver to configure the mux for USB.

Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 drivers/phy/qualcomm/Kconfig                       |  10 +
 drivers/phy/qualcomm/Makefile                      |   1 +
 .../phy/qualcomm/phy-qcom-uniphy-usb-ss-22ull.c    | 304 +++++++++++++++++++++
 3 files changed, 315 insertions(+)

diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
index 60a0ead127fa..1ceb04afe1e3 100644
--- a/drivers/phy/qualcomm/Kconfig
+++ b/drivers/phy/qualcomm/Kconfig
@@ -158,6 +158,16 @@ config PHY_QCOM_UNIPHY_PCIE_28LP
 	  handles PHY initialization, clock management required after
 	  resetting the hardware and power management.
 
+config PHY_QCOM_UNIPHY_USB_22ULL
+	tristate "Qualcomm IPQ5332 UNIPHY USB Super-Speed 22ull driver"
+	depends on USB && (ARCH_QCOM || COMPILE_TEST)
+	select GENERIC_PHY
+	help
+	  Enable this to support the Qualcomm USB Super-Speed UNIPHY transceiver
+	  that is used on Qualcomm IPQ5018 and IPQ5332 SoCs with DWC3 USB core.
+	  It handles PHY initialization, clock management required after
+	  resetting the hardware and power management.
+
 config PHY_QCOM_M31_EUSB
 	tristate "Qualcomm M31 eUSB2 PHY driver support"
 	depends on USB && (ARCH_QCOM || COMPILE_TEST)
diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
index b71a6a0bed3f..295e8042e3f4 100644
--- a/drivers/phy/qualcomm/Makefile
+++ b/drivers/phy/qualcomm/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_PHY_QCOM_QMP_USB_LEGACY)	+= phy-qcom-qmp-usb-legacy.o
 obj-$(CONFIG_PHY_QCOM_QUSB2)		+= phy-qcom-qusb2.o
 obj-$(CONFIG_PHY_QCOM_EUSB2_REPEATER)	+= phy-qcom-eusb2-repeater.o
 obj-$(CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP)	+= phy-qcom-uniphy-pcie-28lp.o
+obj-$(CONFIG_PHY_QCOM_UNIPHY_USB_22ULL)	+= phy-qcom-uniphy-usb-ss-22ull.o
 obj-$(CONFIG_PHY_QCOM_USB_HS) 		+= phy-qcom-usb-hs.o
 obj-$(CONFIG_PHY_QCOM_USB_HSIC) 	+= phy-qcom-usb-hsic.o
 obj-$(CONFIG_PHY_QCOM_USB_HS_28NM)	+= phy-qcom-usb-hs-28nm.o
diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-usb-ss-22ull.c b/drivers/phy/qualcomm/phy-qcom-uniphy-usb-ss-22ull.c
new file mode 100644
index 000000000000..089de7cebef0
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-usb-ss-22ull.c
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+
+#define SSCG_CTRL_REG_1				0x9c
+#define SSCG_CTRL_REG_2				0xa0
+#define SSCG_CTRL_REG_3				0xa4
+#define SSCG_CTRL_REG_4				0xa8
+#define SSCG_CTRL_REG_5				0xac
+
+#define PCIE_USB_COMBO_PHY_CFG_MISC1		0x214
+#define PCIE_USB_COMBO_PHY_CFG_RX_AFE_2		0x7C4
+#define PCIE_USB_COMBO_PHY_CFG_RX_DLF_DEMUX_2	0x7E8
+
+#define TCSR_USB_MUX_SEL			BIT(0)
+
+struct phy_init_tbl {
+	unsigned int offset;
+	unsigned int val;
+};
+
+struct uniphy_cfg {
+	const struct phy_init_tbl *init_seq;
+	int num_init_seq;
+	u32 pipe_clk_rate;
+};
+
+struct uniphy_usb {
+	struct device		*dev;
+	const struct uniphy_cfg	*cfg;
+	struct phy		*phy;
+	void __iomem		*base;
+	struct clk_bulk_data	*clks;
+	unsigned int		num_clks;
+	struct reset_control	*reset;
+	struct regulator	*vreg;
+	struct regmap		*tcsr;
+	unsigned int		mux_offset;
+};
+
+#define PHY_INIT_CFG(o, v)		\
+	{				\
+		.offset = o,		\
+		.val = v,		\
+	}
+
+static const struct phy_init_tbl ipq5018_usb_uniphy_init_tbl[] = {
+	PHY_INIT_CFG(SSCG_CTRL_REG_4, 0x1cb9),
+	PHY_INIT_CFG(SSCG_CTRL_REG_5, 0x023a),
+	PHY_INIT_CFG(SSCG_CTRL_REG_3, 0xd360),
+	PHY_INIT_CFG(SSCG_CTRL_REG_1, 0x1),
+	PHY_INIT_CFG(SSCG_CTRL_REG_2, 0xeb),
+};
+
+static const struct phy_init_tbl ipq5332_usb_uniphy_init_tbl[] = {
+	PHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_RX_AFE_2, 0x1076),
+	PHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_RX_DLF_DEMUX_2, 0x3142),
+	PHY_INIT_CFG(PCIE_USB_COMBO_PHY_CFG_MISC1, 0x3),
+};
+
+static const struct uniphy_cfg ipq5018_cfg = {
+	.init_seq	= ipq5018_usb_uniphy_init_tbl,
+	.num_init_seq	= ARRAY_SIZE(ipq5018_usb_uniphy_init_tbl),
+	.pipe_clk_rate	= 250000000,
+};
+
+static const struct uniphy_cfg ipq5332_cfg = {
+	.init_seq	= ipq5332_usb_uniphy_init_tbl,
+	.num_init_seq	= ARRAY_SIZE(ipq5332_usb_uniphy_init_tbl),
+	.pipe_clk_rate	= 250000000,
+};
+
+static int uniphy_usb_init(struct phy *phy)
+{
+	struct uniphy_usb *uniphy = phy_get_drvdata(phy);
+	const struct uniphy_cfg *cfg = uniphy->cfg;
+	const struct phy_init_tbl *tbl = cfg->init_seq;
+	void __iomem *base = uniphy->base;
+	struct device *dev = uniphy->dev;
+	int i, ret;
+
+	ret = regulator_enable(uniphy->vreg);
+	if (ret) {
+		dev_err(dev, "failed to enable regulator: %d\n", ret);
+		return ret;
+	}
+
+	/* Perform phy reset */
+	ret = reset_control_assert(uniphy->reset);
+	if (ret) {
+		dev_err(dev, "Failed to assert reset: %d\n", ret);
+		goto err_disable_regulator;
+	}
+
+	usleep_range(1, 5);
+
+	ret = reset_control_deassert(uniphy->reset);
+	if (ret) {
+		dev_err(dev, "Failed to deassert reset: %d\n", ret);
+		goto err_assert_reset;
+	}
+
+	ret = clk_bulk_prepare_enable(uniphy->num_clks, uniphy->clks);
+	if (ret) {
+		dev_err(dev, "failed to enable clocks: %d\n", ret);
+		goto err_assert_reset;
+	}
+
+	/* phy autoload delay */
+	usleep_range(35, 40);
+
+	for (i = 0; i < cfg->num_init_seq; i++)
+		writel(tbl[i].val, base + tbl[i].offset);
+
+	return 0;
+
+err_assert_reset:
+	/* Assert phy reset */
+	reset_control_assert(uniphy->reset);
+
+err_disable_regulator:
+	regulator_disable(uniphy->vreg);
+
+	return ret;
+}
+
+static int uniphy_usb_shutdown(struct phy *phy)
+{
+	struct uniphy_usb *uniphy = phy_get_drvdata(phy);
+
+	clk_bulk_disable_unprepare(uniphy->num_clks, uniphy->clks);
+
+	/* Assert phy reset */
+	reset_control_assert(uniphy->reset);
+
+	regulator_disable(uniphy->vreg);
+
+	return 0;
+}
+
+static const struct phy_ops uniphy_usb_ops = {
+	.power_on	= uniphy_usb_init,
+	.power_off	= uniphy_usb_shutdown,
+	.owner		= THIS_MODULE,
+};
+
+/*
+ * Register a fixed rate pipe clock.
+ *
+ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
+ * controls it. The <s>_pipe_clk coming out of the GCC is requested
+ * by the PHY driver for its operations.
+ * We register the <s>_pipe_clksrc here. The gcc driver takes care
+ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
+ * Below picture shows this relationship.
+ *
+ *         +---------------+
+ *         |   PHY block   |<<---------------------------------------+
+ *         |               |                                         |
+ *         |   +-------+   |                   +-----+               |
+ *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
+ *    clk  |   +-------+   |                   +-----+
+ *         +---------------+
+ */
+static int phy_pipe_clk_register(struct uniphy_usb *uniphy, int id)
+{
+	struct device *dev = uniphy->dev;
+	struct clk_hw *hw;
+	char name[64];
+
+	snprintf(name, sizeof(name), "usbphy%d_pipe_clk_src", id);
+	hw = devm_clk_hw_register_fixed_rate(dev, name, NULL, 0,
+					     uniphy->cfg->pipe_clk_rate);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+
+	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
+}
+
+static int qcom_uniphy_usb_mux_select(struct uniphy_usb *uniphy, bool enable)
+{
+	return regmap_update_bits(uniphy->tcsr, uniphy->mux_offset,
+				  TCSR_USB_MUX_SEL,
+				  enable ? TCSR_USB_MUX_SEL : 0);
+}
+
+static int qcom_uniphy_usb_probe(struct platform_device *pdev)
+{
+	struct phy_provider *phy_provider;
+	struct device *dev = &pdev->dev;
+	struct uniphy_usb *uniphy;
+	int ret;
+
+	uniphy = devm_kzalloc(dev, sizeof(*uniphy), GFP_KERNEL);
+	if (!uniphy)
+		return -ENOMEM;
+
+	uniphy->dev = dev;
+
+	uniphy->cfg = of_device_get_match_data(dev);
+	if (!uniphy->cfg)
+		return -EINVAL;
+
+	uniphy->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(uniphy->base))
+		return dev_err_probe(dev, PTR_ERR(uniphy->base),
+				     "failed to map base\n");
+
+	ret = devm_clk_bulk_get_all(dev, &uniphy->clks);
+	if (ret < 0)
+		return dev_err_probe(dev, ret, "failed to get clocks\n");
+
+	uniphy->num_clks = ret;
+
+	uniphy->reset = devm_reset_control_get_exclusive_by_index(dev, 0);
+	if (IS_ERR(uniphy->reset))
+		return dev_err_probe(dev, PTR_ERR(uniphy->reset),
+				     "failed to get reset\n");
+
+	uniphy->vreg = devm_regulator_get(dev, "vdd");
+	if (IS_ERR(uniphy->vreg))
+		return dev_err_probe(dev, PTR_ERR(uniphy->vreg),
+				     "failed to get vreg\n");
+
+	uniphy->tcsr = syscon_regmap_lookup_by_phandle_args(dev->of_node,
+							    "qcom,phy-usb-mux-sel",
+							    1, &uniphy->mux_offset);
+	if (IS_ERR(uniphy->tcsr)) {
+		ret = PTR_ERR(uniphy->tcsr);
+		uniphy->tcsr = NULL;
+		return dev_err_probe(dev, ret, "failed to get regmap\n");
+	}
+
+	/*
+	 * Select the USB position of the phy mux before anything comes out
+	 * of reset. Selecting it later leaves the SuperSpeed pads muxed away
+	 * while the controller resets, and the SS link doesn't train and is
+	 * stuck in Rx.Detect (USB2 is unaffected as it isn't muxed).
+	 */
+	ret = qcom_uniphy_usb_mux_select(uniphy, true);
+	if (ret)
+		return dev_err_probe(dev, ret, "failed to select USB mux\n");
+
+	uniphy->phy = devm_phy_create(dev, NULL, &uniphy_usb_ops);
+	if (IS_ERR(uniphy->phy)) {
+		ret = PTR_ERR(uniphy->phy);
+		return dev_err_probe(dev, ret, "failed to create PHY\n");
+	}
+
+	ret = phy_pipe_clk_register(uniphy, uniphy->phy->id);
+	if (ret)
+		return dev_err_probe(dev, ret, "failed to register pipe clk\n");
+
+	phy_set_drvdata(uniphy->phy, uniphy);
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	ret = PTR_ERR_OR_ZERO(phy_provider);
+
+	return ret;
+}
+
+static void qcom_uniphy_usb_remove(struct platform_device *pdev)
+{
+	struct uniphy_usb *uniphy = platform_get_drvdata(pdev);
+
+	qcom_uniphy_usb_mux_select(uniphy, false);
+}
+
+static const struct of_device_id qcom_uniphy_usb_of_match[] = {
+	{ .compatible = "qcom,ipq5018-uniphy-usb-ss-phy", .data = &ipq5018_cfg},
+	{ .compatible = "qcom,ipq5332-uniphy-usb-ss-phy", .data = &ipq5332_cfg},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, qcom_uniphy_usb_of_match);
+
+static struct platform_driver qcom_uniphy_usb_driver = {
+	.probe	= qcom_uniphy_usb_probe,
+	.remove = qcom_uniphy_usb_remove,
+	.driver = {
+		.of_match_table	= qcom_uniphy_usb_of_match,
+		.name  = "qcom,uniphy-usb-ss-phy",
+	}
+};
+module_platform_driver(qcom_uniphy_usb_driver);
+
+MODULE_DESCRIPTION("Qualcomm UNIPHY Super-Speed USB PHY driver");
+MODULE_LICENSE("GPL");

-- 
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[PATCH v2 03/14] arm64: dts: qcom: ipq5018: Add USB Super-Speed PHY node

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Add USB Super-Speed UNIPHY node and populate the USB DT clock on the GCC
node for the GCC to gate the PIPE clock supplied by the USB3 PHY.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 4fc627b47fe7..d259a841ad17 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -179,6 +179,23 @@ usbphy0: phy@5b000 {
 			status = "disabled";
 		};
 
+		usbphy1: phy@5d000 {
+			compatible = "qcom,ipq5018-uniphy-usb-ss-phy";
+			reg = <0x0005d000 0x800>;
+
+			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_USB0_PIPE_CLK>;
+
+			resets = <&gcc GCC_USB0_PHY_BCR>;
+
+			#clock-cells = <0>;
+			#phy-cells = <0>;
+
+			qcom,phy-usb-mux-sel = <&tcsr 0x10540>;
+
+			status = "disabled";
+		};
+
 		pcie1_phy: phy@7e000 {
 			compatible = "qcom,ipq5018-uniphy-pcie-phy";
 			reg = <0x0007e000 0x800>;
@@ -436,7 +453,7 @@ gcc: clock-controller@1800000 {
 				 <&sleep_clk>,
 				 <&pcie0_phy>,
 				 <&pcie1_phy>,
-				 <0>,
+				 <&usbphy1>,
 				 <&gephy_rx_clk>,
 				 <&gephy_tx_clk>,
 				 <0>,

-- 
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[PATCH v2 04/14] arm64: dts: qcom: ipq5332: Flatten usb controller node

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Flatten usb controller node and update to using latest bindings and
flattened driver approach.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts |  6 ++--
 arch/arm64/boot/dts/qcom/ipq5332.dtsi       | 51 +++++++++++++----------------
 2 files changed, 24 insertions(+), 33 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
index c224ffc65b08..25a70cd884c0 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
@@ -90,11 +90,9 @@ spi_0_cs_pins: spi-0-cs-state {
 };
 
 &usb {
-	status = "okay";
-};
-
-&usb_dwc {
 	dr_mode = "host";
+
+	status = "okay";
 };
 
 &usbphy0 {
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 74d9de8d7641..83d0377455da 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -493,16 +493,9 @@ qpic_nand: spi@79b0000 {
 			status = "disabled";
 		};
 
-		usb: usb@8af8800 {
-			compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";
-			reg = <0x08af8800 0x400>;
-
-			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "pwr_event",
-					  "dp_hs_phy_irq",
-					  "dm_hs_phy_irq";
+		usb: usb@8a00000 {
+			compatible = "qcom,ipq5332-dwc3", "qcom,snps-dwc3";
+			reg = <0x08a00000 0xe000>;
 
 			clocks = <&gcc GCC_USB0_MASTER_CLK>,
 				 <&gcc GCC_USB0_SLEEP_CLK>,
@@ -513,31 +506,31 @@ usb: usb@8af8800 {
 
 			resets = <&gcc GCC_USB_BCR>;
 
-			qcom,select-utmi-as-pipe-clk;
+			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "dwc_usb3",
+					  "pwr_event",
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq";
 
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
 			interconnects = <&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>,
 					<&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>;
 			interconnect-names = "usb-ddr", "apps-usb";
 
-			status = "disabled";
+			phys = <&usbphy0>;
+			phy-names = "usb2-phy";
 
-			usb_dwc: usb@8a00000 {
-				compatible = "snps,dwc3";
-				reg = <0x08a00000 0xe000>;
-				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
-				clock-names = "ref";
-				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
-				phy-names = "usb2-phy";
-				phys = <&usbphy0>;
-				tx-fifo-resize;
-				snps,is-utmi-l1-suspend;
-				snps,hird-threshold = /bits/ 8 <0x0>;
-				snps,dis_u2_susphy_quirk;
-				snps,dis_u3_susphy_quirk;
-			};
+			qcom,select-utmi-as-pipe-clk;
+
+			tx-fifo-resize;
+			snps,is-utmi-l1-suspend;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_u3_susphy_quirk;
+
+			status = "disabled";
 		};
 
 		intc: interrupt-controller@b000000 {

-- 
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[PATCH v2 05/14] arm64: dts: qcom: ipq5018: Flatten usb controller node

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Flatten usb controller node and update to using latest bindings and
flattened driver approach.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts |  6 ++--
 arch/arm64/boot/dts/qcom/ipq5018.dtsi          | 49 +++++++++++---------------
 2 files changed, 23 insertions(+), 32 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
index 33eef92b19b1..8efb2b21ed9e 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
@@ -110,11 +110,9 @@ data-pins {
 };
 
 &usb {
-	status = "okay";
-};
-
-&usb_dwc {
 	dr_mode = "host";
+
+	status = "okay";
 };
 
 &usbphy0 {
diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index d259a841ad17..965649db36f3 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -597,16 +597,9 @@ qpic_nand: spi@79b0000 {
 			status = "disabled";
 		};
 
-		usb: usb@8af8800 {
-			compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
-			reg = <0x08af8800 0x400>;
-
-			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "pwr_event",
-					  "dp_hs_phy_irq",
-					  "dm_hs_phy_irq";
+		usb: usb@8a00000 {
+			compatible = "qcom,ipq5018-dwc3", "qcom,snps-dwc3";
+			reg = <0x08a00000 0xe000>;
 
 			clocks = <&gcc GCC_USB0_MASTER_CLK>,
 				 <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
@@ -617,29 +610,29 @@ usb: usb@8af8800 {
 				      "sleep",
 				      "mock_utmi";
 
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "dwc_usb3",
+					  "pwr_event",
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq";
+
 			resets = <&gcc GCC_USB0_BCR>;
 
+			phys = <&usbphy0>;
+			phy-names = "usb2-phy";
+
 			qcom,select-utmi-as-pipe-clk;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
 
-			status = "disabled";
+			tx-fifo-resize;
+			snps,is-utmi-l1-suspend;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_u3_susphy_quirk;
 
-			usb_dwc: usb@8a00000 {
-				compatible = "snps,dwc3";
-				reg = <0x08a00000 0xe000>;
-				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
-				clock-names = "ref";
-				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-				phy-names = "usb2-phy";
-				phys = <&usbphy0>;
-				tx-fifo-resize;
-				snps,is-utmi-l1-suspend;
-				snps,hird-threshold = /bits/ 8 <0x0>;
-				snps,dis_u2_susphy_quirk;
-				snps,dis_u3_susphy_quirk;
-			};
+			status = "disabled";
 		};
 
 		intc: interrupt-controller@b000000 {

-- 
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[PATCH v2 06/14] dt-bindings: usb: qcom,snps-dwc3: Add clocks for USB3 on Qualcomm IPQ5332

[George Moussalem via B4 Relay]

From: Praveenkumar I <quic_ipkumar@quicinc.com>

Add aux and lfps clocks in Qualcomm IPQ5332. These clocks are required
only for USB Super-Speed support.

Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 .../devicetree/bindings/usb/qcom,snps-dwc3.yaml      | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
index ea60f7220afe..ce36109f5df7 100644
--- a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
@@ -173,7 +173,6 @@ allOf:
           contains:
             enum:
               - qcom,ipq4019-dwc3
-              - qcom,ipq5332-dwc3
     then:
       properties:
         clocks:
@@ -185,6 +184,25 @@ allOf:
             - const: sleep
             - const: mock_utmi
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,ipq5332-dwc3
+    then:
+      properties:
+        clocks:
+          minItems: 5
+          maxItems: 5
+        clock-names:
+          items:
+            - const: core
+            - const: sleep
+            - const: mock_utmi
+            - const: aux
+            - const: lfps
+
   - if:
       properties:
         compatible:

-- 
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[PATCH v2 07/14] dt-bindings: usb: qcom,snps-dwc3: Add clocks for USB3 on Qualcomm IPQ5018

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Add aux and lfps clocks in Qualcomm IPQ5018. These clocks are required
only for USB Super-Speed support.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 .../devicetree/bindings/usb/qcom,snps-dwc3.yaml     | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
index ce36109f5df7..e87cdf41f5f2 100644
--- a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
@@ -184,6 +184,26 @@ allOf:
             - const: sleep
             - const: mock_utmi
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,ipq5018-dwc3
+    then:
+      properties:
+        clocks:
+          minItems: 6
+          maxItems: 6
+        clock-names:
+          items:
+            - const: core
+            - const: iface
+            - const: sleep
+            - const: mock_utmi
+            - const: aux
+            - const: lfps
+
   - if:
       properties:
         compatible:
@@ -304,7 +324,6 @@ allOf:
         compatible:
           contains:
             enum:
-              - qcom,ipq5018-dwc3
               - qcom,msm8994-dwc3
               - qcom,qcs404-dwc3
     then:

-- 
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[PATCH v2 08/14] arm64: dts: qcom: ipq5332: Add clocks required for USB3 support

[George Moussalem via B4 Relay]

From: Praveenkumar I <quic_ipkumar@quicinc.com>

Add aux and lfps clocks to USB controller node for Super-Speed support.

Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq5332.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 83d0377455da..664586979ec4 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -499,10 +499,14 @@ usb: usb@8a00000 {
 
 			clocks = <&gcc GCC_USB0_MASTER_CLK>,
 				 <&gcc GCC_USB0_SLEEP_CLK>,
-				 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+				 <&gcc GCC_USB0_MOCK_UTMI_CLK>,
+				 <&gcc GCC_USB0_AUX_CLK>,
+				 <&gcc GCC_USB0_LFPS_CLK>;
 			clock-names = "core",
 				      "sleep",
-				      "mock_utmi";
+				      "mock_utmi",
+				      "aux",
+				      "lfps";
 
 			resets = <&gcc GCC_USB_BCR>;
 

-- 
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[PATCH v2 09/14] arm64: dts: qcom: ipq5018: Add clocks required for USB3 support

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Add aux and lfps clocks to USB controller node for Super-Speed support.
These clocks are required for USB3 mode only and are not needed for USB2
mode.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 965649db36f3..c98889a7c26c 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -604,11 +604,21 @@ usb: usb@8a00000 {
 			clocks = <&gcc GCC_USB0_MASTER_CLK>,
 				 <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 				 <&gcc GCC_USB0_SLEEP_CLK>,
-				 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+				 <&gcc GCC_USB0_MOCK_UTMI_CLK>,
+				 <&gcc GCC_USB0_AUX_CLK>,
+				 <&gcc GCC_USB0_LFPS_CLK>;
 			clock-names = "core",
 				      "iface",
 				      "sleep",
-				      "mock_utmi";
+				      "mock_utmi",
+				      "aux",
+				      "lfps";
+			assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
+					  <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+			assigned-clock-rates = <200000000>,
+					       <200000000>,
+					       <60000000>;
 
 			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,

-- 
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[PATCH v2 10/14] arm64: dts: qcom: ipq5332: Add Super-Speed UNIPHY to USB node

[George Moussalem via B4 Relay]

From: Praveenkumar I <quic_ipkumar@quicinc.com>

Add the USB3 UNIPHY node to the USB controller node.
In addition, switch to the pipe clock supplied by the USB3 UNIPHY
instead of the UTMI clock.

Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq5332.dtsi | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 664586979ec4..6253443c8d7f 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -523,10 +523,8 @@ usb: usb@8a00000 {
 					<&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>;
 			interconnect-names = "usb-ddr", "apps-usb";
 
-			phys = <&usbphy0>;
-			phy-names = "usb2-phy";
-
-			qcom,select-utmi-as-pipe-clk;
+			phys = <&usbphy0>, <&usbphy1>;
+			phy-names = "usb2-phy", "usb3-phy";
 
 			tx-fifo-resize;
 			snps,is-utmi-l1-suspend;

-- 
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[PATCH v2 11/14] arm64: dts: qcom: ipq5018: Add Super-Speed UNIPHY to USB node

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Add the USB3 UNIPHY node to the USB controller node.
In addition, switch to the pipe clock supplied by the USB3 UNIPHY
instead of the UTMI clock.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index c98889a7c26c..01b8181ffa40 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -631,10 +631,8 @@ usb: usb@8a00000 {
 
 			resets = <&gcc GCC_USB0_BCR>;
 
-			phys = <&usbphy0>;
-			phy-names = "usb2-phy";
-
-			qcom,select-utmi-as-pipe-clk;
+			phys = <&usbphy0>, <&usbphy1>;
+			phy-names = "usb2-phy", "usb3-phy";
 
 			tx-fifo-resize;
 			snps,is-utmi-l1-suspend;

-- 
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[PATCH v2 12/14] arm64: dts: qcom: ipq5332: Enable USB Super-Speed PHY

[George Moussalem via B4 Relay]

From: Praveenkumar I <quic_ipkumar@quicinc.com>

Enable USB Super-Speed PHY support. The PCIe and USB3 PHYs share the
same MMIO address space, so override the compatible string to use the
USB3 PHY driver instead of the PCIe PHY driver and set the required
properties accordingly.

Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
index 25a70cd884c0..164f9a9a6c75 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
@@ -100,3 +100,22 @@ &usbphy0 {
 
 	status = "okay";
 };
+
+/* this combo PHY supports PCIe and USB3 */
+&pcie0_phy {
+	compatible = "qcom,ipq5018-uniphy-usb-ss-phy";
+
+	clocks = <&gcc GCC_PCIE3X1_PHY_AHB_CLK>,
+		 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+		 <&gcc GCC_USB0_PIPE_CLK>;
+
+	resets =  <&gcc GCC_USB0_PHY_BCR>;
+
+	qcom,phy-usb-mux-sel = <&tcsr 0x10540>;
+
+	vdd-supply = <&regulator_fixed_5p0>;
+
+	/delete-property/ num-lanes;
+
+	status = "okay";
+};

-- 
2.53.0



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[PATCH v2 13/14] arm64: dts: qcom: ipq5018: Enable USB Super-Speed PHY

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Add the 5V supply regulator and enable USB Super-Speed PHY support.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
index 8efb2b21ed9e..ca29f271e673 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
@@ -22,6 +22,14 @@ aliases {
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	regulator_fixed_5p0: regulator-s0500 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "fixed_5p0";
+		gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &blsp1_uart1 {
@@ -119,6 +127,12 @@ &usbphy0 {
 	status = "okay";
 };
 
+&usbphy1 {
+	vdd-supply = <&regulator_fixed_5p0>;
+
+	status = "okay";
+};
+
 &xo_board_clk {
 	clock-div = <4>;
 	clock-mult = <1>;

-- 
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[PATCH v2 14/14] arm64: defconfig: Enable qcom USB UNIPHY driver

[George Moussalem via B4 Relay]

From: Praveenkumar I <quic_ipkumar@quicinc.com>

Enable USB UNIPHY driver present in Qualcomm IPQ5332.

Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 6ec8d3a69c98..301cc21200bb 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1782,6 +1782,7 @@ CONFIG_PHY_QCOM_QUSB2=m
 CONFIG_PHY_QCOM_EUSB2_REPEATER=m
 CONFIG_PHY_QCOM_M31_USB=m
 CONFIG_PHY_QCOM_M31_EUSB=m
+CONFIG_PHY_QCOM_UNIPHY_USB_22ULL=m
 CONFIG_PHY_QCOM_USB_HS=m
 CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=m
 CONFIG_PHY_QCOM_USB_HS_28NM=m

-- 
2.53.0



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Re: [PATCH v2 01/14] dt-bindings: phy: Document the Qualcomm IPQ5332 UNIPHY USB Super-speed PHY

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Missing `minItems: 3` constraint for IPQ5332 clocks in conditional block allows incomplete device trees to pass validation.
--

--- Patch [1]: [PATCH v2 01/14] dt-bindings: phy: Document the Qualcomm IPQ5332 UNIPHY USB Super-speed PHY ---
commit 0e89230ae30b325a8982291c9e629f57e5fde180
Author: Praveenkumar I <quic_ipkumar@quicinc.com>

dt-bindings: phy: Document the Qualcomm IPQ5332 UNIPHY USB Super-speed PHY

Document the Qualcomm USB3 22ull UNIPHY present in the IPQ5018 and
IPQ5332 SoCs.

> diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-usb-ss-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-usb-ss-phy.yaml
> new file mode 100644
> index 0000000000000..cc9eccac51ddb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-usb-ss-phy.yaml

[ ... ]

> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,ipq5332-uniphy-usb-ss-phy
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: Shared PCIe/USB3 PHY AHB clock
> +            - description: USB3 PHY CFG AHB clock
> +            - description: USB3 pipe clock

[Severity: Low]
Is a minItems: 3 constraint missing for the clocks in this conditional block?

Since the global clocks definition sets minItems: 2, device trees for IPQ5332
that incorrectly specify only 2 clocks will silently pass dt_binding_check
validation. The json-schema items list keyword only validates the elements
present up to the size of the instance array; it does not enforce array length
by itself.

Would it be better to add minItems: 3 alongside the items list to ensure all
three clocks are required when the qcom,ipq5332-uniphy-usb-ss-phy compatible
string is used?

-- 
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Re: [PATCH v2 06/14] dt-bindings: usb: qcom,snps-dwc3: Add clocks for USB3 on Qualcomm IPQ5332

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The schema modification unconditionally mandates 5 clocks for `qcom,ipq5332-dwc3`, breaking validation for existing valid device trees that provide only 3 clocks for High-Speed-only configurations.
--

--- Patch [6]: [PATCH v2 06/14] dt-bindings: usb: qcom,snps-dwc3: Add clocks for USB3 on Qualcomm IPQ5332 ---
commit 76251f6cda12ef34d26acca7a91c897245bd05c0
Author: Praveenkumar I <quic_ipkumar@quicinc.com>

dt-bindings: usb: qcom,snps-dwc3: Add clocks for USB3 on Qualcomm IPQ5332

This commit adds aux and lfps clocks for the Qualcomm IPQ5332 platform in the
qcom,snps-dwc3 bindings, splitting it from the qcom,ipq4019-dwc3 block.

> diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
> index 8201656b41ed7..e59fbfc1af71b 100644
> --- a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
> +++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
[ ... ]
> @@ -182,6 +181,25 @@ allOf:
>              - const: sleep
>              - const: mock_utmi
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,ipq5332-dwc3
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 5
> +          maxItems: 5

[Severity: High]
The commit message states that the aux and lfps clocks are required only for
USB Super-Speed support. Does setting minItems to 5 unconditionally break
schema validation for existing High-Speed-only device trees that only supply
the core, sleep, and mock_utmi clocks?

If these clocks are optional depending on the hardware configuration, should
minItems remain 3 with the additional clocks defined as optional items?

> +        clock-names:
> +          items:
> +            - const: core
> +            - const: sleep
> +            - const: mock_utmi
> +            - const: aux
> +            - const: lfps
> +

-- 
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Re: [PATCH v2 02/14] phy: qcom: Introduce Qualcomm IPQ5332 Super-Speed USB UNIPHY driver

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Missing `platform_set_drvdata()` in the probe function causes a NULL pointer dereference in the remove callback.
- [Medium] Probe failure paths fail to restore the TCSR multiplexer to its default hardware state.
- [Medium] The driver fails to `select MFD_SYSCON` in Kconfig, risking a silent probe failure.
--

--- Patch [2]: [PATCH v2 02/14] phy: qcom: Introduce Qualcomm IPQ5332 Super-Speed USB UNIPHY driver ---
commit 2ff7b4ffaf9a300ab45c516bb3b192d9f0a5c88e
Author: Praveenkumar I <quic_ipkumar@quicinc.com>

phy: qcom: Introduce Qualcomm IPQ5332 Super-Speed USB UNIPHY driver

Adds Qualcomm 22ull Super-Speed USB UNIPHY driver support which is
present in Qualcomm IPQ5018 & IPQ5332 SoCs.

This PHY is interfaced with SNPS DWC3 USB and SNPS DWC PCIe. Either one
of the interface can use the it and selection is done via mux present in
TCSR register. By default, the PHY is configured for PCIe interface and
needs this driver to configure the mux for USB.

> diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
> index 60a0ead127fa9..1ceb04afe1e3a 100644
> --- a/drivers/phy/qualcomm/Kconfig
> +++ b/drivers/phy/qualcomm/Kconfig
> @@ -158,6 +158,16 @@ config PHY_QCOM_UNIPHY_PCIE_28LP
>  	  handles PHY initialization, clock management required after
>  	  resetting the hardware and power management.
>  
> +config PHY_QCOM_UNIPHY_USB_22ULL
> +	tristate "Qualcomm IPQ5332 UNIPHY USB Super-Speed 22ull driver"
> +	depends on USB && (ARCH_QCOM || COMPILE_TEST)
> +	select GENERIC_PHY

[Severity: Medium]
Since this driver uses syscon_regmap_lookup_by_phandle_args(), should it
select MFD_SYSCON to ensure the required syscon utilities are compiled in
and avoid silent probe failures?

> +	help
> +	  Enable this to support the Qualcomm USB Super-Speed UNIPHY transceiver

[ ... ]

> diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-usb-ss-22ull.c b/drivers/phy/qualcomm/phy-qcom-uniphy-usb-ss-22ull.c
> new file mode 100644
> index 0000000000000..089de7cebef03
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-usb-ss-22ull.c

[ ... ]

> +static int qcom_uniphy_usb_probe(struct platform_device *pdev)
> +{

[ ... ]

> +	/*
> +	 * Select the USB position of the phy mux before anything comes out
> +	 * of reset. Selecting it later leaves the SuperSpeed pads muxed away
> +	 * while the controller resets, and the SS link doesn't train and is
> +	 * stuck in Rx.Detect (USB2 is unaffected as it isn't muxed).
> +	 */
> +	ret = qcom_uniphy_usb_mux_select(uniphy, true);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "failed to select USB mux\n");
> +
> +	uniphy->phy = devm_phy_create(dev, NULL, &uniphy_usb_ops);
> +	if (IS_ERR(uniphy->phy)) {
> +		ret = PTR_ERR(uniphy->phy);
> +		return dev_err_probe(dev, ret, "failed to create PHY\n");
> +	}

[Severity: Medium]
If devm_phy_create() or phy_pipe_clk_register() fail after the mux has been
selected, the function returns directly without restoring the hardware state.
Should there be a cleanup action (perhaps via devm_add_action_or_reset())
to restore the multiplexer to its default PCIe state on probe failure?

> +
> +	ret = phy_pipe_clk_register(uniphy, uniphy->phy->id);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "failed to register pipe clk\n");
> +
> +	phy_set_drvdata(uniphy->phy, uniphy);

[Severity: High]
Does this function also need to call platform_set_drvdata(pdev, uniphy)?
Currently qcom_uniphy_usb_remove() relies on platform_get_drvdata(pdev),
which would return NULL if not set here, and cause a NULL pointer dereference
when passed to qcom_uniphy_usb_mux_select().

> +
> +	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +
> +	ret = PTR_ERR_OR_ZERO(phy_provider);
> +
> +	return ret;
> +}

-- 
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Re: [PATCH v2 09/14] arm64: dts: qcom: ipq5018: Add clocks required for USB3 support

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The patch adds `assigned-clocks` and `assigned-clock-rates` to hardcode specific clock frequencies, which is completely undocumented in the commit message.
--

--- Patch [9]: [PATCH v2 09/14] arm64: dts: qcom: ipq5018: Add clocks required for USB3 support ---
commit 339a6b4d83bd552f4fe80b1ff4d6d41390119b3a
Author: George Moussalem <george.moussalem@outlook.com>

arm64: dts: qcom: ipq5018: Add clocks required for USB3 support

This commit adds the auxiliary and LFPS clocks to the USB controller node
in the IPQ5018 device tree to enable Super-Speed (USB3) mode. It also sets
default assigned clocks and clock rates for the controller.

> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -591,11 +591,21 @@ usb: usb@8a00000 {

[ ... ]

>  			clock-names = "core",
>  				      "iface",
>  				      "sleep",
> -				      "mock_utmi";
> +				      "mock_utmi",
> +				      "aux",
> +				      "lfps";
> +			assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
> +					  <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
> +					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> +			assigned-clock-rates = <200000000>,
> +					       <200000000>,
> +					       <60000000>;

[Severity: Medium]
The commit message mentions adding the aux and lfps clocks for USB3 support,
but does not document adding these assigned-clocks and assigned-clock-rates.

Could the commit message be updated to explain the rationale for forcing these
specific 200MHz and 60MHz frequencies during initialization?

-- 
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Re: [PATCH v2 03/14] arm64: dts: qcom: ipq5018: Add USB Super-Speed PHY node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing `platform_set_drvdata()` in the PHY driver probe function leads to a NULL pointer dereference on driver removal.
--

--- Patch [3]: [PATCH v2 03/14] arm64: dts: qcom: ipq5018: Add USB Super-Speed PHY node ---
commit 97eadd80983348dbdd8dbea710c772858c61ccf6
Author: George Moussalem <george.moussalem@outlook.com>

arm64: dts: qcom: ipq5018: Add USB Super-Speed PHY node

Add USB Super-Speed UNIPHY node and populate the USB DT clock on the GCC
node for the GCC to gate the PIPE clock supplied by the USB3 PHY.

> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -179,6 +179,23 @@ usbphy0: phy@5b000 {
>  			status = "disabled";
>  		};
>  
> +		usbphy1: phy@5d000 {
> +			compatible = "qcom,ipq5018-uniphy-usb-ss-phy";

[Severity: High]
Does enabling this PHY expose a NULL pointer dereference in the driver upon
removal?

Looking at the driver for this PHY in
drivers/phy/qualcomm/phy-qcom-uniphy-usb-ss-22ull.c, the
qcom_uniphy_usb_probe() function allocates the uniphy state but fails to save
it to the platform device:

drivers/phy/qualcomm/phy-qcom-uniphy-usb-ss-22ull.c:qcom_uniphy_usb_probe() {
    ...
	phy_set_drvdata(uniphy->phy, uniphy);

	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
    ...
}

When the driver is unbound, qcom_uniphy_usb_remove() retrieves a NULL pointer:

drivers/phy/qualcomm/phy-qcom-uniphy-usb-ss-22ull.c:qcom_uniphy_usb_remove() {
	struct uniphy_usb *uniphy = platform_get_drvdata(pdev);

	qcom_uniphy_usb_mux_select(uniphy, false);
}

This NULL pointer is then passed to qcom_uniphy_usb_mux_select(), causing a
crash.

Should a fix adding platform_set_drvdata(pdev, uniphy) be included to prevent
unbinding this device from causing a kernel oops?

-- 
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Re: [PATCH v2 07/14] dt-bindings: usb: qcom,snps-dwc3: Add clocks for USB3 on Qualcomm IPQ5018

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] DT schema backward compatibility violation: qcom,ipq5018-dwc3 mandates exactly 6 clocks, breaking existing High-Speed configurations.
--

--- Patch [7]: [PATCH v2 07/14] dt-bindings: usb: qcom,snps-dwc3: Add clocks for USB3 on Qualcomm IPQ5018 ---
commit 52d44d5749e478530dd0178f543b2a151efa9d68
Author: George Moussalem <george.moussalem@outlook.com>

dt-bindings: usb: qcom,snps-dwc3: Add clocks for USB3 on Qualcomm IPQ5018

This commit adds support for the aux and lfps clocks for the Qualcomm
IPQ5018 SoC in the snps-dwc3 device tree bindings. It creates a new
conditional block to specify these extra clocks and removes the compatible
string from a shared configuration.

> diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
> index e59fbfc1af71b..e3e22ac8462de 100644
> --- a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
> +++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
> @@ -181,6 +181,26 @@ allOf:
>              - const: sleep
>              - const: mock_utmi
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,ipq5018-dwc3
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 6

[Severity: Medium]
Will this break dtbs_check for existing High-Speed only device trees?

The commit message notes these new clocks are only required for USB
Super-Speed support, but setting minItems to 6 in the allOf conditional
block for qcom,ipq5018-dwc3 in
Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml mandates all 6
clocks for every device tree using this compatible string.

Since older configurations only provide 4 clocks, they will fail schema
validation.

Should minItems be set to 4 to preserve backward compatibility?

> +          maxItems: 6
> +        clock-names:
> +          items:
> +            - const: core
> +            - const: iface
> +            - const: sleep
> +            - const: mock_utmi
> +            - const: aux
> +            - const: lfps

-- 
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Re: [PATCH v2 12/14] arm64: dts: qcom: ipq5332: Enable USB Super-Speed PHY

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Incorrect Device Tree Compatible String
- [Low] Missing USB Controller PHY Reference / Device Tree Build Failure
--

--- Patch [12]: [PATCH v2 12/14] arm64: dts: qcom: ipq5332: Enable USB Super-Speed PHY ---
commit 3876ed72a1a7faf7ac5d0f75eed308d2c1085ec6
Author: Praveenkumar I <quic_ipkumar@quicinc.com>

arm64: dts: qcom: ipq5332: Enable USB Super-Speed PHY

This commit enables USB Super-Speed PHY support on the IPQ5332-RDP468
board. It overrides the PCIe PHY compatible string so the combo PHY is
handled by the USB3 PHY driver, and sets the required clocks and resets.

> diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
> index 25a70cd884c03..164f9a9a6c757 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts
[ ... ]
> @@ -100,3 +100,22 @@ &usbphy0 {
>  
>  	status = "okay";
>  };
> +
> +/* this combo PHY supports PCIe and USB3 */
> +&pcie0_phy {
> +	compatible = "qcom,ipq5018-uniphy-usb-ss-phy";

[Severity: High]
Does this compatible string use the wrong SoC version for this board?

Because this is an IPQ5332 board, using the IPQ5018 compatible string will
cause the phy-qcom-uniphy-usb-ss-22ull driver to write the IPQ5018
initialization sequence (targeting offsets like 0xa8) instead of the correct
IPQ5332 sequence (targeting 0x7C4 and 0x7E8). 

This will cause initialization to fail and may corrupt unrelated registers.

> +
> +	clocks = <&gcc GCC_PCIE3X1_PHY_AHB_CLK>,
> +		 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> +		 <&gcc GCC_USB0_PIPE_CLK>;
> +
> +	resets =  <&gcc GCC_USB0_PHY_BCR>;
> +
> +	qcom,phy-usb-mux-sel = <&tcsr 0x10540>;
> +
> +	vdd-supply = <&regulator_fixed_5p0>;
> +
> +	/delete-property/ num-lanes;
> +
> +	status = "okay";
> +};

[Severity: Low]
Is an override for the USB controller node missing from this file?

An earlier patch in this series adds phys = <&usbphy0>, <&usbphy1>; to
ipq5332.dtsi, but usbphy1 is never defined. This will cause a device tree
build failure due to the unresolved phandle.

Should this board file override the phys property in the &usb node to link
this newly configured &pcie0_phy combo PHY, replacing the non-existent
<&usbphy1> reference? 

Without this link, the USB controller will not use the combo PHY and will
remain degraded to High-Speed 2.0.

-- 
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Re: [PATCH v2 10/14] arm64: dts: qcom: ipq5332: Add Super-Speed UNIPHY to USB node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The patch introduces a reference to an undefined phandle `<&usbphy1>`, which will break devicetree compilation.
--

--- Patch [10]: [PATCH v2 10/14] arm64: dts: qcom: ipq5332: Add Super-Speed UNIPHY to USB node ---
commit 27afe7df7dfd63bf61a327eb2425e1692b59003b
Author: Praveenkumar I <quic_ipkumar@quicinc.com>

arm64: dts: qcom: ipq5332: Add Super-Speed UNIPHY to USB node

This patch adds the USB3 UNIPHY node to the USB controller node.
It also switches to the pipe clock supplied by the USB3 UNIPHY
instead of the UTMI clock.

> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> index 4c1016f5059e9..c2d384fa9df18 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> @@ -486,10 +486,8 @@ usb: usb@8a00000 {
>  					<&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>;
>  			interconnect-names = "usb-ddr", "apps-usb";
>  
> -			phys = <&usbphy0>;
> -			phy-names = "usb2-phy";
> -
> -			qcom,select-utmi-as-pipe-clk;
> +			phys = <&usbphy0>, <&usbphy1>;

[Severity: Low]
Does this introduce a reference to an undefined phandle <&usbphy1>? It
appears this might break devicetree compilation with a "Reference to
non-existent node or label" error when building a board that includes
this SoC .dtsi.

> +			phy-names = "usb2-phy", "usb3-phy";
>  
>  			tx-fifo-resize;
>  			snps,is-utmi-l1-suspend;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260812-ipq5018-usb3-v2-0-8f355d7ff0ef@outlook.com?part=10

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Re: [PATCH v2 05/14] arm64: dts: qcom: ipq5018: Flatten usb controller node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The flattened `qcom,snps-dwc3` node provides a `reg` memory region size (`0xe000`) that is too small to cover the qscratch wrapper registers, leading to a `-EBUSY` probe failure.
--

--- Patch [5]: [PATCH v2 05/14] arm64: dts: qcom: ipq5018: Flatten usb controller node ---
commit e097cafa032cb2e224c3052691cef507b25b9831
Author: George Moussalem <george.moussalem@outlook.com>

arm64: dts: qcom: ipq5018: Flatten usb controller node

This commit flattens the USB controller node and updates it to use the
latest bindings and flattened driver approach.

> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> index abd12b31a5147..7b8c9465f4442 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
[ ... ]
> -		usb: usb@8af8800 {
> -			compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
> -			reg = <0x08af8800 0x400>;
> -
> -			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "pwr_event",
> -					  "dp_hs_phy_irq",
> -					  "dm_hs_phy_irq";
> +		usb: usb@8a00000 {
> +			compatible = "qcom,ipq5018-dwc3", "qcom,snps-dwc3";
> +			reg = <0x08a00000 0xe000>;

[Severity: High]
Does this reg size correctly cover the qscratch wrapper registers?

The Qualcomm wrapper driver (dwc3-qcom.c) artificially expands the memory
resource size up to the 0xf8800 offset. Since the new flattened node here
only allocates a length of 0xe000 bytes, won't devm_ioremap_resource()
fail with -EBUSY during probe when the core driver requests a region that
extends beyond this parent device boundary?

-- 
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Re: [PATCH v2 13/14] arm64: dts: qcom: ipq5018: Enable USB Super-Speed PHY

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Power Management Regression: Missing `vdd-supply` on `usbphy0` causes USB 2.0 to lose power when `usbphy1` is suspended.
- [Medium] Missing Pin Control Configuration for the 5.0V Regulator GPIO.
- [Low] Misleading Devicetree Node Name for 5.0V Regulator.
--

--- Patch [13]: [PATCH v2 13/14] arm64: dts: qcom: ipq5018: Enable USB Super-Speed PHY ---
commit 0e34c498b874a88fdd6ad0b61268476b5d10f482
Author: George Moussalem <george.moussalem@outlook.com>

arm64: dts: qcom: ipq5018: Enable USB Super-Speed PHY
    
Add the 5V supply regulator and enable USB Super-Speed PHY support.

> diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
> index fcd5a078a2b08..0b147c9529149 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
> @@ -22,6 +22,14 @@ aliases {
>  	chosen {
>  		stdout-path = "serial0:115200n8";
>  	};
> +
> +	regulator_fixed_5p0: regulator-s0500 {

[Severity: Low]
This isn't a bug, but the node name regulator-s0500 implies a 500mV supply.

Since the regulator is explicitly configured for 5000000 microvolts, could 
this cause confusion? The fixed-regulator device tree binding schema typically 
prefers regulator-5v0 for a 5.0V regulator.

> +		compatible = "regulator-fixed";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		regulator-name = "fixed_5p0";
> +		gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;

[Severity: Medium]
Does this rely on the bootloader to leave the pin multiplexed as a GPIO?

There are no corresponding pinctrl-0 states defined or assigned here to
guarantee that gpio24 is multiplexed as a general-purpose GPIO rather than
an alternate function.

If the bootloader leaves it in the wrong electrical state, could USB power 
initialization silently fail?

> +	};
>  };

[ ... ]

> @@ -117,6 +125,12 @@ &usbphy0 {
>  	status = "okay";
>  };
>  
> +&usbphy1 {
> +	vdd-supply = <&regulator_fixed_5p0>;

[Severity: High]
Will this cause USB 2.0 devices to lose power when usbphy1 is suspended?

The single 5V GPIO regulator provides power for the port used by both
usbphy0 (USB 2.0) and usbphy1 (USB 3.0 SS). 

If usbphy1 is suspended by runtime PM (or inactive when only a USB 2.0 
device is connected), the regulator core will disable regulator_fixed_5p0 
because its only known consumer no longer requires it. 

Should usbphy0 also explicitly declare vdd-supply = <&regulator_fixed_5p0>
so the regulator core keeps the power on for USB 2.0 devices?

> +
> +	status = "okay";
> +};
> +
>  &xo_board_clk {
>  	clock-div = <4>;
>  	clock-mult = <1>;

-- 
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Re: [PATCH v2 11/14] arm64: dts: qcom: ipq5018: Add Super-Speed UNIPHY to USB node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Removing `qcom,select-utmi-as-pipe-clk` from the base `.dtsi` breaks USB initialization on boards that do not enable `usbphy1` (USB 2.0-only configurations).
--

--- Patch [11]: [PATCH v2 11/14] arm64: dts: qcom: ipq5018: Add Super-Speed UNIPHY to USB node ---
commit cad428ffac4e6a077748bf0a342a5d6933fea31b
Author: George Moussalem <george.moussalem@outlook.com>

arm64: dts: qcom: ipq5018: Add Super-Speed UNIPHY to USB node

This commit adds the USB3 UNIPHY node to the USB controller node in the
IPQ5018 device tree. It also removes the property that selects the UTMI
clock as the pipe clock, expecting the pipe clock to be supplied by the
USB3 UNIPHY instead.

> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> index 82e9ba6020ebd..87c3ade70217f 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -618,10 +618,8 @@ usb: usb@8a00000 {
>  
>  			resets = <&gcc GCC_USB0_BCR>;
>  
> -			phys = <&usbphy0>;
> -			phy-names = "usb2-phy";
> -
> -			qcom,select-utmi-as-pipe-clk;

[Severity: High]
Will removing this property break boards that do not enable usbphy1?

For example, looking at arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts,
it configures USB but lacks usbphy1:

&usb {
        dr_mode = "host";

        status = "okay";
};

Because qcom,select-utmi-as-pipe-clk is no longer in the base device tree,
the dwc3-qcom wrapper won't fall back to the UTMI clock.

Since usbphy1 is disabled on these USB 2.0-only configurations, the PHY
driver doesn't probe and the pipe clock is never provided. Does this cause
the dwc3 controller to hang while waiting for a non-existent clock during
initialization?

> +			phys = <&usbphy0>, <&usbphy1>;
> +			phy-names = "usb2-phy", "usb3-phy";
>  
>  			tx-fifo-resize;
>  			snps,is-utmi-l1-suspend;

-- 
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Re: [PATCH v2 04/14] arm64: dts: qcom: ipq5332: Flatten usb controller node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The flattened USB controller node specifies a 'reg' region that is too small, entirely excluding the QCOM wrapper register space that the driver relies on, which leads to probe failures.
--

--- Patch [4]: [PATCH v2 04/14] arm64: dts: qcom: ipq5332: Flatten usb controller node ---
commit 4c4cf3e503a7cae17e6181ac3e5f119bbfadc49e
Author: George Moussalem <george.moussalem@outlook.com>

arm64: dts: qcom: ipq5332: Flatten usb controller node

This commit flattens the usb controller node for ipq5332. It updates the
node to use the latest bindings and the flattened driver approach.

> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> @@ -456,16 +456,9 @@ qpic_nand: spi@79b0000 {
>  			status = "disabled";
>  		};
>  
> -		usb: usb@8af8800 {
> -			compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";
> -			reg = <0x08af8800 0x400>;
> -
> -			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "pwr_event",
> -					  "dp_hs_phy_irq",
> -					  "dm_hs_phy_irq";
> +		usb: usb@8a00000 {
> +			compatible = "qcom,ipq5332-dwc3", "qcom,snps-dwc3";
> +			reg = <0x08a00000 0xe000>;

[Severity: High]
Does this reg size need to be larger to cover the QCOM wrapper registers?

When transitioning to the flattened qcom,snps-dwc3 binding, the reg size is
set to 0xe000, which only covers the DWC3 core registers.

The dwc3-qcom.c wrapper driver relies on the qscratch wrapper registers which
reside at an offset of 0xf8800. The driver modifies the requested resource end
address to include this offset, which means devm_ioremap_resource() will
request a region that exceeds the 0xe000 byte resource specified here.

Could this overlap mismatch cause a resource conflict during
__request_region() and fail the probe with -EBUSY, rendering USB unusable
on the SoC? Should the region be expanded to cover the wrapper registers?

-- 
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Re: [PATCH v2 10/14] arm64: dts: qcom: ipq5332: Add Super-Speed UNIPHY to USB node

[Sergey Shtylyov]

On 8/12/26 12:34 PM, George Moussalem via B4 Relay wrote:

> From: Praveenkumar I <quic_ipkumar@quicinc.com>
> 
> Add the USB3 UNIPHY node to the USB controller node.

   You're not adding any nodes... Perhaps "refer to the USB3 UNIPHY node"?

> In addition, switch to the pipe clock supplied by the USB3 UNIPHY
> instead of the UTMI clock.
> 
> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> ---
>  arch/arm64/boot/dts/qcom/ipq5332.dtsi | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> index 664586979ec4..6253443c8d7f 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> @@ -523,10 +523,8 @@ usb: usb@8a00000 {
>  					<&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>;
>  			interconnect-names = "usb-ddr", "apps-usb";
>  
> -			phys = <&usbphy0>;
> -			phy-names = "usb2-phy";
> -
> -			qcom,select-utmi-as-pipe-clk;
> +			phys = <&usbphy0>, <&usbphy1>;
> +			phy-names = "usb2-phy", "usb3-phy";
>  
>  			tx-fifo-resize;
>  			snps,is-utmi-l1-suspend;
> 

MBR, Sergey


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Re: [PATCH v2 11/14] arm64: dts: qcom: ipq5018: Add Super-Speed UNIPHY to USB node

[Sergey Shtylyov]

On 8/12/26 12:34 PM, George Moussalem via B4 Relay wrote:

> From: George Moussalem <george.moussalem@outlook.com>
> 
> Add the USB3 UNIPHY node to the USB controller node.

   The same comment here...

> In addition, switch to the pipe clock supplied by the USB3 UNIPHY
> instead of the UTMI clock.
> 
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
> ---
>  arch/arm64/boot/dts/qcom/ipq5018.dtsi | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> index c98889a7c26c..01b8181ffa40 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -631,10 +631,8 @@ usb: usb@8a00000 {
>  
>  			resets = <&gcc GCC_USB0_BCR>;
>  
> -			phys = <&usbphy0>;
> -			phy-names = "usb2-phy";
> -
> -			qcom,select-utmi-as-pipe-clk;
> +			phys = <&usbphy0>, <&usbphy1>;
> +			phy-names = "usb2-phy", "usb3-phy";
>  
>  			tx-fifo-resize;
>  			snps,is-utmi-l1-suspend;
> 

MBR, Sergey


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