Linux-PHY Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: sashiko-bot@kernel.org
To: "Krishna Chaitanya Chundru" <krishna.chundru@oss.qualcomm.com>
Cc: linux-pci@vger.kernel.org, linux-phy@lists.infradead.org,
	neil.armstrong@linaro.org, vkoul@kernel.org, robh@kernel.org,
	conor+dt@kernel.org, devicetree@vger.kernel.org,
	olteanv@gmail.com
Subject: Re: [PATCH v4 6/6] phy: qcom: qmp-pcie: Add Nord Gen5x16 PCIe multi-PHY support
Date: Mon, 21 Sep 2026 05:58:46 +0000	[thread overview]
Message-ID: <20260921055846.B5BAE1F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260921-nord-v4-6-ed05c6e09240@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Unused static array variables due to macro typo
--

commit 426e06547f75580c252f2935af9323cd36b0aced
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

phy: qcom: qmp-pcie: Add Nord Gen5x16 PCIe multi-PHY support

This commit adds support for the Nord Gen5x16 bifurcated QMP PCIe PHY. It
adds configurations for x16, x8+x8, x8+x4+x4, and x8+x4+x2+x2 lane modes,
along with register programming and power sequencing.

> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-multiphy.c
[ ... ]
> +static const char * const nord_pciephy_port_a_nocsr_reset_l[] = {
> +	"port_a_nocsr",
> +};
> +
> +static const char * const nord_pciephy_port_b_nocsr_reset_l[] = {
> +	"port_b_nocsr",
> +};
[ ... ]
> +NORD_QMP_PCIE_PORT_CFG(a, pciephy_port_a_reg_l, nord_pciephy_port_a_pd_l,
> +		       nord_pciephy_port_a_reset_l, pciephy_port_a_nocsr_reset_l,
> +		       nord_pciephy_port_a_pipeclk_l, true);
> +NORD_QMP_PCIE_PORT_CFG(b, pciephy_port_b_reg_l, nord_pciephy_port_b_pd_l,
> +		       nord_pciephy_port_b_reset_l, pciephy_port_b_nocsr_reset_l,
> +		       nord_pciephy_port_b_pipeclk_l, true);

[Severity: Low]
Does this code accidentally pass pciephy_port_a_nocsr_reset_l instead of
nord_pciephy_port_a_nocsr_reset_l into the NORD_QMP_PCIE_PORT_CFG macro for
port a (and similarly for port b)?

This leaves the newly defined nord_pciephy_port_a_nocsr_reset_l and
nord_pciephy_port_b_nocsr_reset_l static arrays entirely unused.

This will trigger a -Wunused-variable compiler warning, which can cause
build failures when compiling the kernel with -Werror.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260921-nord-v4-0-ed05c6e09240@oss.qualcomm.com?part=6

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

  reply	other threads:[~2026-09-21  5:58 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-21  5:37 [PATCH v4 0/6] Add PCIe support for Qualcomm Nord platform Krishna Chaitanya Chundru
2026-09-21  5:37 ` [PATCH v4 1/6] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding Krishna Chaitanya Chundru
2026-09-21  5:43   ` sashiko-bot
2026-09-24 13:22   ` Krzysztof Kozlowski
2026-09-25  4:08     ` Krishna Chaitanya Chundru
2026-09-25  6:28       ` Krzysztof Kozlowski
2026-09-25  6:36   ` Krzysztof Kozlowski
2026-09-21  5:37 ` [PATCH v4 2/6] dt-bindings: pci: qcom: add Nord PCIe controller compatible Krishna Chaitanya Chundru
2026-09-21  5:42   ` sashiko-bot
2026-09-21  5:37 ` [PATCH v4 3/6] PCI: qcom: Add Nord PCIe controller support Krishna Chaitanya Chundru
2026-09-21  5:46   ` sashiko-bot
2026-09-21  5:37 ` [PATCH v4 4/6] phy: qcom: qmp: Move qphy_setbits/clrbits/checkbits to common header Krishna Chaitanya Chundru
2026-09-21  5:42   ` sashiko-bot
2026-09-21  5:37 ` [PATCH v4 5/6] phy: qcom: qmp-pcie: Refactor common multiphy handling Krishna Chaitanya Chundru
2026-09-21  5:48   ` sashiko-bot
2026-09-22  8:12   ` Shawn Guo
2026-09-25 15:23   ` Manivannan Sadhasivam
2026-09-21  5:37 ` [PATCH v4 6/6] phy: qcom: qmp-pcie: Add Nord Gen5x16 PCIe multi-PHY support Krishna Chaitanya Chundru
2026-09-21  5:58   ` sashiko-bot [this message]
2026-09-22  8:12   ` Shawn Guo
2026-09-25 15:25   ` Manivannan Sadhasivam
2026-09-21  6:30 ` [PATCH v4 0/6] Add PCIe support for Qualcomm Nord platform Qiang Yu
2026-09-21  7:37   ` Konrad Dybcio
2026-09-22  9:18     ` Qiang Yu
2026-09-22  8:13 ` Shawn Guo
2026-10-03  9:36 ` (subset) " Vinod Koul

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260921055846.B5BAE1F000FF@smtp.kernel.org \
    --to=sashiko-bot@kernel.org \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=krishna.chundru@oss.qualcomm.com \
    --cc=linux-pci@vger.kernel.org \
    --cc=linux-phy@lists.infradead.org \
    --cc=neil.armstrong@linaro.org \
    --cc=olteanv@gmail.com \
    --cc=robh@kernel.org \
    --cc=sashiko-reviews@lists.linux.dev \
    --cc=vkoul@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox