From: Tingwei Zhang <quic_tingweiz@quicinc.com>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Ziyue Zhang <quic_ziyuzhan@quicinc.com>
Cc: <vkoul@kernel.org>, <kishon@kernel.org>, <robh+dt@kernel.org>,
<manivannan.sadhasivam@linaro.org>, <bhelgaas@google.com>,
<kw@linux.com>, <lpieralisi@kernel.org>,
<quic_qianyu@quicinc.com>, <conor+dt@kernel.org>,
<neil.armstrong@linaro.org>, <andersson@kernel.org>,
<konradybcio@kernel.org>, <quic_shashim@quicinc.com>,
<quic_kaushalk@quicinc.com>, <quic_tdas@quicinc.com>,
<quic_aiquny@quicinc.com>, <kernel@quicinc.com>,
<linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>
Subject: Re: [PATCH 4/5] arm64: dts: qcom: qcs8300: enable pcie0 for QCS8300
Date: Fri, 15 Nov 2024 12:59:12 +0800 [thread overview]
Message-ID: <288be342-952b-4210-afe7-6e194dfd54a9@quicinc.com> (raw)
In-Reply-To: <26943ea3-109c-473d-818b-2a08dba859ab@oss.qualcomm.com>
On 11/14/2024 9:03 PM, Konrad Dybcio wrote:
> On 14.11.2024 1:10 PM, Dmitry Baryshkov wrote:
>> On Thu, Nov 14, 2024 at 05:54:08PM +0800, Ziyue Zhang wrote:
>>> Add configurations in devicetree for PCIe0, including registers, clocks,
>>> interrupts and phy setting sequence.
>>>
>>> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 44 +++++-
>>> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 176 ++++++++++++++++++++++
>>> 2 files changed, 219 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
>>> index 7eed19a694c3..9d7c8555ed38 100644
>>> --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
>>> +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
>>> @@ -213,7 +213,7 @@ vreg_l9c: ldo9 {
>>> &gcc {
>>
>> The patch doesn't seem to update the gcc node in qcs8300.dtsi. Is there
>> any reason to have the clocks property in the board data file?
>
> Definitely not. Ziyue, please move that change to the soc dtsi
Gcc node is updated in board device tree due to sleep_clk is defined in
board device tree. Sleep_clk is from PMIC instead SoC so we were
requested to move sleep_clk to board device tree in previous review [1].
[1]https://lore.kernel.org/all/10914199-1e86-4a2e-aec8-2a48cc49ef14@kernel.org/
>
> Konrad
--
Thanks,
Tingwei
--
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next prev parent reply other threads:[~2024-11-15 4:59 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-14 9:54 [PATCH 0/5] pci: qcom: Add QCS8300 PCIe support Ziyue Zhang
2024-11-14 9:54 ` [PATCH 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2 Ziyue Zhang
2024-11-15 17:56 ` Rob Herring (Arm)
2024-11-14 9:54 ` [PATCH 2/5] phy: qcom-qmp-pcie: add dual lane PHY support for QCS8300 Ziyue Zhang
2024-11-15 20:49 ` Dmitry Baryshkov
2024-11-14 9:54 ` [PATCH 3/5] dt-bindings: PCI: qcom,pcie-sa8775p: document qcs8300 Ziyue Zhang
2024-11-15 17:56 ` Rob Herring (Arm)
2024-11-14 9:54 ` [PATCH 4/5] arm64: dts: qcom: qcs8300: enable pcie0 for QCS8300 Ziyue Zhang
2024-11-14 12:10 ` Dmitry Baryshkov
2024-11-14 13:03 ` Konrad Dybcio
2024-11-15 4:59 ` Tingwei Zhang [this message]
2024-11-15 6:26 ` Dmitry Baryshkov
2024-11-15 6:42 ` Tingwei Zhang
2024-11-15 7:03 ` Dmitry Baryshkov
2024-11-15 7:16 ` Tingwei Zhang
2024-11-15 7:36 ` Dmitry Baryshkov
2024-11-14 13:02 ` Konrad Dybcio
2024-11-15 6:46 ` Manivannan Sadhasivam
2024-11-27 9:56 ` Ziyue Zhang
2024-11-14 9:54 ` [PATCH 5/5] arm64: dts: qcom: qcs8300: enable pcie1 " Ziyue Zhang
2024-11-14 13:03 ` Konrad Dybcio
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