Re: [PATCH 4/5] arm64: dts: qcom: qcs8300: enable pcie0 for QCS8300

[Ziyue Zhang <quic_ziyuzhan@quicinc.com>]

On 11/14/2024 9:02 PM, Konrad Dybcio wrote:
> On 14.11.2024 10:54 AM, Ziyue Zhang wrote:
>> Add configurations in devicetree for PCIe0, including registers, clocks,
>> interrupts and phy setting sequence.
>>
>> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/qcs8300-ride.dts |  44 +++++-
>>   arch/arm64/boot/dts/qcom/qcs8300.dtsi     | 176 ++++++++++++++++++++++
> This implies this patch should be two separate ones
>
>
> [...]
>
>
>> +&tlmm {
>> +	pcie0_default_state: pcie0-default-state {
>> +		perst-pins {
>> +			pins = "gpio2";
>> +			function = "gpio";
>> +			drive-strength = <2>;
>> +			bias-pull-down;
>> +		};
>> +
>> +		clkreq-pins {
>> +			pins = "gpio1";
>> +			function = "pcie0_clkreq";
>> +			drive-strength = <2>;
>> +			bias-pull-up;
>> +		};
>> +
>> +		wake-pins {
>> +			pins = "gpio0";
> Sorting these in an increasing order would be welcome
>
>
>>   
>> +		pcie0: pci@1c00000 {
>> +			compatible = "qcom,pcie-qcs8300","qcom,pcie-sa8775p";
> Missing ' ' after ','
>
>> +			reg = <0x0 0x01c00000 0x0 0x3000>,
>> +			      <0x0 0x40000000 0x0 0xf20>,
>> +			      <0x0 0x40000f20 0x0 0xa8>,
>> +			      <0x0 0x40001000 0x0 0x4000>,
>> +			      <0x0 0x40100000 0x0 0x100000>,
>> +			      <0x0 0x01c03000 0x0 0x1000>;
>> +
>> +			reg-names = "parf",
>> +				    "dbi",
>> +				    "elbi",
>> +				    "atu",
>> +				    "config",
>> +				    "mhi";
>> +
>> +			device_type = "pci";
> Please try to match the style in x1e80100, it's mostly coherent but
> things like newlines differ, which is tiny but mildly annoying
>
>> +
>> +			#address-cells = <3>;
>> +			#size-cells = <2>;
>> +			ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
>> +				 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
> Looks like there's a bit more space in there
>> +			bus-range = <0x00 0xff>;
>> +
>> +			dma-coherent;
>> +
>> +			linux,pci-domain = <0>;
>> +			num-lanes = <2>;
>> +
>> +			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> +			interrupt-names = "msi0",
>> +					  "msi1",
>> +					  "msi2",
>> +					  "msi3",
>> +					  "msi4",
>> +					  "msi5",
>> +					  "msi6",
>> +					  "msi7";
> Please also add a "global" interrupt.. looks like it's GIC_SPI 166, but
> please confirm
> okay
>> +
>> +			#interrupt-cells = <1>;
>> +			interrupt-map-mask = <0 0 0 0x7>;
>> +			interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
>> +					<0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
>> +					<0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
>> +					<0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> +			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
>> +				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>> +				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
>> +				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
>> +				 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
>> +
>> +			clock-names = "aux",
>> +				      "cfg",
>> +				      "bus_master",
>> +				      "bus_slave",
>> +				      "slave_q2a";
>> +
>> +			assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
>> +			assigned-clock-rates = <19200000>;
>> +
>> +			interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
> QCOM_ICC_TAG_ALWAYS
> okay
>> +					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
> QCOM_ICC_TAG_ACTIVE_ONLY
>
> [...]
> okay
>> +
>> +			pcieport0: pcie@0 {
>> +				device_type = "pci";
>> +				reg = <0x0 0x0 0x0 0x0 0x0>;
>> +				#address-cells = <3>;
>> +				#size-cells = <2>;
>> +				ranges;
>> +				bus-range = <0x01 0xff>;
>> +			};
> Are you going to use this? If not, please drop

its required by wlan driver we need it

BRs

Ziyue

>
>> +		};
>> +
>> +		pcie0_phy: phy@1c04000 {
>> +			compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy";
>> +			reg = <0x0 0x1c04000 0x0 0x2000>;
>> +
>> +			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> This clock goes to the RC, it should be _PHY_AUX (which you put below
> as phy_aux), please replace it.
> will do it
>> +				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>> +				 <&gcc GCC_PCIE_CLKREF_EN>,
>> +				 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
>> +				 <&gcc GCC_PCIE_0_PIPE_CLK>,
>> +				 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
>> +				 <&gcc GCC_PCIE_0_PHY_AUX_CLK>;
>> +
>> +			clock-names = "aux",
>> +				      "cfg_ahb",
>> +				      "ref",
>> +				      "rchng",
>> +				      "pipe",
>> +				      "pipediv2",
>> +				      "phy_aux";
> Konrad

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