[PATCH 0/2] phy: qcom-qusb2: sort out register layouts

[PATCH 0/2] phy: qcom-qusb2: sort out register layouts

[Dmitry Baryshkov]

IPQ6018 and MSM8996 use the same register layout, however for historical
reasons ipq6018_regs_layout ended up correctly definig TEST1 register at
0x98 (because platforms using that layout didn't use autoresume), while
msm8996_regs_layout used TEST_CTRL offset (0xb8) for the TEST1 layout
entry. Fix handling of the autoresume register and definitions of those
regs layouts.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
Dmitry Baryshkov (2):
      phy: qcom-qusb2: don't unrelated bits if autoresume is not used
      phy: qcom-qusb2: fix autoresume handling

 drivers/phy/qualcomm/phy-qcom-qusb2.c | 44 +++++++++++++++++------------------
 1 file changed, 21 insertions(+), 23 deletions(-)
---
base-commit: be5c93fa674f0fc3c8f359c2143abce6bbb422e6
change-id: 20260702-fix-qusb2-3600a65bfcae

Best regards,
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[PATCH 1/2] phy: qcom-qusb2: don't unrelated bits if autoresume is not used

[Dmitry Baryshkov]

The IPQ6018 and QCS615 platforms don't need to toggle the autoresume
bit. However the driver ended up toggling a completely unrelated bit
(BIT 0 in the TEST1 register) instead of skipping the autoresume bit
programmign at all.

Update those two platforms to specify 0 mask for the autoresume_en and
skip programming if the mask is 0.

Fixes: 2cfbe6765b7a ("phy: qcom-qusb2: add QUSB2 support for IPQ6018")
Fixes: 8adbf20e0502 ("phy: qcom-qusb2: Add support for QCS615")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/phy/qualcomm/phy-qcom-qusb2.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index eb93015be841..1109c480843e 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -341,7 +341,7 @@ static const struct qusb2_phy_cfg ipq6018_phy_cfg = {
 	.disable_ctrl   = POWER_DOWN,
 	.mask_core_ready = PLL_LOCKED,
 	/* autoresume not used */
-	.autoresume_en   = BIT(0),
+	.autoresume_en   = 0,
 };
 
 static const struct qusb2_phy_cfg qcs615_phy_cfg = {
@@ -352,7 +352,7 @@ static const struct qusb2_phy_cfg qcs615_phy_cfg = {
 	.disable_ctrl   = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
 	.mask_core_ready = PLL_LOCKED,
 	/* autoresume not used */
-	.autoresume_en   = BIT(0),
+	.autoresume_en   = 0,
 };
 
 static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
@@ -677,7 +677,7 @@ static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev)
 	}
 
 	/* enable phy auto-resume only if device is connected on bus */
-	if (qphy->mode != PHY_MODE_INVALID) {
+	if (qphy->mode != PHY_MODE_INVALID && cfg->autoresume_en) {
 		qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
 			      cfg->autoresume_en);
 		/* Autoresume bit has to be toggled in order to enable it */

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Re: [PATCH 1/2] phy: qcom-qusb2: don't unrelated bits if autoresume is not used

[Konrad Dybcio]

On 7/2/26 1:40 PM, Dmitry Baryshkov wrote:
> The IPQ6018 and QCS615 platforms don't need to toggle the autoresume
> bit.

why?

Konrad

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Re: [PATCH 1/2] phy: qcom-qusb2: don't unrelated bits if autoresume is not used

[Dmitry Baryshkov]

On Thu, Jul 02, 2026 at 02:00:06PM +0200, Konrad Dybcio wrote:
> On 7/2/26 1:40 PM, Dmitry Baryshkov wrote:
> > The IPQ6018 and QCS615 platforms don't need to toggle the autoresume
> > bit.
> 
> why?

Here I have no idea, the HPG is unspecific, exact details are to be
defined somewhere else. The platforms, when they were added, just stated
that autoresume is to be skipped. Maybe original developers (in cc) can
answer this question. Anyway, if autoresume is to be toggled, it should
be coming as a separate fixup. I can reorder the patches though, so that
at least register layout is correct.


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Re: [PATCH 1/2] phy: qcom-qusb2: don't unrelated bits if autoresume is not used

[Konrad Dybcio]

On 7/2/26 2:21 PM, Dmitry Baryshkov wrote:
> On Thu, Jul 02, 2026 at 02:00:06PM +0200, Konrad Dybcio wrote:
>> On 7/2/26 1:40 PM, Dmitry Baryshkov wrote:
>>> The IPQ6018 and QCS615 platforms don't need to toggle the autoresume
>>> bit.
>>
>> why?
> 
> Here I have no idea, the HPG is unspecific, exact details are to be
> defined somewhere else. The platforms, when they were added, just stated
> that autoresume is to be skipped. Maybe original developers (in cc) can
> answer this question. Anyway, if autoresume is to be toggled, it should
> be coming as a separate fixup. I can reorder the patches though, so that
> at least register layout is correct.

+Krishna, Wesley?

Konrad

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Re: [PATCH 1/2] phy: qcom-qusb2: don't unrelated bits if autoresume is not used

[Krishna Kurapati]

On 7/2/2026 5:54 PM, Konrad Dybcio wrote:
> On 7/2/26 2:21 PM, Dmitry Baryshkov wrote:
>> On Thu, Jul 02, 2026 at 02:00:06PM +0200, Konrad Dybcio wrote:
>>> On 7/2/26 1:40 PM, Dmitry Baryshkov wrote:
>>>> The IPQ6018 and QCS615 platforms don't need to toggle the autoresume
>>>> bit.
>>>
>>> why?
>>
>> Here I have no idea, the HPG is unspecific, exact details are to be
>> defined somewhere else. The platforms, when they were added, just stated
>> that autoresume is to be skipped. Maybe original developers (in cc) can
>> answer this question. Anyway, if autoresume is to be toggled, it should
>> be coming as a separate fixup. I can reorder the patches though, so that
>> at least register layout is correct.
> 
> +Krishna, Wesley?
> 
I checked downstream driver code and I see this:

1. If the phy is qusb2 v2, then we are setting and clearing BIT(0) of 
TEST1 register.
2. If the phy is qusb2, then we are setting and clearing BIT(3) of 
TEST_CTRL register.

For both IPQ6018 and QCS615, I checked and its BIT(3) of TEST_CTRL 
register to be set.

For msm8998 it is BIT(0) of TEST1 register.

Also for qcs615, in downstream code, I see that auto-resume is being 
set. Its a mistake from my end when I added [1].

[1]: 
https://lore.kernel.org/all/20241014084432.3310114-5-quic_kriskura@quicinc.com/

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Krishna,

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Re: [PATCH 1/2] phy: qcom-qusb2: don't unrelated bits if autoresume is not used

[Dmitry Baryshkov]

On Thu, Jul 02, 2026 at 07:13:29PM +0530, Krishna Kurapati wrote:
> 
> 
> On 7/2/2026 5:54 PM, Konrad Dybcio wrote:
> > On 7/2/26 2:21 PM, Dmitry Baryshkov wrote:
> > > On Thu, Jul 02, 2026 at 02:00:06PM +0200, Konrad Dybcio wrote:
> > > > On 7/2/26 1:40 PM, Dmitry Baryshkov wrote:
> > > > > The IPQ6018 and QCS615 platforms don't need to toggle the autoresume
> > > > > bit.
> > > > 
> > > > why?
> > > 
> > > Here I have no idea, the HPG is unspecific, exact details are to be
> > > defined somewhere else. The platforms, when they were added, just stated
> > > that autoresume is to be skipped. Maybe original developers (in cc) can
> > > answer this question. Anyway, if autoresume is to be toggled, it should
> > > be coming as a separate fixup. I can reorder the patches though, so that
> > > at least register layout is correct.
> > 
> > +Krishna, Wesley?
> > 

[..]

> 
> Also for qcs615, in downstream code, I see that auto-resume is being set.
> Its a mistake from my end when I added [1].
> 
> [1]: https://lore.kernel.org/all/20241014084432.3310114-5-quic_kriskura@quicinc.com/

Ok, I'll fix it in v2.

Do we need to enable autoresume for IPQ6018 too?

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Re: [PATCH 1/2] phy: qcom-qusb2: don't unrelated bits if autoresume is not used

[Konrad Dybcio]

On 7/2/26 1:40 PM, Dmitry Baryshkov wrote:
> The IPQ6018 and QCS615 platforms don't need to toggle the autoresume
> bit. However the driver ended up toggling a completely unrelated bit
> (BIT 0 in the TEST1 register) instead of skipping the autoresume bit
> programmign at all.
> 
> Update those two platforms to specify 0 mask for the autoresume_en and
> skip programming if the mask is 0.

I'd say that we should just use the correct value of BIT(3) for both
and order this patch after the other one

Konrad

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[PATCH 2/2] phy: qcom-qusb2: fix autoresume handling

[Dmitry Baryshkov]

There is a confusion regarding the autoresume bit. Some verions of the
QUSB2 PHY have it in the TEST1 register, while on the others it is a
part of the TEST_CTRL register. When adding support for autoresume bit,
the code attempted to simplify the handling of those registers, putting
both registers to the TEST1 layout entry. In the end,
ipq6018_regs_layout ended up correctly definig TEST1 register at 0x98
(because platforms using that layout didn't use autoresume), while
msm8996_regs_layout used TEST_CTRL offset (0xb8) for the TEST1
layout entry.

Update the platform data to specify the register to be used for
autoresume handling, define both TEST1 and TEST_CTRL registers and merge
ipq6018_regs_layout and msm8996_regs_layout which become identical
afterwards.

Fixes: 891a96f65ac3 ("phy: qcom-qusb2: Add support for runtime PM")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
 drivers/phy/qualcomm/phy-qcom-qusb2.c | 38 +++++++++++++++++------------------
 1 file changed, 18 insertions(+), 20 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index 1109c480843e..ff3bc8fc2f18 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -131,6 +131,7 @@ enum qusb2phy_reg_layout {
 	QUSB2PHY_PORT_TUNE5,
 	QUSB2PHY_PORT_TEST1,
 	QUSB2PHY_PORT_TEST2,
+	QUSB2PHY_PORT_TEST_CTRL,
 	QUSB2PHY_PORT_POWERDOWN,
 	QUSB2PHY_INTR_CTRL,
 };
@@ -164,19 +165,6 @@ static const struct qusb2_phy_init_tbl qcs615_init_tbl[] = {
 	QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
 };
 
-static const unsigned int ipq6018_regs_layout[] = {
-	[QUSB2PHY_PLL_STATUS]              = 0x38,
-	[QUSB2PHY_PORT_TUNE1]              = 0x80,
-	[QUSB2PHY_PORT_TUNE2]              = 0x84,
-	[QUSB2PHY_PORT_TUNE3]              = 0x88,
-	[QUSB2PHY_PORT_TUNE4]              = 0x8C,
-	[QUSB2PHY_PORT_TUNE5]              = 0x90,
-	[QUSB2PHY_PORT_TEST1]              = 0x98,
-	[QUSB2PHY_PORT_TEST2]              = 0x9C,
-	[QUSB2PHY_PORT_POWERDOWN]          = 0xB4,
-	[QUSB2PHY_INTR_CTRL]               = 0xBC,
-};
-
 static const unsigned int msm8996_regs_layout[] = {
 	[QUSB2PHY_PLL_STATUS]		= 0x38,
 	[QUSB2PHY_PORT_TUNE1]		= 0x80,
@@ -184,8 +172,9 @@ static const unsigned int msm8996_regs_layout[] = {
 	[QUSB2PHY_PORT_TUNE3]		= 0x88,
 	[QUSB2PHY_PORT_TUNE4]		= 0x8c,
 	[QUSB2PHY_PORT_TUNE5]		= 0x90,
-	[QUSB2PHY_PORT_TEST1]		= 0xb8,
+	[QUSB2PHY_PORT_TEST1]		= 0x98,
 	[QUSB2PHY_PORT_TEST2]		= 0x9c,
+	[QUSB2PHY_PORT_TEST_CTRL]	= 0xb8,
 	[QUSB2PHY_PORT_POWERDOWN]	= 0xb4,
 	[QUSB2PHY_INTR_CTRL]		= 0xbc,
 };
@@ -294,6 +283,7 @@ struct qusb2_phy_cfg {
 	unsigned int mask_core_ready;
 	unsigned int disable_ctrl;
 	unsigned int autoresume_en;
+	bool autoresume_in_test_ctrl;
 
 	/* true if PHY has PLL_TEST register to select clk_scheme */
 	bool has_pll_test;
@@ -318,6 +308,7 @@ static const struct qusb2_phy_cfg msm8996_phy_cfg = {
 	.disable_ctrl	= (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
 	.mask_core_ready = PLL_LOCKED,
 	.autoresume_en	 = BIT(3),
+	.autoresume_in_test_ctrl = true,
 };
 
 static const struct qusb2_phy_cfg msm8998_phy_cfg = {
@@ -336,7 +327,7 @@ static const struct qusb2_phy_cfg msm8998_phy_cfg = {
 static const struct qusb2_phy_cfg ipq6018_phy_cfg = {
 	.tbl            = ipq6018_init_tbl,
 	.tbl_num        = ARRAY_SIZE(ipq6018_init_tbl),
-	.regs           = ipq6018_regs_layout,
+	.regs           = msm8996_regs_layout,
 
 	.disable_ctrl   = POWER_DOWN,
 	.mask_core_ready = PLL_LOCKED,
@@ -347,7 +338,7 @@ static const struct qusb2_phy_cfg ipq6018_phy_cfg = {
 static const struct qusb2_phy_cfg qcs615_phy_cfg = {
 	.tbl            = qcs615_init_tbl,
 	.tbl_num        = ARRAY_SIZE(qcs615_init_tbl),
-	.regs           = ipq6018_regs_layout,
+	.regs           = msm8996_regs_layout,
 
 	.disable_ctrl   = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
 	.mask_core_ready = PLL_LOCKED,
@@ -379,6 +370,7 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = {
 	.disable_ctrl	= (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
 	.mask_core_ready = PLL_LOCKED,
 	.autoresume_en	 = BIT(3),
+	.autoresume_in_test_ctrl = true,
 };
 
 static const struct qusb2_phy_cfg sm6115_phy_cfg = {
@@ -391,6 +383,7 @@ static const struct qusb2_phy_cfg sm6115_phy_cfg = {
 	.disable_ctrl	= (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
 	.mask_core_ready = PLL_LOCKED,
 	.autoresume_en	 = BIT(3),
+	.autoresume_in_test_ctrl = true,
 };
 
 static const char * const qusb2_phy_vreg_names[] = {
@@ -678,11 +671,16 @@ static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev)
 
 	/* enable phy auto-resume only if device is connected on bus */
 	if (qphy->mode != PHY_MODE_INVALID && cfg->autoresume_en) {
-		qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
-			      cfg->autoresume_en);
+		unsigned int reg;
+
+		if (cfg->autoresume_in_test_ctrl)
+			reg = cfg->regs[QUSB2PHY_PORT_TEST_CTRL];
+		else
+			reg = cfg->regs[QUSB2PHY_PORT_TEST1];
+
+		qusb2_setbits(qphy->base, reg, cfg->autoresume_en);
 		/* Autoresume bit has to be toggled in order to enable it */
-		qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
-			      cfg->autoresume_en);
+		qusb2_clrbits(qphy->base, reg, cfg->autoresume_en);
 	}
 
 	if (!qphy->has_se_clk_scheme)

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Re: [PATCH 2/2] phy: qcom-qusb2: fix autoresume handling

[Konrad Dybcio]

On 7/2/26 1:40 PM, Dmitry Baryshkov wrote:
> There is a confusion regarding the autoresume bit. Some verions of the
> QUSB2 PHY have it in the TEST1 register, while on the others it is a
> part of the TEST_CTRL register. When adding support for autoresume bit,
> the code attempted to simplify the handling of those registers, putting
> both registers to the TEST1 layout entry. In the end,
> ipq6018_regs_layout ended up correctly definig TEST1 register at 0x98
> (because platforms using that layout didn't use autoresume), while
> msm8996_regs_layout used TEST_CTRL offset (0xb8) for the TEST1
> layout entry.
> 
> Update the platform data to specify the register to be used for
> autoresume handling, define both TEST1 and TEST_CTRL registers and merge
> ipq6018_regs_layout and msm8996_regs_layout which become identical
> afterwards.
> 
> Fixes: 891a96f65ac3 ("phy: qcom-qusb2: Add support for runtime PM")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad


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