* [PATCH v4 01/16] dt-bindings: phy: rockchip-usbdp: add improved ports scheme
From: Sebastian Reichel @ 2026-04-28 16:13 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260428-rockchip-usbdp-cleanup-v4-0-7775671ece22@collabora.com>
Currently the Rockchip USBDP PHY is missing a documented port scheme.
Meanwhile upstream RK3588 DTS files are a bit messy and use different
port schemes. The upstream USBDP PHY Linux kernel driver does not yet
parse the ports at all and thus does not create any implicit ABI either.
But with the current mess it is not possible to properly support USB-C
DP AltMode. Thus this introduces a proper port scheme following roughly
the ports design of the Qualcomm QMP USB4-USB3-DP PHY controller binding
with a slight difference that there is an additional port for the
USB-C SBU port as the Rockchip USB-DP PHY also contains the SBU mux.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
.../bindings/phy/phy-rockchip-usbdp.yaml | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml
index 8b7059d5b182..f728acf057e4 100644
--- a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml
@@ -114,6 +114,29 @@ properties:
A port node to link the PHY to a TypeC controller for the purpose of
handling orientation switching.
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Output endpoint of the PHY for USB (or DP when configured into 4 lane
+ mode), which should point to the superspeed port of a USB connector.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Incoming endpoint from the USB controller
+
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Incoming endpoint from the DisplayPort controller
+
+ port@3:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Output endpoint of the PHY for DP, which should either point to the
+ SBU port of a USB-C connector or a DisplayPort connector input port.
+
required:
- compatible
- reg
--
2.53.0
--
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^ permalink raw reply related
* [PATCH v4 02/16] phy: rockchip: usbdp: Do not loose USB3 PHY status
From: Sebastian Reichel @ 2026-04-28 16:13 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260428-rockchip-usbdp-cleanup-v4-0-7775671ece22@collabora.com>
By default (i.e. without manually enabling runtime PM) DWC3 requests the
USB3 PHY once and keeps it enabled all the time. When DisplayPort is
being requested later on, a mode change is needed. This re-initializes
the PHY. During re-initialization the status variable has incorrectly
been cleared, which means the tracking information for USB3 ist lost.
This is not an immediate problem, since the DP side keeps the PHY
enabled. But once DP is toggled off, the whole PHY will be disabled.
This is a problem, because the USB side still needs it powered.
Fix things by not clearing the status flags.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index fba35510d88c..744cc7c642f4 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -1009,7 +1009,6 @@ static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode)
rk_udphy_u3_port_disable(udphy, false);
} else if (udphy->mode_change) {
udphy->mode_change = false;
- udphy->status = UDPHY_MODE_NONE;
if (udphy->mode == UDPHY_MODE_DP)
rk_udphy_u3_port_disable(udphy, true);
--
2.53.0
--
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^ permalink raw reply related
* Re: [PATCH v22 5/8] dt-bindings: phy: Add Freescale iMX8MQ DP and HDMI PHY
From: Luca Ceresoli @ 2026-04-28 12:21 UTC (permalink / raw)
To: Laurentiu Palcu
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, dri-devel, devicetree, linux-kernel, linux-phy,
imx, linux-arm-kernel, linux, Alexander Stein, Ying Liu
In-Reply-To: <f6rf5d6nhglkwendf5yvaklfn2ovlwkqstsz7vvl5zefibtiun@wic7bchohmwv>
Hello Laurentiu,
On Mon Apr 27, 2026 at 4:35 PM CEST, Laurentiu Palcu wrote:
> Hi Luca,
>
> On Mon, Apr 27, 2026 at 02:59:47PM +0200, Luca Ceresoli wrote:
>> Hello Laurentiu,
>>
>> On Fri Apr 24, 2026 at 1:07 PM CEST, Laurentiu Palcu wrote:
>> > From: Sandor Yu <Sandor.yu@nxp.com>
>> >
>> > Add bindings for Freescale iMX8MQ DP and HDMI PHY.
>> >
>> > Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
>> > Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
>> > ---
>> > .../bindings/phy/fsl,imx8mq-hdptx-phy.yaml | 80 ++++++++++++++++++++++
>> > 1 file changed, 80 insertions(+)
>> >
>> > diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-hdptx-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mq-hdptx-phy.yaml
>> > new file mode 100644
>> > index 0000000000000..a24435139b8b3
>> > --- /dev/null
>> > +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-hdptx-phy.yaml
>> > @@ -0,0 +1,80 @@
>> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> > +%YAML 1.2
>> > +---
>> > +$id: http://devicetree.org/schemas/phy/fsl,imx8mq-hdptx-phy.yaml#
>> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> > +
>> > +title: Cadence HDP-TX DP/HDMI PHY for Freescale i.MX8MQ SoC
>> > +
>> > +maintainers:
>> > + - Sandor Yu <sandor.yu@nxp.com>
>>
>> Based on what you said in the cover, I guess this line will have to be
>> changed. Are you willing to maintain this binding?
>
> Yes, I'll update it in the next iteration.
>
>>
>> > +description:
>> > + The Cadence HDP-TX DP/HDMI PHY is a child node of the MHDP8501 bridge,
>> > + sharing the same MMIO region as the parent bridge node.
>> > +
>> > +properties:
>> > + compatible:
>> > + const: fsl,imx8mq-hdptx-phy
>> > +
>> > + clocks:
>> > + items:
>> > + - description: PHY reference clock.
>> > + - description: APB clock.
>> > +
>> > + clock-names:
>> > + items:
>> > + - const: ref
>> > + - const: apb
>> > +
>> > + "#phy-cells":
>> > + const: 0
>> > +
>> > +required:
>> > + - compatible
>> > + - clocks
>> > + - clock-names
>> > + - "#phy-cells"
>> > +
>> > +additionalProperties: false
>> > +
>> > +examples:
>> > + - |
>> > + #include <dt-bindings/clock/imx8mq-clock.h>
>> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> > +
>> > + display-bridge@32c00000 {
>> > + compatible = "fsl,imx8mq-mhdp8501";
>> > + reg = <0x32c00000 0x100000>;
>> > + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
>> > + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
>> > + interrupt-names = "plug_in", "plug_out";
>> > + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
>> > + phys = <&dp_phy>;
>> > +
>> > + ports {
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>>
>> The ports are not mentioned in the properties. I'm not a DT maintainer, but
>> I think they should, e.g. to mention which port is the input and which is
>> the output.
>>
>> > +
>> > + port@0 {
>> > + reg = <0>;
>> > + endpoint {
>> > + remote-endpoint = <&dcss_out>;
>> > + };
>> > + };
>> > +
>> > + port@1 {
>> > + reg = <1>;
>> > + endpoint {
>> > + data-lanes = <2 1 0 3>;
>>
>> Having a remote-endpoint property would be nice here, to make the example
>> more complete.
>
> The ports and the remote endpoints are documented in the bridge binding...
Ah, my bad, I reviewed too quickly and mixed the phy and bridge bindings in
my mind, sorry.
>
> However, I believe I screwed this example up by adding the entire bridge node,
> instead of just a simple:
>
> mhdp {
> phy {
> compatible = "fsl,imx8mq-hdptx-phy";
> #phy-cells = <0>;
> clocks = <&hdmi_phy_27m>, <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
> clock-names = "ref", "apb";
> };
> };
>
> I'll simplify the example in the next iteration.
Yes, I think it would make sense to do it.
Thanks,
Luca
--
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Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply
* Re: [PATCH 4/4] phy: qualcomm: qmp-combo: Add support for Hawi SoC
From: Dmitry Baryshkov @ 2026-04-28 11:40 UTC (permalink / raw)
To: Ronak Raheja
Cc: vkoul, krzk+dt, conor+dt, robh, neil.armstrong, gregkh,
konrad.dybcio, abel.vesa, wesley.cheng, krzysztof.kozlowski,
linux-arm-msm, linux-phy, devicetree, linux-usb, linux-kernel
In-Reply-To: <20260427214217.2735240-5-ronak.raheja@oss.qualcomm.com>
On Mon, Apr 27, 2026 at 02:42:17PM -0700, Ronak Raheja wrote:
> Add support for the USB3-DP combo PHY found on Hawi platform.
>
> The QMP PHY for Hawi uses QSERDES V10 register layouts. Add the required
> PHY sequences from the hardware programming guide and new V10 register
> header files. Also add a new v10 offset structure to incorporate the new
> COM AON register module.
Was this tested with the DP too or did you test only the USB part?
>
> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
> .../phy/qualcomm/phy-qcom-qmp-com-aon-v10.h | 15 ++
> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 231 +++++++++++++++++-
> .../phy/qualcomm/phy-qcom-qmp-dp-phy-v10.h | 15 ++
> .../phy/qualcomm/phy-qcom-qmp-pcs-aon-v10.h | 13 +
> .../phy/qualcomm/phy-qcom-qmp-pcs-usb-v10.h | 19 ++
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h | 34 +++
> .../qualcomm/phy-qcom-qmp-qserdes-com-v10.h | 89 +++++++
> .../qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h | 89 +++++++
> drivers/phy/qualcomm/phy-qcom-qmp.h | 5 +
> 9 files changed, 506 insertions(+), 4 deletions(-)
> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-com-aon-v10.h
> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v10.h
> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v10.h
> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v10.h
> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h
> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h
> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h
>
> @@ -2198,6 +2368,7 @@ struct qmp_combo_offsets {
> u16 dp_txa;
> u16 dp_txb;
> u16 dp_dp_phy;
> + u16 aon_toggle;
Are there (or will there) be any other regs? Is it just one-register
space?
> };
>
> struct qmp_phy_cfg {
> @@ -2705,6 +2895,27 @@ static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = {
> .regs = qmp_v6_n4_usb3phy_regs_layout,
> };
>
> +static const struct qmp_phy_cfg hawi_usb3dpphy_cfg = {
> + .offsets = &qmp_combo_offsets_v10,
> +
> + .serdes_tbl = hawi_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(hawi_usb3_serdes_tbl),
> + .tx_tbl = hawi_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(hawi_usb3_tx_tbl),
> + .rx_tbl = hawi_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(hawi_usb3_rx_tbl),
> + .pcs_tbl = hawi_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(hawi_usb3_pcs_tbl),
> + .pcs_usb_tbl = hawi_usb3_pcs_usb_tbl,
> + .pcs_usb_tbl_num = ARRAY_SIZE(hawi_usb3_pcs_usb_tbl),
> +
> + .regs = qmp_v10_usb3phy_regs_layout,
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
No DP counterpart and no mention of it in the commit message.
> +};
> +
> static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
> .offsets = &qmp_combo_offsets_v3,
>
--
With best wishes
Dmitry
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^ permalink raw reply
* RE: [PATCH] phy: renesas: phy-rzg3e-usb3: Fix runtime PM underflow during suspend
From: Biju Das @ 2026-04-28 9:38 UTC (permalink / raw)
To: Ovidiu Panait, vkoul@kernel.org, neil.armstrong@linaro.org
Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
In-Reply-To: <TY7P301MB198432F1681EFA444D16F824D3372@TY7P301MB1984.JPNP301.PROD.OUTLOOK.COM>
Hi Ovidiu,
> -----Original Message-----
> From: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> Sent: 28 April 2026 10:21
> Subject: RE: [PATCH] phy: renesas: phy-rzg3e-usb3: Fix runtime PM underflow during suspend
>
> Hi Biju,
>
> >
> > Hi Ovidiu,
> >
> > Thanks for the patch
> >
> > > -----Original Message-----
> > > From: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> > > Sent: 27 April 2026 20:48
> > > Subject: [PATCH] phy: renesas: phy-rzg3e-usb3: Fix runtime PM
> > > underflow
> > during suspend
> > >
> > > On the Renesas RZ/V2H platform, if the xhcd driver is unbound and
> > > the
> > system is suspended afterwards, a
> > > PM underflow error will occur:
> > >
> > > # echo 15850000.usb >
> > > /sys/bus/platform/drivers/xhci-renesas-hcd/unbind
> > > # systemctl suspend
> > > 15870000.usb-phy: PM: dpm_run_callback(): genpd_resume_noirq
> > > returns -
> > 13
> > > 15870000.usb-phy: PM: failed to resume noirq: error -13
> > > 15870000.usb-phy: Runtime PM usage count underflow!
> > >
> > > Since the PHY framework is managing the runtime PM of the PHY via
> > phy_power_on()/phy_power_off(), there
> > > is no need for the PHY driver to manipulate the runtime PM state
> > > during
> > suspend.
> > >
> > > To fix this, remove the runtime PM calls from the suspend/resume
> > > paths
> > and add a get/put pair inside
> > > rzg3e_phy_usb3_init_helper() to make sure the clock is enabled
> > > during
> > init, even when there is no
> > > consumer for the PHY.
> > >
> > > Also, change the suspend ops from NOIRQ_SYSTEM_SLEEP_PM_OPS to
> > SYSTEM_SLEEP_PM_OPS because runtime PM
> > > is disabled during the noirq phase and pm_runtime_resume_and_get()
> > > would
> > not actually enable the device
> > > clock.
> > >
> > > Fixes: ee5f1a3f90a4 ("phy: renesas: Add Renesas RZ/G3E USB3.0 PHY
> > driver")
> > > Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> > > ---
> > > drivers/phy/renesas/phy-rzg3e-usb3.c | 31
> > > ++++++++++++++++------------
> > > 1 file changed, 18 insertions(+), 13 deletions(-)
> > >
> > > diff --git a/drivers/phy/renesas/phy-rzg3e-usb3.c
> > b/drivers/phy/renesas/phy-rzg3e-usb3.c
> > > index 6b3453ea0004..055775e1a0f7 100644
> > > --- a/drivers/phy/renesas/phy-rzg3e-usb3.c
> > > +++ b/drivers/phy/renesas/phy-rzg3e-usb3.c
> > > @@ -64,6 +64,7 @@
> > > #define USB3_TEST_LANECONFIG0_DEFAULT (0xd)
> > >
> > > struct rz_usb3 {
> > > + struct device *dev;
> >
> > Do you need dev as struct phy has dev member [1]?
> >
> > [1]
> > https://elixir.bootlin.com/linux/v6.0-
> > rc4/source/include/linux/phy/phy.h#L153
> >
> > > void __iomem *base;
> > > struct reset_control *rstc;
> > > bool skip_reinit;
> > > @@ -130,11 +131,21 @@ static int rzg3e_phy_usb3test_phy_init(void
> > __iomem *base)
> > > return 0;
> > > }
> > >
> > > -static int rzg3e_phy_usb3_init_helper(void __iomem *base)
> >
> > you can add one more function parameter dev here.
> >
> > static int rzg3e_phy_usb3_init_helper(struct device *dev, void __iomem
> > *base)
> >
> > > +static int rzg3e_phy_usb3_init_helper(struct rz_usb3 *r)
> > > {
> > > - rzg3e_phy_usb2test_phy_init(base);
> > > + int ret;
> > > +
> > > + ret = pm_runtime_resume_and_get(r->dev);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + rzg3e_phy_usb2test_phy_init(r->base);
> > >
> > > - return rzg3e_phy_usb3test_phy_init(base);
> > > + ret = rzg3e_phy_usb3test_phy_init(r->base);
> > > +
> > > + pm_runtime_put_sync(r->dev);
> > > +
> > > + return ret;
> > > }
> > >
> > > static int rzg3e_phy_usb3_init(struct phy *p) @@ -143,7 +154,7 @@
> > static int
> > > rzg3e_phy_usb3_init(struct phy *p)
> > > int ret = 0;
> > >
> > > if (!r->skip_reinit)
> > > - ret = rzg3e_phy_usb3_init_helper(r->base);
> > > + ret = rzg3e_phy_usb3_init_helper(r);
> >
> > ret = rzg3e_phy_usb3_init_helper(&p->dev, r->base);
> >
> > >
> > > return ret;
> > > }
> > > @@ -187,6 +198,7 @@ static int rzg3e_phy_usb3_probe(struct
> > platform_device *pdev)
> > >
> > > platform_set_drvdata(pdev, r);
> >
> > > phy_set_drvdata(phy, r);
> > > + r->dev = dev;
> >
> > Drop this.
> >
> > >
> > > provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> > > if (IS_ERR(provider))
> > > @@ -199,7 +211,6 @@ static int rzg3e_phy_usb3_suspend(struct device
> > *dev) {
> > > struct rz_usb3 *r = dev_get_drvdata(dev);
> > >
> > > - pm_runtime_put(dev);
> > > reset_control_assert(r->rstc);
> > > r->skip_reinit = false;
> > >
> > > @@ -215,27 +226,21 @@ static int rzg3e_phy_usb3_resume(struct device
> > *dev)
> > > if (ret)
> > > return ret;
> > >
> > > - ret = pm_runtime_resume_and_get(dev);
> > > + ret = rzg3e_phy_usb3_init_helper(r);
> >
> > ret = rzg3e_phy_usb3_init_helper(dev, r->base);
>
> "dev" is the platform device, which is different from phy->dev. Phy->dev is a child of the platform
> device.
You are correct. I missed that.
>
> We could be referencing the platform device from phy->dev with &phy->dev.parent, but I don't think that
> will make the code cleaner.
Thought of avoiding another global variable that saves 4 bytes.
Changing "&phy->dev"->""&phy->dev.parent" is not making the code cleaner
then leave as it is.
Cheers,
Biju
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^ permalink raw reply
* RE: [PATCH] phy: renesas: phy-rzg3e-usb3: Fix runtime PM underflow during suspend
From: Ovidiu Panait @ 2026-04-28 9:21 UTC (permalink / raw)
To: Biju Das, vkoul@kernel.org, neil.armstrong@linaro.org
Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
In-Reply-To: <TY3PR01MB11346819FE6253E90C7B4F88486372@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Hi Biju,
>
> Hi Ovidiu,
>
> Thanks for the patch
>
> > -----Original Message-----
> > From: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> > Sent: 27 April 2026 20:48
> > Subject: [PATCH] phy: renesas: phy-rzg3e-usb3: Fix runtime PM underflow
> during suspend
> >
> > On the Renesas RZ/V2H platform, if the xhcd driver is unbound and the
> system is suspended afterwards, a
> > PM underflow error will occur:
> >
> > # echo 15850000.usb > /sys/bus/platform/drivers/xhci-renesas-hcd/unbind
> > # systemctl suspend
> > 15870000.usb-phy: PM: dpm_run_callback(): genpd_resume_noirq returns -
> 13
> > 15870000.usb-phy: PM: failed to resume noirq: error -13
> > 15870000.usb-phy: Runtime PM usage count underflow!
> >
> > Since the PHY framework is managing the runtime PM of the PHY via
> phy_power_on()/phy_power_off(), there
> > is no need for the PHY driver to manipulate the runtime PM state during
> suspend.
> >
> > To fix this, remove the runtime PM calls from the suspend/resume paths
> and add a get/put pair inside
> > rzg3e_phy_usb3_init_helper() to make sure the clock is enabled during
> init, even when there is no
> > consumer for the PHY.
> >
> > Also, change the suspend ops from NOIRQ_SYSTEM_SLEEP_PM_OPS to
> SYSTEM_SLEEP_PM_OPS because runtime PM
> > is disabled during the noirq phase and pm_runtime_resume_and_get() would
> not actually enable the device
> > clock.
> >
> > Fixes: ee5f1a3f90a4 ("phy: renesas: Add Renesas RZ/G3E USB3.0 PHY
> driver")
> > Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> > ---
> > drivers/phy/renesas/phy-rzg3e-usb3.c | 31 ++++++++++++++++------------
> > 1 file changed, 18 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/phy/renesas/phy-rzg3e-usb3.c
> b/drivers/phy/renesas/phy-rzg3e-usb3.c
> > index 6b3453ea0004..055775e1a0f7 100644
> > --- a/drivers/phy/renesas/phy-rzg3e-usb3.c
> > +++ b/drivers/phy/renesas/phy-rzg3e-usb3.c
> > @@ -64,6 +64,7 @@
> > #define USB3_TEST_LANECONFIG0_DEFAULT (0xd)
> >
> > struct rz_usb3 {
> > + struct device *dev;
>
> Do you need dev as struct phy has dev member [1]?
>
> [1]
> https://elixir.bootlin.com/linux/v6.0-
> rc4/source/include/linux/phy/phy.h#L153
>
> > void __iomem *base;
> > struct reset_control *rstc;
> > bool skip_reinit;
> > @@ -130,11 +131,21 @@ static int rzg3e_phy_usb3test_phy_init(void
> __iomem *base)
> > return 0;
> > }
> >
> > -static int rzg3e_phy_usb3_init_helper(void __iomem *base)
>
> you can add one more function parameter dev here.
>
> static int rzg3e_phy_usb3_init_helper(struct device *dev, void __iomem
> *base)
>
> > +static int rzg3e_phy_usb3_init_helper(struct rz_usb3 *r)
> > {
> > - rzg3e_phy_usb2test_phy_init(base);
> > + int ret;
> > +
> > + ret = pm_runtime_resume_and_get(r->dev);
> > + if (ret)
> > + return ret;
> > +
> > + rzg3e_phy_usb2test_phy_init(r->base);
> >
> > - return rzg3e_phy_usb3test_phy_init(base);
> > + ret = rzg3e_phy_usb3test_phy_init(r->base);
> > +
> > + pm_runtime_put_sync(r->dev);
> > +
> > + return ret;
> > }
> >
> > static int rzg3e_phy_usb3_init(struct phy *p) @@ -143,7 +154,7 @@
> static int
> > rzg3e_phy_usb3_init(struct phy *p)
> > int ret = 0;
> >
> > if (!r->skip_reinit)
> > - ret = rzg3e_phy_usb3_init_helper(r->base);
> > + ret = rzg3e_phy_usb3_init_helper(r);
>
> ret = rzg3e_phy_usb3_init_helper(&p->dev, r->base);
>
> >
> > return ret;
> > }
> > @@ -187,6 +198,7 @@ static int rzg3e_phy_usb3_probe(struct
> platform_device *pdev)
> >
> > platform_set_drvdata(pdev, r);
>
> > phy_set_drvdata(phy, r);
> > + r->dev = dev;
>
> Drop this.
>
> >
> > provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> > if (IS_ERR(provider))
> > @@ -199,7 +211,6 @@ static int rzg3e_phy_usb3_suspend(struct device
> *dev) {
> > struct rz_usb3 *r = dev_get_drvdata(dev);
> >
> > - pm_runtime_put(dev);
> > reset_control_assert(r->rstc);
> > r->skip_reinit = false;
> >
> > @@ -215,27 +226,21 @@ static int rzg3e_phy_usb3_resume(struct device
> *dev)
> > if (ret)
> > return ret;
> >
> > - ret = pm_runtime_resume_and_get(dev);
> > + ret = rzg3e_phy_usb3_init_helper(r);
>
> ret = rzg3e_phy_usb3_init_helper(dev, r->base);
"dev" is the platform device, which is different from phy->dev. Phy->dev
is a child of the platform device.
We could be referencing the platform device from phy->dev with &phy->dev.parent,
but I don't think that will make the code cleaner.
Considering this, I think the current implementation is fine.
Ovidiu
>
> With the above addressed,
>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
>
> Cheers,
> Biju
>
> > if (ret)
> > goto reset_assert;
> >
> > - ret = rzg3e_phy_usb3_init_helper(r->base);
> > - if (ret)
> > - goto pm_put;
> > -
> > r->skip_reinit = true;
> >
> > return 0;
> >
> > -pm_put:
> > - pm_runtime_put(dev);
> > reset_assert:
> > reset_control_assert(r->rstc);
> > return ret;
> > }
> >
> > static const struct dev_pm_ops rzg3e_phy_usb3_pm = {
> > - NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg3e_phy_usb3_suspend,
> rzg3e_phy_usb3_resume)
> > + SYSTEM_SLEEP_PM_OPS(rzg3e_phy_usb3_suspend, rzg3e_phy_usb3_resume)
> > };
> >
> > static const struct of_device_id rzg3e_phy_usb3_match_table[] = {
> > --
> > 2.34.1
--
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^ permalink raw reply
* Re: [PATCH 4/4] phy: qualcomm: qmp-combo: Add support for Hawi SoC
From: Abel Vesa @ 2026-04-28 8:32 UTC (permalink / raw)
To: Ronak Raheja
Cc: vkoul, krzk+dt, conor+dt, robh, neil.armstrong, gregkh,
dmitry.baryshkov, konrad.dybcio, wesley.cheng,
krzysztof.kozlowski, linux-arm-msm, linux-phy, devicetree,
linux-usb, linux-kernel
In-Reply-To: <20260427214217.2735240-5-ronak.raheja@oss.qualcomm.com>
On 26-04-27 14:42:17, Ronak Raheja wrote:
> Add support for the USB3-DP combo PHY found on Hawi platform.
>
> The QMP PHY for Hawi uses QSERDES V10 register layouts. Add the required
> PHY sequences from the hardware programming guide and new V10 register
> header files. Also add a new v10 offset structure to incorporate the new
> COM AON register module.
>
> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
--
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^ permalink raw reply
* Re: [PATCH v2] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document Nord QMP UFS PHY
From: Krzysztof Kozlowski @ 2026-04-28 6:23 UTC (permalink / raw)
To: Shawn Guo
Cc: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Konrad Dybcio, Dmitry Baryshkov, Bartosz Golaszewski,
Deepti Jaggi, linux-phy, devicetree, linux-arm-msm, linux-kernel
In-Reply-To: <20260427012732.231611-1-shengchao.guo@oss.qualcomm.com>
On Mon, Apr 27, 2026 at 09:27:32AM +0800, Shawn Guo wrote:
> Document QMP UFS PHY on Qualcomm Nord SoC which is compatible with
> 'qcom,sm8650-qmp-ufs-phy'.
Why are you naming compatibles not devices in the commit msgs? We never
used, never asked for it, there are basically no such commits. git log
can help here, for example last commit from Abel looks reasonable
(although repeating "so use fallback" is redundant - it's obvious).
Best regards,
Krzysztof
--
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^ permalink raw reply
* RE: [PATCH] phy: renesas: phy-rzg3e-usb3: Fix runtime PM underflow during suspend
From: Biju Das @ 2026-04-28 6:17 UTC (permalink / raw)
To: Ovidiu Panait, vkoul@kernel.org, neil.armstrong@linaro.org
Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, Ovidiu Panait
In-Reply-To: <20260427194741.161533-1-ovidiu.panait.rb@renesas.com>
Hi Ovidiu,
Thanks for the patch
> -----Original Message-----
> From: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> Sent: 27 April 2026 20:48
> Subject: [PATCH] phy: renesas: phy-rzg3e-usb3: Fix runtime PM underflow during suspend
>
> On the Renesas RZ/V2H platform, if the xhcd driver is unbound and the system is suspended afterwards, a
> PM underflow error will occur:
>
> # echo 15850000.usb > /sys/bus/platform/drivers/xhci-renesas-hcd/unbind
> # systemctl suspend
> 15870000.usb-phy: PM: dpm_run_callback(): genpd_resume_noirq returns -13
> 15870000.usb-phy: PM: failed to resume noirq: error -13
> 15870000.usb-phy: Runtime PM usage count underflow!
>
> Since the PHY framework is managing the runtime PM of the PHY via phy_power_on()/phy_power_off(), there
> is no need for the PHY driver to manipulate the runtime PM state during suspend.
>
> To fix this, remove the runtime PM calls from the suspend/resume paths and add a get/put pair inside
> rzg3e_phy_usb3_init_helper() to make sure the clock is enabled during init, even when there is no
> consumer for the PHY.
>
> Also, change the suspend ops from NOIRQ_SYSTEM_SLEEP_PM_OPS to SYSTEM_SLEEP_PM_OPS because runtime PM
> is disabled during the noirq phase and pm_runtime_resume_and_get() would not actually enable the device
> clock.
>
> Fixes: ee5f1a3f90a4 ("phy: renesas: Add Renesas RZ/G3E USB3.0 PHY driver")
> Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> ---
> drivers/phy/renesas/phy-rzg3e-usb3.c | 31 ++++++++++++++++------------
> 1 file changed, 18 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/phy/renesas/phy-rzg3e-usb3.c b/drivers/phy/renesas/phy-rzg3e-usb3.c
> index 6b3453ea0004..055775e1a0f7 100644
> --- a/drivers/phy/renesas/phy-rzg3e-usb3.c
> +++ b/drivers/phy/renesas/phy-rzg3e-usb3.c
> @@ -64,6 +64,7 @@
> #define USB3_TEST_LANECONFIG0_DEFAULT (0xd)
>
> struct rz_usb3 {
> + struct device *dev;
Do you need dev as struct phy has dev member [1]?
[1]
https://elixir.bootlin.com/linux/v6.0-rc4/source/include/linux/phy/phy.h#L153
> void __iomem *base;
> struct reset_control *rstc;
> bool skip_reinit;
> @@ -130,11 +131,21 @@ static int rzg3e_phy_usb3test_phy_init(void __iomem *base)
> return 0;
> }
>
> -static int rzg3e_phy_usb3_init_helper(void __iomem *base)
you can add one more function parameter dev here.
static int rzg3e_phy_usb3_init_helper(struct device *dev, void __iomem *base)
> +static int rzg3e_phy_usb3_init_helper(struct rz_usb3 *r)
> {
> - rzg3e_phy_usb2test_phy_init(base);
> + int ret;
> +
> + ret = pm_runtime_resume_and_get(r->dev);
> + if (ret)
> + return ret;
> +
> + rzg3e_phy_usb2test_phy_init(r->base);
>
> - return rzg3e_phy_usb3test_phy_init(base);
> + ret = rzg3e_phy_usb3test_phy_init(r->base);
> +
> + pm_runtime_put_sync(r->dev);
> +
> + return ret;
> }
>
> static int rzg3e_phy_usb3_init(struct phy *p) @@ -143,7 +154,7 @@ static int
> rzg3e_phy_usb3_init(struct phy *p)
> int ret = 0;
>
> if (!r->skip_reinit)
> - ret = rzg3e_phy_usb3_init_helper(r->base);
> + ret = rzg3e_phy_usb3_init_helper(r);
ret = rzg3e_phy_usb3_init_helper(&p->dev, r->base);
>
> return ret;
> }
> @@ -187,6 +198,7 @@ static int rzg3e_phy_usb3_probe(struct platform_device *pdev)
>
> platform_set_drvdata(pdev, r);
> phy_set_drvdata(phy, r);
> + r->dev = dev;
Drop this.
>
> provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> if (IS_ERR(provider))
> @@ -199,7 +211,6 @@ static int rzg3e_phy_usb3_suspend(struct device *dev) {
> struct rz_usb3 *r = dev_get_drvdata(dev);
>
> - pm_runtime_put(dev);
> reset_control_assert(r->rstc);
> r->skip_reinit = false;
>
> @@ -215,27 +226,21 @@ static int rzg3e_phy_usb3_resume(struct device *dev)
> if (ret)
> return ret;
>
> - ret = pm_runtime_resume_and_get(dev);
> + ret = rzg3e_phy_usb3_init_helper(r);
ret = rzg3e_phy_usb3_init_helper(dev, r->base);
With the above addressed,
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Cheers,
Biju
> if (ret)
> goto reset_assert;
>
> - ret = rzg3e_phy_usb3_init_helper(r->base);
> - if (ret)
> - goto pm_put;
> -
> r->skip_reinit = true;
>
> return 0;
>
> -pm_put:
> - pm_runtime_put(dev);
> reset_assert:
> reset_control_assert(r->rstc);
> return ret;
> }
>
> static const struct dev_pm_ops rzg3e_phy_usb3_pm = {
> - NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg3e_phy_usb3_suspend, rzg3e_phy_usb3_resume)
> + SYSTEM_SLEEP_PM_OPS(rzg3e_phy_usb3_suspend, rzg3e_phy_usb3_resume)
> };
>
> static const struct of_device_id rzg3e_phy_usb3_match_table[] = {
> --
> 2.34.1
--
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^ permalink raw reply
* [PATCH 4/4] phy: qualcomm: qmp-combo: Add support for Hawi SoC
From: Ronak Raheja @ 2026-04-27 21:42 UTC (permalink / raw)
To: vkoul, krzk+dt, conor+dt, robh, neil.armstrong, gregkh
Cc: dmitry.baryshkov, konrad.dybcio, abel.vesa, wesley.cheng,
krzysztof.kozlowski, ronak.raheja, linux-arm-msm, linux-phy,
devicetree, linux-usb, linux-kernel
In-Reply-To: <20260427214217.2735240-1-ronak.raheja@oss.qualcomm.com>
Add support for the USB3-DP combo PHY found on Hawi platform.
The QMP PHY for Hawi uses QSERDES V10 register layouts. Add the required
PHY sequences from the hardware programming guide and new V10 register
header files. Also add a new v10 offset structure to incorporate the new
COM AON register module.
Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
.../phy/qualcomm/phy-qcom-qmp-com-aon-v10.h | 15 ++
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 231 +++++++++++++++++-
.../phy/qualcomm/phy-qcom-qmp-dp-phy-v10.h | 15 ++
.../phy/qualcomm/phy-qcom-qmp-pcs-aon-v10.h | 13 +
.../phy/qualcomm/phy-qcom-qmp-pcs-usb-v10.h | 19 ++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h | 34 +++
.../qualcomm/phy-qcom-qmp-qserdes-com-v10.h | 89 +++++++
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h | 89 +++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 5 +
9 files changed, 506 insertions(+), 4 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-com-aon-v10.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v10.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v10.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v10.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-com-aon-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-com-aon-v10.h
new file mode 100644
index 000000000000..6542b586be89
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-com-aon-v10.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_COM_AON_V10_H_
+#define QCOM_PHY_QMP_COM_AON_V10_H_
+
+/* Only for QMP V10 PHY - COM AON registers */
+
+#define QPHY_V10_COM_AON_USB3_AON_TOGGLE_ENABLE 0x00
+#define QPHY_V10_COM_AON_DP_AON_TOGGLE_ENABLE 0x04
+#define QPHY_V10_COM_AON_DUMMY_STATUS 0x08
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index 93f1aa10d400..53b709ea93d5 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -32,6 +32,7 @@
#include "phy-qcom-qmp.h"
#include "phy-qcom-qmp-pcs-aon-v6.h"
#include "phy-qcom-qmp-pcs-aon-v8.h"
+#include "phy-qcom-qmp-pcs-aon-v10.h"
#include "phy-qcom-qmp-pcs-misc-v3.h"
#include "phy-qcom-qmp-pcs-misc-v4.h"
#include "phy-qcom-qmp-pcs-misc-v5.h"
@@ -40,6 +41,7 @@
#include "phy-qcom-qmp-pcs-usb-v5.h"
#include "phy-qcom-qmp-pcs-usb-v6.h"
#include "phy-qcom-qmp-pcs-usb-v8.h"
+#include "phy-qcom-qmp-pcs-usb-v10.h"
#include "phy-qcom-qmp-dp-com-v3.h"
@@ -49,9 +51,12 @@
#include "phy-qcom-qmp-dp-phy-v5.h"
#include "phy-qcom-qmp-dp-phy-v6.h"
#include "phy-qcom-qmp-dp-phy-v8.h"
+#include "phy-qcom-qmp-dp-phy-v10.h"
#include "phy-qcom-qmp-usb43-pcs-v8.h"
+#include "phy-qcom-qmp-com-aon-v10.h"
+
/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
/* DP PHY soft reset */
#define SW_DPPHY_RESET BIT(0)
@@ -268,6 +273,36 @@ static const unsigned int qmp_v8_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V8_TX_TRANSCEIVER_BIAS_EN,
};
+static const unsigned int qmp_v10_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
+ [QPHY_SW_RESET] = QPHY_V10_PCS_SW_RESET,
+ [QPHY_START_CTRL] = QPHY_V10_PCS_START_CONTROL,
+ [QPHY_PCS_STATUS] = QPHY_V10_PCS_PCS_STATUS1,
+ [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V10_PCS_POWER_DOWN_CONTROL,
+
+ /* In PCS_USB */
+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V10_PCS_USB3_AUTONOMOUS_MODE_CTRL,
+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V10_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
+
+ [QPHY_PCS_CLAMP_ENABLE] = QPHY_V10_PCS_AON_CLAMP_ENABLE,
+
+ [QPHY_AON_TOGGLE_ENABLE] = QPHY_V10_COM_AON_USB3_AON_TOGGLE_ENABLE,
+ [QPHY_DP_AON_TOGGLE_ENABLE] = QPHY_V10_COM_AON_DP_AON_TOGGLE_ENABLE,
+
+ [QPHY_COM_RESETSM_CNTRL] = QSERDES_V10_COM_RESETSM_CNTRL,
+ [QPHY_COM_C_READY_STATUS] = QSERDES_V10_COM_C_READY_STATUS,
+ [QPHY_COM_CMN_STATUS] = QSERDES_V10_COM_CMN_STATUS,
+ [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V10_COM_BIAS_EN_CLKBUFLR_EN,
+
+ [QPHY_DP_PHY_STATUS] = QSERDES_V10_DP_PHY_STATUS,
+ [QPHY_DP_PHY_VCO_DIV] = QSERDES_V10_DP_PHY_VCO_DIV,
+
+ [QPHY_TX_TX_POL_INV] = QSERDES_V10_TX_TX_POL_INV,
+ [QPHY_TX_TX_DRV_LVL] = QSERDES_V10_TX_TX_DRV_LVL,
+ [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V10_TX_TX_EMP_POST1_LVL,
+ [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V10_TX_HIGHZ_DRVR_EN,
+ [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V10_TX_TRANSCEIVER_BIAS_EN,
+};
+
static const unsigned int qmp_v8_n3_usb43dpphy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_SW_RESET] = QPHY_V8_USB43_PCS_SW_RESET,
[QPHY_START_CTRL] = QPHY_V8_USB43_PCS_START_CONTROL,
@@ -2058,6 +2093,141 @@ static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
};
+static const struct qmp_phy_init_tbl hawi_usb3_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE2_MODE1, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_CP_CTRL_MODE1, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_RCTRL_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_CCTRL_MODE1, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_CORECLK_DIV_MODE1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP1_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP2_MODE1, 0x41),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DEC_START_MODE1, 0x41),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DEC_START_MSB_MODE1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START1_MODE1, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START2_MODE1, 0x75),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START3_MODE1, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_HSCLK_SEL_1, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_VCO_TUNE1_MODE1, 0x25),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_VCO_TUNE2_MODE1, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE2_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_CP_CTRL_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_CCTRL_MODE0, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP1_MODE0, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP2_MODE0, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DEC_START_MODE0, 0x41),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DEC_START_MSB_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START1_MODE0, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START2_MODE0, 0x75),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START3_MODE0, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_VCO_TUNE1_MODE0, 0x25),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_VCO_TUNE2_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_BG_TIMER, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_PER1, 0x62),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_PER2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SYSCLK_BUF_ENABLE, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_SYSCLK_EN_SEL, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP_CFG, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_VCO_TUNE_MAP, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_CORE_CLK_EN, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_CMN_CONFIG_1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_AUTO_GAIN_ADJ_CTRL_3, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_V10_COM_ADDITIONAL_MISC, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl hawi_usb3_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_RES_CODE_LANE_TX, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_RES_CODE_LANE_RX, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_1, 0xe5),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_3, 0x11),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_4, 0x31),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_5, 0x5d),
+ QMP_PHY_INIT_CFG(QSERDES_V10_TX_RCV_DETECT_LVL_2, 0x12),
+ QMP_PHY_INIT_CFG_LANE(QSERDES_V10_TX_PI_QEC_CTRL, 0x21, 1),
+ QMP_PHY_INIT_CFG_LANE(QSERDES_V10_TX_PI_QEC_CTRL, 0x05, 2),
+};
+
+static const struct qmp_phy_init_tbl hawi_usb3_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_FO_GAIN, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SO_GAIN, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_PI_CONTROLS, 0x99),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SB2_THRESH1, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SB2_THRESH2, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SB2_GAIN1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SB2_GAIN2, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_AUX_DATA_TCOARSE_TFINE, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_VGA_CAL_CNTRL1, 0x54),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_VGA_CAL_CNTRL2, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_GM_CAL, 0x13),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_IDAC_TSETTLE_LOW, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_ENABLES, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_CNTRL, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_LOW, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH, 0xbf),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH2, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH3, 0xdf),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH4, 0xed),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_LOW, 0x19),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH2, 0x91),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH3, 0xb7),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH4, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_DFE_EN_TIMER, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_DCC_CTRL1, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_VTH_CODE, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_CAL_CTRL1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_CAL_TRIM, 0x08),
+};
+
+static const struct qmp_phy_init_tbl hawi_usb3_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_LOCK_DETECT_CONFIG1, 0xc4),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_LOCK_DETECT_CONFIG2, 0x89),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_LOCK_DETECT_CONFIG3, 0x20),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_LOCK_DETECT_CONFIG6, 0x13),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_REFGEN_REQ_CONFIG1, 0x21),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_RX_SIGDET_LVL, 0x55),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_RX_CONFIG, 0x0a),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_ALIGN_DETECT_CONFIG1, 0x88),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_ALIGN_DETECT_CONFIG2, 0x13),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_PCS_TX_RX_CONFIG, 0x04),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_PCS_TX_RX_CONFIG2, 0x01),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_EQ_CONFIG1, 0x4b),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_EQ_CONFIG5, 0x10),
+};
+
+static const struct qmp_phy_init_tbl hawi_usb3_pcs_usb_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_V10_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
+};
+
/* list of regulators */
static struct regulator_bulk_data qmp_phy_vreg_l[] = {
{ .supply = "vdda-phy", .init_load_uA = 21800, },
@@ -2198,6 +2368,7 @@ struct qmp_combo_offsets {
u16 dp_txa;
u16 dp_txb;
u16 dp_dp_phy;
+ u16 aon_toggle;
};
struct qmp_phy_cfg {
@@ -2270,6 +2441,7 @@ struct qmp_combo {
const struct qmp_phy_cfg *cfg;
void __iomem *com;
+ void __iomem *aon_toggle;
void __iomem *serdes;
void __iomem *tx;
@@ -2416,6 +2588,24 @@ static const struct qmp_combo_offsets qmp_combo_offsets_v8 = {
.dp_dp_phy = 0x3c00,
};
+static const struct qmp_combo_offsets qmp_combo_offsets_v10 = {
+ .com = 0x0000,
+ .aon_toggle = 0x0400,
+ .txa = 0x1400,
+ .rxa = 0x1600,
+ .txb = 0x1800,
+ .rxb = 0x1a00,
+ .usb3_serdes = 0x1000,
+ .usb3_pcs_misc = 0x1c00,
+ .usb3_pcs = 0x1e00,
+ .usb3_pcs_aon = 0x2000,
+ .usb3_pcs_usb = 0x2100,
+ .dp_serdes = 0x3000,
+ .dp_txa = 0x3400,
+ .dp_txb = 0x3800,
+ .dp_dp_phy = 0x3c00,
+};
+
static const struct qmp_combo_offsets qmp_combo_usb43dp_offsets_v8 = {
.com = 0x0000,
.usb3_pcs_aon = 0x0100,
@@ -2705,6 +2895,27 @@ static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = {
.regs = qmp_v6_n4_usb3phy_regs_layout,
};
+static const struct qmp_phy_cfg hawi_usb3dpphy_cfg = {
+ .offsets = &qmp_combo_offsets_v10,
+
+ .serdes_tbl = hawi_usb3_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(hawi_usb3_serdes_tbl),
+ .tx_tbl = hawi_usb3_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(hawi_usb3_tx_tbl),
+ .rx_tbl = hawi_usb3_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(hawi_usb3_rx_tbl),
+ .pcs_tbl = hawi_usb3_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(hawi_usb3_pcs_tbl),
+ .pcs_usb_tbl = hawi_usb3_pcs_usb_tbl,
+ .pcs_usb_tbl_num = ARRAY_SIZE(hawi_usb3_pcs_usb_tbl),
+
+ .regs = qmp_v10_usb3phy_regs_layout,
+ .reset_list = msm8996_usb3phy_reset_l,
+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+};
+
static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
.offsets = &qmp_combo_offsets_v3,
@@ -3662,13 +3873,18 @@ static int qmp_combo_com_init(struct qmp_combo *qmp, bool force)
{
const struct qmp_phy_cfg *cfg = qmp->cfg;
void __iomem *com = qmp->com;
- void __iomem *pcs_aon = qmp->pcs_aon;
+ void __iomem *aon_toggle;
int ret;
u32 val;
if (!force && qmp->init_count++)
return 0;
+ if (qmp->aon_toggle)
+ aon_toggle = qmp->aon_toggle;
+ else
+ aon_toggle = qmp->pcs_aon;
+
ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
if (ret) {
dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
@@ -3699,9 +3915,9 @@ static int qmp_combo_com_init(struct qmp_combo *qmp, bool force)
SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
/* override hardware control for reset of qmp phy */
- if (pcs_aon && cfg->regs[QPHY_AON_TOGGLE_ENABLE]) {
- qphy_clrbits(pcs_aon, cfg->regs[QPHY_AON_TOGGLE_ENABLE], 0x1);
- qphy_clrbits(pcs_aon, cfg->regs[QPHY_DP_AON_TOGGLE_ENABLE], 0x1);
+ if (aon_toggle && cfg->regs[QPHY_AON_TOGGLE_ENABLE]) {
+ qphy_clrbits(aon_toggle, cfg->regs[QPHY_AON_TOGGLE_ENABLE], 0x1);
+ qphy_clrbits(aon_toggle, cfg->regs[QPHY_DP_AON_TOGGLE_ENABLE], 0x1);
}
/* Use software based port select and switch on typec orientation */
@@ -4733,6 +4949,9 @@ static int qmp_combo_parse_dt(struct qmp_combo *qmp)
}
qmp->dp_dp_phy = base + offs->dp_dp_phy;
+ if (offs->aon_toggle)
+ qmp->aon_toggle = base + offs->aon_toggle;
+
ret = qmp_combo_clk_init(qmp);
if (ret)
return ret;
@@ -4986,6 +5205,10 @@ static const struct of_device_id qmp_combo_of_match_table[] = {
.compatible = "qcom,glymur-qmp-usb3-dp-phy",
.data = &glymur_usb3dpphy_cfg,
},
+ {
+ .compatible = "qcom,hawi-qmp-usb3-dp-phy",
+ .data = &hawi_usb3dpphy_cfg,
+ },
{
.compatible = "qcom,sar2130p-qmp-usb3-dp-phy",
.data = &sar2130p_usb3dpphy_cfg,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v10.h
new file mode 100644
index 000000000000..6f3ea7d13556
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v10.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_DP_PHY_V10_H_
+#define QCOM_PHY_QMP_DP_PHY_V10_H_
+
+/* Only for QMP V10 PHY - DP PHY registers */
+
+#define QSERDES_V10_DP_PHY_VCO_DIV 0x070
+#define QSERDES_V10_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0
+#define QSERDES_V10_DP_PHY_STATUS 0x0e4
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v10.h
new file mode 100644
index 000000000000..b858381bc238
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v10.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_AON_V10_H_
+#define QCOM_PHY_QMP_PCS_AON_V10_H_
+
+/* Only for QMP V10 PHY - PCS AON registers */
+
+#define QPHY_V10_PCS_AON_CLAMP_ENABLE 0x00
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v10.h
new file mode 100644
index 000000000000..0cc25e6acf58
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v10.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_USB_V10_H_
+#define QCOM_PHY_QMP_PCS_USB_V10_H_
+
+/* Only for QMP V10 PHY - USB PCS registers */
+
+#define QPHY_V10_PCS_USB3_POWER_STATE_CONFIG1 0x00
+#define QPHY_V10_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x08
+#define QPHY_V10_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x14
+#define QPHY_V10_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x18
+#define QPHY_V10_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x3c
+#define QPHY_V10_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
+#define QPHY_V10_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x44
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h
new file mode 100644
index 000000000000..ac0fc434984b
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V10_H_
+#define QCOM_PHY_QMP_PCS_V10_H_
+
+/* Only for QMP V10 PHY - PCS registers */
+
+#define QPHY_V10_PCS_SW_RESET 0x000
+#define QPHY_V10_PCS_PCS_STATUS1 0x014
+#define QPHY_V10_PCS_POWER_DOWN_CONTROL 0x040
+#define QPHY_V10_PCS_START_CONTROL 0x044
+#define QPHY_V10_PCS_POWER_STATE_CONFIG1 0x090
+#define QPHY_V10_PCS_LOCK_DETECT_CONFIG1 0x0c4
+#define QPHY_V10_PCS_LOCK_DETECT_CONFIG2 0x0c8
+#define QPHY_V10_PCS_LOCK_DETECT_CONFIG3 0x0cc
+#define QPHY_V10_PCS_LOCK_DETECT_CONFIG6 0x0d8
+#define QPHY_V10_PCS_REFGEN_REQ_CONFIG1 0x0dc
+#define QPHY_V10_PCS_RX_SIGDET_LVL 0x188
+#define QPHY_V10_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
+#define QPHY_V10_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
+#define QPHY_V10_PCS_RATE_SLEW_CNTRL1 0x198
+#define QPHY_V10_PCS_RX_CONFIG 0x1b0
+#define QPHY_V10_PCS_ALIGN_DETECT_CONFIG1 0x1c0
+#define QPHY_V10_PCS_ALIGN_DETECT_CONFIG2 0x1c4
+#define QPHY_V10_PCS_PCS_TX_RX_CONFIG 0x1d0
+#define QPHY_V10_PCS_PCS_TX_RX_CONFIG2 0x1d4
+#define QPHY_V10_PCS_EQ_CONFIG1 0x1e0
+#define QPHY_V10_PCS_EQ_CONFIG2 0x1e4
+#define QPHY_V10_PCS_EQ_CONFIG5 0x1f0
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h
new file mode 100644
index 000000000000..92fbde7c9c7c
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_COM_V10_H_
+#define QCOM_PHY_QMP_QSERDES_COM_V10_H_
+
+/* Only for QMP V10 PHY - QSERDES COM registers */
+
+#define QSERDES_V10_COM_SSC_STEP_SIZE1_MODE1 0x00
+#define QSERDES_V10_COM_SSC_STEP_SIZE2_MODE1 0x04
+#define QSERDES_V10_COM_CP_CTRL_MODE1 0x10
+#define QSERDES_V10_COM_PLL_RCTRL_MODE1 0x14
+#define QSERDES_V10_COM_PLL_CCTRL_MODE1 0x18
+#define QSERDES_V10_COM_CORECLK_DIV_MODE1 0x1c
+#define QSERDES_V10_COM_LOCK_CMP1_MODE1 0x20
+#define QSERDES_V10_COM_LOCK_CMP2_MODE1 0x24
+#define QSERDES_V10_COM_DEC_START_MODE1 0x28
+#define QSERDES_V10_COM_DEC_START_MSB_MODE1 0x2c
+#define QSERDES_V10_COM_DIV_FRAC_START1_MODE1 0x30
+#define QSERDES_V10_COM_DIV_FRAC_START2_MODE1 0x34
+#define QSERDES_V10_COM_DIV_FRAC_START3_MODE1 0x38
+#define QSERDES_V10_COM_HSCLK_SEL_1 0x3c
+#define QSERDES_V10_COM_INTEGLOOP_GAIN0_MODE1 0x40
+#define QSERDES_V10_COM_INTEGLOOP_GAIN1_MODE1 0x44
+#define QSERDES_V10_COM_VCO_TUNE1_MODE1 0x48
+#define QSERDES_V10_COM_VCO_TUNE2_MODE1 0x4c
+#define QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50
+#define QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x54
+#define QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x58
+#define QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x5c
+#define QSERDES_V10_COM_SSC_STEP_SIZE1_MODE0 0x60
+#define QSERDES_V10_COM_SSC_STEP_SIZE2_MODE0 0x64
+#define QSERDES_V10_COM_CP_CTRL_MODE0 0x70
+#define QSERDES_V10_COM_PLL_RCTRL_MODE0 0x74
+#define QSERDES_V10_COM_PLL_CCTRL_MODE0 0x78
+#define QSERDES_V10_COM_PLL_CORE_CLK_DIV_MODE0 0x7c
+#define QSERDES_V10_COM_LOCK_CMP1_MODE0 0x80
+#define QSERDES_V10_COM_LOCK_CMP2_MODE0 0x84
+#define QSERDES_V10_COM_DEC_START_MODE0 0x88
+#define QSERDES_V10_COM_DEC_START_MSB_MODE0 0x8c
+#define QSERDES_V10_COM_DIV_FRAC_START1_MODE0 0x90
+#define QSERDES_V10_COM_DIV_FRAC_START2_MODE0 0x94
+#define QSERDES_V10_COM_DIV_FRAC_START3_MODE0 0x98
+#define QSERDES_V10_COM_HSCLK_HS_SWITCH_SEL_1 0x9c
+#define QSERDES_V10_COM_INTEGLOOP_GAIN0_MODE0 0xa0
+#define QSERDES_V10_COM_INTEGLOOP_GAIN1_MODE0 0xa4
+#define QSERDES_V10_COM_VCO_TUNE1_MODE0 0xa8
+#define QSERDES_V10_COM_VCO_TUNE2_MODE0 0xac
+#define QSERDES_V10_COM_BG_TIMER 0xbc
+#define QSERDES_V10_COM_SSC_EN_CENTER 0xc0
+#define QSERDES_V10_COM_SSC_ADJ_PER1 0xc4
+#define QSERDES_V10_COM_SSC_PER1 0xcc
+#define QSERDES_V10_COM_SSC_PER2 0xd0
+#define QSERDES_V10_COM_POST_DIV_MUX 0xd8
+#define QSERDES_V10_COM_BIAS_EN_CLKBUFLR_EN 0xdc
+#define QSERDES_V10_COM_CLK_ENABLE1 0xe0
+#define QSERDES_V10_COM_SYS_CLK_CTRL 0xe4
+#define QSERDES_V10_COM_SYSCLK_BUF_ENABLE 0xe8
+#define QSERDES_V10_COM_PLL_IVCO 0xf4
+#define QSERDES_V10_COM_PLL_IVCO_MODE1 0xf8
+#define QSERDES_V10_COM_CMN_IETRIM 0xfc
+#define QSERDES_V10_COM_CMN_IPTRIM 0x100
+#define QSERDES_V10_COM_SYSCLK_EN_SEL 0x110
+#define QSERDES_V10_COM_RESETSM_CNTRL 0x118
+#define QSERDES_V10_COM_LOCK_CMP_EN 0x120
+#define QSERDES_V10_COM_LOCK_CMP_CFG 0x124
+#define QSERDES_V10_COM_VCO_TUNE_CTRL 0x13c
+#define QSERDES_V10_COM_VCO_TUNE_MAP 0x140
+#define QSERDES_V10_COM_VCO_TUNE_INITVAL2 0x148
+#define QSERDES_V10_COM_VCO_TUNE_MAXVAL2 0x158
+#define QSERDES_V10_COM_CLK_SELECT 0x164
+#define QSERDES_V10_COM_CORE_CLK_EN 0x170
+#define QSERDES_V10_COM_CMN_CONFIG_1 0x174
+#define QSERDES_V10_COM_SVS_MODE_CLK_SEL 0x17c
+#define QSERDES_V10_COM_CMN_MISC_1 0x184
+#define QSERDES_V10_COM_CMN_MODE 0x188
+#define QSERDES_V10_COM_PLL_VCO_DC_LEVEL_CTRL 0x198
+#define QSERDES_V10_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4
+#define QSERDES_V10_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8
+#define QSERDES_V10_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac
+#define QSERDES_V10_COM_ADDITIONAL_MISC 0x1b4
+#define QSERDES_V10_COM_ADDITIONAL_MISC_2 0x1b8
+#define QSERDES_V10_COM_ADDITIONAL_MISC_3 0x1bc
+#define QSERDES_V10_COM_CMN_STATUS 0x2c8
+#define QSERDES_V10_COM_C_READY_STATUS 0x2f0
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h
new file mode 100644
index 000000000000..84f1adee5ff7
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V10_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_V10_H_
+
+/* Only for QMP V10 PHY - QSERDES TX/RX registers */
+
+/* TX registers */
+#define QSERDES_V10_TX_CLKBUF_ENABLE 0x08
+#define QSERDES_V10_TX_TX_EMP_POST1_LVL 0x0c
+#define QSERDES_V10_TX_TX_DRV_LVL 0x14
+#define QSERDES_V10_TX_RESET_TSYNC_EN 0x1c
+#define QSERDES_V10_TX_PRE_STALL_LDO_BOOST_EN 0x20
+#define QSERDES_V10_TX_TX_BAND 0x24
+#define QSERDES_V10_TX_INTERFACE_SELECT 0x2c
+#define QSERDES_V10_TX_RES_CODE_LANE_TX 0x34
+#define QSERDES_V10_TX_RES_CODE_LANE_RX 0x38
+#define QSERDES_V10_TX_RES_CODE_LANE_OFFSET_TX 0x3c
+#define QSERDES_V10_TX_RES_CODE_LANE_OFFSET_RX 0x40
+#define QSERDES_V10_TX_TRANSCEIVER_BIAS_EN 0x54
+#define QSERDES_V10_TX_HIGHZ_DRVR_EN 0x58
+#define QSERDES_V10_TX_TX_POL_INV 0x5c
+#define QSERDES_V10_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
+#define QSERDES_V10_TX_BIST_PATTERN7 0x7c
+#define QSERDES_V10_TX_LANE_MODE_1 0x84
+#define QSERDES_V10_TX_LANE_MODE_2 0x88
+#define QSERDES_V10_TX_LANE_MODE_3 0x8c
+#define QSERDES_V10_TX_LANE_MODE_4 0x90
+#define QSERDES_V10_TX_LANE_MODE_5 0x94
+#define QSERDES_V10_TX_RCV_DETECT_LVL_2 0xa4
+#define QSERDES_V10_TX_TRAN_DRVR_EMP_EN 0xc0
+#define QSERDES_V10_TX_TX_INTERFACE_MODE 0xc4
+#define QSERDES_V10_TX_VMODE_CTRL1 0xc8
+#define QSERDES_V10_TX_PI_QEC_CTRL 0xe4
+
+/* RX registers */
+#define QSERDES_V10_RX_UCDR_FO_GAIN 0x08
+#define QSERDES_V10_RX_UCDR_SO_GAIN 0x14
+#define QSERDES_V10_RX_UCDR_FASTLOCK_FO_GAIN 0x30
+#define QSERDES_V10_RX_UCDR_SO_SATURATION_AND_ENABLE 0x34
+#define QSERDES_V10_RX_UCDR_FASTLOCK_COUNT_LOW 0x3c
+#define QSERDES_V10_RX_UCDR_FASTLOCK_COUNT_HIGH 0x40
+#define QSERDES_V10_RX_UCDR_PI_CONTROLS 0x44
+#define QSERDES_V10_RX_UCDR_SB2_THRESH1 0x4c
+#define QSERDES_V10_RX_UCDR_SB2_THRESH2 0x50
+#define QSERDES_V10_RX_UCDR_SB2_GAIN1 0x54
+#define QSERDES_V10_RX_UCDR_SB2_GAIN2 0x58
+#define QSERDES_V10_RX_AUX_DATA_TCOARSE_TFINE 0x60
+#define QSERDES_V10_RX_TX_ADAPT_POST_THRESH 0xcc
+#define QSERDES_V10_RX_VGA_CAL_CNTRL1 0xd4
+#define QSERDES_V10_RX_VGA_CAL_CNTRL2 0xd8
+#define QSERDES_V10_RX_GM_CAL 0xdc
+#define QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL2 0xec
+#define QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL3 0xf0
+#define QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL4 0xf4
+#define QSERDES_V10_RX_RX_IDAC_TSETTLE_LOW 0xf8
+#define QSERDES_V10_RX_RX_IDAC_TSETTLE_HIGH 0xfc
+#define QSERDES_V10_RX_RX_IDAC_ENABLES 0x100
+#define QSERDES_V10_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x104
+#define QSERDES_V10_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
+#define QSERDES_V10_RX_SIGDET_ENABLES 0x118
+#define QSERDES_V10_RX_SIGDET_CNTRL 0x11c
+#define QSERDES_V10_RX_SIGDET_DEGLITCH_CNTRL 0x124
+#define QSERDES_V10_RX_RX_MODE_00_LOW 0x15c
+#define QSERDES_V10_RX_RX_MODE_00_HIGH 0x160
+#define QSERDES_V10_RX_RX_MODE_00_HIGH2 0x164
+#define QSERDES_V10_RX_RX_MODE_00_HIGH3 0x168
+#define QSERDES_V10_RX_RX_MODE_00_HIGH4 0x16c
+#define QSERDES_V10_RX_RX_MODE_01_LOW 0x170
+#define QSERDES_V10_RX_RX_MODE_01_HIGH 0x174
+#define QSERDES_V10_RX_RX_MODE_01_HIGH2 0x178
+#define QSERDES_V10_RX_RX_MODE_01_HIGH3 0x17c
+#define QSERDES_V10_RX_RX_MODE_01_HIGH4 0x180
+#define QSERDES_V10_RX_RX_MODE_10_LOW 0x184
+#define QSERDES_V10_RX_RX_MODE_10_HIGH 0x188
+#define QSERDES_V10_RX_RX_MODE_10_HIGH2 0x18c
+#define QSERDES_V10_RX_RX_MODE_10_HIGH3 0x190
+#define QSERDES_V10_RX_RX_MODE_10_HIGH4 0x194
+#define QSERDES_V10_RX_DFE_EN_TIMER 0x1a0
+#define QSERDES_V10_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
+#define QSERDES_V10_RX_DCC_CTRL1 0x1a8
+#define QSERDES_V10_RX_VTH_CODE 0x1b0
+#define QSERDES_V10_RX_SIGDET_CAL_CTRL1 0x1e4
+#define QSERDES_V10_RX_SIGDET_CAL_TRIM 0x1f8
+
+#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index a873bdd7bffe..7af77572970e 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -39,6 +39,9 @@
#include "phy-qcom-qmp-qserdes-txrx-v8.h"
#include "phy-qcom-qmp-qserdes-lalb-v8.h"
+#include "phy-qcom-qmp-qserdes-com-v10.h"
+#include "phy-qcom-qmp-qserdes-txrx-v10.h"
+
#include "phy-qcom-qmp-qserdes-pll.h"
#include "phy-qcom-qmp-pcs-v2.h"
@@ -65,6 +68,8 @@
#include "phy-qcom-qmp-pcs-v8_50.h"
+#include "phy-qcom-qmp-pcs-v10.h"
+
/* QPHY_SW_RESET bit */
#define SW_RESET BIT(0)
/* QPHY_POWER_DOWN_CONTROL */
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH 3/4] dt-bindings: usb: qcom,snps-dwc3: Add Hawi compatible
From: Ronak Raheja @ 2026-04-27 21:42 UTC (permalink / raw)
To: vkoul, krzk+dt, conor+dt, robh, neil.armstrong, gregkh
Cc: dmitry.baryshkov, konrad.dybcio, abel.vesa, wesley.cheng,
krzysztof.kozlowski, ronak.raheja, linux-arm-msm, linux-phy,
devicetree, linux-usb, linux-kernel
In-Reply-To: <20260427214217.2735240-1-ronak.raheja@oss.qualcomm.com>
Document the Synopsys DWC3 USB controller found on the Hawi platform.
Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
index 8201656b41ed..2d10994f7b44 100644
--- a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
@@ -27,6 +27,7 @@ properties:
- qcom,eliza-dwc3
- qcom,glymur-dwc3
- qcom,glymur-dwc3-mp
+ - qcom,hawi-dwc3
- qcom,ipq4019-dwc3
- qcom,ipq5018-dwc3
- qcom,ipq5332-dwc3
@@ -203,6 +204,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,hawi-dwc3
- qcom,ipq5424-dwc3
- qcom,ipq9574-dwc3
- qcom,kaanapali-dwc3
@@ -540,6 +542,7 @@ allOf:
contains:
enum:
- qcom,eliza-dwc3
+ - qcom,hawi-dwc3
- qcom,ipq4019-dwc3
- qcom,ipq8064-dwc3
- qcom,kaanapali-dwc3
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH 2/4] dt-bindings: phy: qcom,m31-eusb2-phy: Document M31 eUSB2 PHY for Hawi
From: Ronak Raheja @ 2026-04-27 21:42 UTC (permalink / raw)
To: vkoul, krzk+dt, conor+dt, robh, neil.armstrong, gregkh
Cc: dmitry.baryshkov, konrad.dybcio, abel.vesa, wesley.cheng,
krzysztof.kozlowski, ronak.raheja, linux-arm-msm, linux-phy,
devicetree, linux-usb, linux-kernel
In-Reply-To: <20260427214217.2735240-1-ronak.raheja@oss.qualcomm.com>
Document the M31 eUSB2 PHY for Hawi which handles the USB2 path. Use
fallback to indicate the compatibility of the M31 eUSB2 PHY on the Hawi
with that on the SM8750.
Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml
index cd6b84213a7c..c0e7e2963ce6 100644
--- a/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml
@@ -19,6 +19,7 @@ properties:
- items:
- enum:
- qcom,glymur-m31-eusb2-phy
+ - qcom,hawi-m31-eusb2-phy
- qcom,kaanapali-m31-eusb2-phy
- const: qcom,sm8750-m31-eusb2-phy
- const: qcom,sm8750-m31-eusb2-phy
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v2 0/4] phy: qcom: Introduce USB support for Hawi
From: Ronak Raheja @ 2026-04-27 21:42 UTC (permalink / raw)
To: vkoul, krzk+dt, conor+dt, robh, neil.armstrong, gregkh
Cc: dmitry.baryshkov, konrad.dybcio, abel.vesa, wesley.cheng,
krzysztof.kozlowski, ronak.raheja, linux-arm-msm, linux-phy,
devicetree, linux-usb, linux-kernel
This series adds USB PHY support for the Hawi SoC. It documents the
QMP USB3-DP combo PHY and M31 eUSB2 PHY bindings, adds the Hawi
compatible to the DWC3 USB binding, and adds the PHY initialization
sequences to the qmp-combo driver.
---
Changes in v2:
- Clarify in the QMP PHY binding commit message why Hawi needs a
dedicated compatible string vs previous targets
- Remove stray blank line in hawi_usb3_rx_tbl
- Link to v1: https://lore.kernel.org/all/20260425070002.348733-1-ronak.raheja@oss.qualcomm.com/
Ronak Raheja (4):
dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Hawi QMP PHY
dt-bindings: phy: qcom,m31-eusb2-phy: Document M31 eUSB2 PHY for Hawi
dt-bindings: usb: qcom,snps-dwc3: Add Hawi compatible
phy: qualcomm: qmp-combo: Add support for Hawi SoC
.../bindings/phy/qcom,m31-eusb2-phy.yaml | 1 +
.../phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | 2 +
.../bindings/usb/qcom,snps-dwc3.yaml | 3 +
.../phy/qualcomm/phy-qcom-qmp-com-aon-v10.h | 15 ++
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 231 +++++++++++++++++-
.../phy/qualcomm/phy-qcom-qmp-dp-phy-v10.h | 15 ++
.../phy/qualcomm/phy-qcom-qmp-pcs-aon-v10.h | 13 +
.../phy/qualcomm/phy-qcom-qmp-pcs-usb-v10.h | 19 ++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h | 34 +++
.../qualcomm/phy-qcom-qmp-qserdes-com-v10.h | 89 +++++++
.../qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h | 89 +++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 5 +
12 files changed, 512 insertions(+), 4 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-com-aon-v10.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v10.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v10.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v10.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* [PATCH 1/4] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Hawi QMP PHY
From: Ronak Raheja @ 2026-04-27 21:42 UTC (permalink / raw)
To: vkoul, krzk+dt, conor+dt, robh, neil.armstrong, gregkh
Cc: dmitry.baryshkov, konrad.dybcio, abel.vesa, wesley.cheng,
krzysztof.kozlowski, ronak.raheja, linux-arm-msm, linux-phy,
devicetree, linux-usb, linux-kernel
In-Reply-To: <20260427214217.2735240-1-ronak.raheja@oss.qualcomm.com>
Document the Hawi compatible string for the QMP combo PHY.
Hawi uses a new QSERDES V10 register layout with a new COM AON module
and hardware-specific PHY init sequences compared to previous targets,
requiring a dedicated compatible string.
Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
---
.../devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
index 3d537b7f9985..7a7059c659be 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
@@ -22,6 +22,7 @@ properties:
- const: qcom,sm8750-qmp-usb3-dp-phy
- enum:
- qcom,glymur-qmp-usb3-dp-phy
+ - qcom,hawi-qmp-usb3-dp-phy
- qcom,sar2130p-qmp-usb3-dp-phy
- qcom,sc7180-qmp-usb3-dp-phy
- qcom,sc7280-qmp-usb3-dp-phy
@@ -205,6 +206,7 @@ allOf:
contains:
enum:
- qcom,glymur-qmp-usb3-dp-phy
+ - qcom,hawi-qmp-usb3-dp-phy
- qcom,sar2130p-qmp-usb3-dp-phy
- qcom,sc8280xp-qmp-usb43dp-phy
- qcom,sm6350-qmp-usb3-dp-phy
--
2.34.1
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^ permalink raw reply related
* [PATCH] phy: renesas: phy-rzg3e-usb3: Fix runtime PM underflow during suspend
From: Ovidiu Panait @ 2026-04-27 19:47 UTC (permalink / raw)
To: vkoul, neil.armstrong, biju.das.jz
Cc: linux-phy, linux-kernel, linux-renesas-soc, Ovidiu Panait
On the Renesas RZ/V2H platform, if the xhcd driver is unbound and the
system is suspended afterwards, a PM underflow error will occur:
# echo 15850000.usb > /sys/bus/platform/drivers/xhci-renesas-hcd/unbind
# systemctl suspend
15870000.usb-phy: PM: dpm_run_callback(): genpd_resume_noirq returns -13
15870000.usb-phy: PM: failed to resume noirq: error -13
15870000.usb-phy: Runtime PM usage count underflow!
Since the PHY framework is managing the runtime PM of the PHY via
phy_power_on()/phy_power_off(), there is no need for the PHY driver to
manipulate the runtime PM state during suspend.
To fix this, remove the runtime PM calls from the suspend/resume paths
and add a get/put pair inside rzg3e_phy_usb3_init_helper() to make sure
the clock is enabled during init, even when there is no consumer for
the PHY.
Also, change the suspend ops from NOIRQ_SYSTEM_SLEEP_PM_OPS to
SYSTEM_SLEEP_PM_OPS because runtime PM is disabled during the noirq phase
and pm_runtime_resume_and_get() would not actually enable the device clock.
Fixes: ee5f1a3f90a4 ("phy: renesas: Add Renesas RZ/G3E USB3.0 PHY driver")
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
drivers/phy/renesas/phy-rzg3e-usb3.c | 31 ++++++++++++++++------------
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/drivers/phy/renesas/phy-rzg3e-usb3.c b/drivers/phy/renesas/phy-rzg3e-usb3.c
index 6b3453ea0004..055775e1a0f7 100644
--- a/drivers/phy/renesas/phy-rzg3e-usb3.c
+++ b/drivers/phy/renesas/phy-rzg3e-usb3.c
@@ -64,6 +64,7 @@
#define USB3_TEST_LANECONFIG0_DEFAULT (0xd)
struct rz_usb3 {
+ struct device *dev;
void __iomem *base;
struct reset_control *rstc;
bool skip_reinit;
@@ -130,11 +131,21 @@ static int rzg3e_phy_usb3test_phy_init(void __iomem *base)
return 0;
}
-static int rzg3e_phy_usb3_init_helper(void __iomem *base)
+static int rzg3e_phy_usb3_init_helper(struct rz_usb3 *r)
{
- rzg3e_phy_usb2test_phy_init(base);
+ int ret;
+
+ ret = pm_runtime_resume_and_get(r->dev);
+ if (ret)
+ return ret;
+
+ rzg3e_phy_usb2test_phy_init(r->base);
- return rzg3e_phy_usb3test_phy_init(base);
+ ret = rzg3e_phy_usb3test_phy_init(r->base);
+
+ pm_runtime_put_sync(r->dev);
+
+ return ret;
}
static int rzg3e_phy_usb3_init(struct phy *p)
@@ -143,7 +154,7 @@ static int rzg3e_phy_usb3_init(struct phy *p)
int ret = 0;
if (!r->skip_reinit)
- ret = rzg3e_phy_usb3_init_helper(r->base);
+ ret = rzg3e_phy_usb3_init_helper(r);
return ret;
}
@@ -187,6 +198,7 @@ static int rzg3e_phy_usb3_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, r);
phy_set_drvdata(phy, r);
+ r->dev = dev;
provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
if (IS_ERR(provider))
@@ -199,7 +211,6 @@ static int rzg3e_phy_usb3_suspend(struct device *dev)
{
struct rz_usb3 *r = dev_get_drvdata(dev);
- pm_runtime_put(dev);
reset_control_assert(r->rstc);
r->skip_reinit = false;
@@ -215,27 +226,21 @@ static int rzg3e_phy_usb3_resume(struct device *dev)
if (ret)
return ret;
- ret = pm_runtime_resume_and_get(dev);
+ ret = rzg3e_phy_usb3_init_helper(r);
if (ret)
goto reset_assert;
- ret = rzg3e_phy_usb3_init_helper(r->base);
- if (ret)
- goto pm_put;
-
r->skip_reinit = true;
return 0;
-pm_put:
- pm_runtime_put(dev);
reset_assert:
reset_control_assert(r->rstc);
return ret;
}
static const struct dev_pm_ops rzg3e_phy_usb3_pm = {
- NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg3e_phy_usb3_suspend, rzg3e_phy_usb3_resume)
+ SYSTEM_SLEEP_PM_OPS(rzg3e_phy_usb3_suspend, rzg3e_phy_usb3_resume)
};
static const struct of_device_id rzg3e_phy_usb3_match_table[] = {
--
2.34.1
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^ permalink raw reply related
* Re: [PATCH v2 0/4] phy: phy-can-transceiver: Ad-hoc cleanups and refactoring
From: Andy Shevchenko @ 2026-04-27 15:26 UTC (permalink / raw)
To: Josua Mayer
Cc: linux-can@vger.kernel.org, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org, Marc Kleine-Budde, Vincent Mailhol,
Vinod Koul, Neil Armstrong, Ulf Hansson
In-Reply-To: <5d4c3c95-cbe1-4439-8036-b014264ce8c2@solid-run.com>
On Mon, Apr 27, 2026 at 01:41:43PM +0000, Josua Mayer wrote:
> Am 27.04.26 um 15:34 schrieb Andy Shevchenko:
> > On Mon, Apr 27, 2026 at 11:09:48AM +0000, Josua Mayer wrote:
> >> Am 14.04.26 um 20:43 schrieb Andy Shevchenko:
> >>> On Tue, Mar 17, 2026 at 09:27:26PM +0100, Andy Shevchenko wrote:
...
> >> For unknown reason your patch-set did not arrive in my inbox.
> >> Perhaps it went missing for others, too?
> > Are you in the MAINTAINERS for this part of the kernel?
> > The CAN NETWORK DRIVERS and GENERIC PHY FRAMEWORK do not list your name.
> Correct. I touched can phy once related to mux only.
> > If you think of mail delivery in general, it's delivered at least to the ML
> > https://lore.kernel.org/all/20260317203001.2108568-1-andriy.shevchenko@linux.intel.com/
> >
> > TBH I don't know what to answer to your question as I don't know your expectations and
> > how it should be fulfilled taking into account my above question...
>
> Changelog v2:
> - Cc'ed to Ulf and Josua due to above
>
> This is why I expected it in my inbox.
> Usually in this situation I blame my provider.
Ah, blame me then. I most likely missed to add your name to the Cc list.
> > But thanks for the reviewing! I will address the commit message in v3.
> Great!
And will try hard to make sure your address will be in the Cc list.
--
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^ permalink raw reply
* Re: [PATCH v22 4/8] drm: bridge: Cadence: Add MHDP8501 DP/HDMI driver
From: Laurentiu Palcu @ 2026-04-27 14:35 UTC (permalink / raw)
To: Luca Ceresoli
Cc: Parshuram Thombare, Swapnil Jakhade, Dmitry Baryshkov,
Nikhil Devshatwar, Jayesh Choudhary, Andrzej Hajda,
Neil Armstrong, Robert Foss, Laurent Pinchart, Jonas Karlman,
Jernej Skrabec, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, dri-devel,
devicetree, linux-kernel, linux-phy, imx, linux-arm-kernel, linux,
Alexander Stein, Ying Liu
In-Reply-To: <DI3YF7J7ZW0P.3OKMUXAM7GW5C@bootlin.com>
Hi Luca,
On Mon, Apr 27, 2026 at 02:59:51PM +0200, Luca Ceresoli wrote:
> Hello Laurentiu,
>
> On Fri Apr 24, 2026 at 1:07 PM CEST, Laurentiu Palcu wrote:
> > From: Sandor Yu <Sandor.yu@nxp.com>
> >
> > Add a new DRM DisplayPort and HDMI bridge driver for Candence MHDP8501
> > used in i.MX8MQ SOC. MHDP8501 could support HDMI or DisplayPort
> > standards according embedded Firmware running in the uCPU.
> >
> > For iMX8MQ SOC, the DisplayPort/HDMI FW was loaded and activated by
> > SOC's ROM code. Bootload binary included respective specific firmware
> > is required.
> >
> > Driver will check display connector type and
> > then load the corresponding driver.
> >
> > Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
> > Co-developed-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
> > Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
>
> ...
>
> > +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c
> ...
> > +enum drm_connector_status cdns_mhdp8501_detect(struct drm_bridge *bridge,
> > + struct drm_connector *connector)
> > +{
> > + struct cdns_mhdp8501_device *mhdp = bridge->driver_private;
>
> Please don't use driver_private. Write a oneliner function wrapping
> container_of(). There are many examples in bridges,
> e.g. bridge_to_sn65dsi83().
ack
>
> > +static int cdns_mhdp8501_get_bridge_type(struct device_node *out_ep,
> > + int *bridge_type)
> > +{
> > + struct device_node *incoming_ep, *node, *ep;
> > + int ret = -ENODEV;
> > +
> > + incoming_ep = of_graph_get_remote_endpoint(out_ep);
> > + if (!incoming_ep)
> > + return -ENODEV;
> > +
> > + node = of_graph_get_port_parent(incoming_ep);
> > + if (!node) {
> > + of_node_put(incoming_ep);
> > + return -ENODEV;
> > + }
> > +
> > + if (of_device_is_compatible(node, "hdmi-connector")) {
> > + *bridge_type = DRM_MODE_CONNECTOR_HDMIA;
> > + ret = 0;
> > + } else if (of_device_is_compatible(node, "dp-connector")) {
> > + *bridge_type = DRM_MODE_CONNECTOR_DisplayPort;
> > + ret = 0;
> > + } else {
> > + for_each_endpoint_of_node(node, ep) {
> > + if (ep == incoming_ep)
> > + continue;
> > +
> > + ret = cdns_mhdp8501_get_bridge_type(ep, bridge_type);
> > + if (!ret) {
> > + of_node_put(ep);
> > + break;
> > + }
> > + }
> > + }
>
> I don't follow what this logic is doing. Can you provide a practical
> example of the "next node" (@node variable) where you fall in the else
> case?
The else would be hit when there's another bridge after this one. But I
don't have a practical example since, on the i.MX8MQ, there is no other
bridge after it. However, as reviewers pointed out in earlier patchset
iterations, we needed to make it generic.
>
> Also, while this resursion will probably work in most, if not all,
> realistic cases, it could take incorrect decisions. Consider the case there
> in the else branch your @node points to some node having two input
> endpoints: ep0 is the incoming_ep and ep1 is another input endpoint. In
> such case you would recurse on ep1 and return its bridge type, which
> however has nothing to to with the output and might be incorrect.
I believe you are right, I assumed each bridge has only one input
endpoint and one output endpoint... :/
>
> Another question is whether this driver should have two compatible strings,
> one for hdmi and one for dp, and set the bridge_type based on that. This
> would make it a lot simpler and remove the need for this function.
I think this is a good idea. I see no reason why having 2 different
compatibles wouldn't work. I'll give it a try.
>
> But if I guess right from the code, this device can output either hdmi or
> dp, and the implementation infers the type based on this device tree
> walk. Is it the case?
Yes, based on the PHY firmware (which is loaded by the ROM) we can have
HDMI or DP functionality.
>
> > +static int cdns_mhdp8501_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct cdns_mhdp8501_device *mhdp;
> > + const struct drm_bridge_funcs *bridge_funcs;
> > + enum phy_mode phy_mode;
> > + struct resource *res;
> > + u32 lane_mapping;
> > + int bridge_type;
> > + u32 reg;
> > + int ret;
> > +
> > + ret = cdns_mhdp8501_dt_parse(pdev, &bridge_type, &lane_mapping);
> > + if (ret < 0)
> > + return ret;
> > +
> > + ret = devm_of_platform_populate(dev);
> > + if (ret)
> > + return ret;
> > +
> > + bridge_funcs = (bridge_type == DRM_MODE_CONNECTOR_HDMIA) ?
> > + &cdns_hdmi_bridge_funcs : &cdns_dp_bridge_funcs;
> > +
> > + mhdp = devm_drm_bridge_alloc(dev, struct cdns_mhdp8501_device,
> > + bridge, bridge_funcs);
> > + if (!mhdp)
> > + return -ENOMEM;
> > +
> > + mhdp->dev = dev;
> > + mhdp->bridge_type = bridge_type;
> > + mhdp->lane_mapping = lane_mapping;
> > +
> > + mhdp->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
> > + if (IS_ERR(mhdp->next_bridge))
> > + return dev_err_probe(dev, PTR_ERR(mhdp->next_bridge),
> > + "failed to get next bridge\n");
>
> devm_drm_of_get_bridge() is there to either create a new panel_bridge
> wrapping a panel or return an existing bridge. However based on the
> cdns_mhdp8501_get_bridge_type() code it seems to me that you will always
> have another bridge after this bridge. And so instead of
> devm_drm_of_get_bridge() you should use of_drm_find_and_get_bridge(),
> which handles bridge refcounting.
Ok, I'll switch to of_drm_find_and_get_bridge().
>
> When switching to it, you additionally can use the drm_bridge::next_bridge
> pointer instead of having your mhdp->next_bridge. This will simplify
> putting the bridge reference. An example of its usage is in [0].
>
> [0] https://lore.kernel.org/lkml/20260109-drm-bridge-alloc-getput-drm_of_find_bridge-2-v2-4-8bad3ef90b9f@bootlin.com/
>
> > +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c
> ...
> > +static int cdns_dp_bridge_attach(struct drm_bridge *bridge,
> > + struct drm_encoder *encoder,
> > + enum drm_bridge_attach_flags flags)
> > +{
> > + struct cdns_mhdp8501_device *mhdp = bridge->driver_private;
> > + int ret;
> > +
> > + ret = drm_bridge_attach(encoder, mhdp->next_bridge, bridge,
> > + flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> > + if (ret < 0)
> > + return ret;
> > +
> > + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
> > + dev_err(mhdp->dev, "do not support creating a drm_connector\n");
> > + return -EINVAL;
> > + }
>
> Any good reason for doing this check after calling drm_bridge_attach()? It
> looks to me that you should first check for valid arguments, and if they
> pass take any actions.
There's no good reason for this. I'll move the check at the beginning.
>
> Same below for the HDMI version.
will do.
Thank you for your review.
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^ permalink raw reply
* Re: [PATCH v22 5/8] dt-bindings: phy: Add Freescale iMX8MQ DP and HDMI PHY
From: Laurentiu Palcu @ 2026-04-27 14:35 UTC (permalink / raw)
To: Luca Ceresoli
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, dri-devel, devicetree, linux-kernel, linux-phy,
imx, linux-arm-kernel, linux, Alexander Stein, Ying Liu
In-Reply-To: <DI3YF5Y2B3GZ.25AP4NKQAXH36@bootlin.com>
Hi Luca,
On Mon, Apr 27, 2026 at 02:59:47PM +0200, Luca Ceresoli wrote:
> Hello Laurentiu,
>
> On Fri Apr 24, 2026 at 1:07 PM CEST, Laurentiu Palcu wrote:
> > From: Sandor Yu <Sandor.yu@nxp.com>
> >
> > Add bindings for Freescale iMX8MQ DP and HDMI PHY.
> >
> > Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
> > Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
> > ---
> > .../bindings/phy/fsl,imx8mq-hdptx-phy.yaml | 80 ++++++++++++++++++++++
> > 1 file changed, 80 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-hdptx-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mq-hdptx-phy.yaml
> > new file mode 100644
> > index 0000000000000..a24435139b8b3
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-hdptx-phy.yaml
> > @@ -0,0 +1,80 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/fsl,imx8mq-hdptx-phy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Cadence HDP-TX DP/HDMI PHY for Freescale i.MX8MQ SoC
> > +
> > +maintainers:
> > + - Sandor Yu <sandor.yu@nxp.com>
>
> Based on what you said in the cover, I guess this line will have to be
> changed. Are you willing to maintain this binding?
Yes, I'll update it in the next iteration.
>
> > +description:
> > + The Cadence HDP-TX DP/HDMI PHY is a child node of the MHDP8501 bridge,
> > + sharing the same MMIO region as the parent bridge node.
> > +
> > +properties:
> > + compatible:
> > + const: fsl,imx8mq-hdptx-phy
> > +
> > + clocks:
> > + items:
> > + - description: PHY reference clock.
> > + - description: APB clock.
> > +
> > + clock-names:
> > + items:
> > + - const: ref
> > + - const: apb
> > +
> > + "#phy-cells":
> > + const: 0
> > +
> > +required:
> > + - compatible
> > + - clocks
> > + - clock-names
> > + - "#phy-cells"
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/imx8mq-clock.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + display-bridge@32c00000 {
> > + compatible = "fsl,imx8mq-mhdp8501";
> > + reg = <0x32c00000 0x100000>;
> > + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "plug_in", "plug_out";
> > + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
> > + phys = <&dp_phy>;
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
>
> The ports are not mentioned in the properties. I'm not a DT maintainer, but
> I think they should, e.g. to mention which port is the input and which is
> the output.
>
> > +
> > + port@0 {
> > + reg = <0>;
> > + endpoint {
> > + remote-endpoint = <&dcss_out>;
> > + };
> > + };
> > +
> > + port@1 {
> > + reg = <1>;
> > + endpoint {
> > + data-lanes = <2 1 0 3>;
>
> Having a remote-endpoint property would be nice here, to make the example
> more complete.
The ports and the remote endpoints are documented in the bridge binding...
However, I believe I screwed this example up by adding the entire bridge node,
instead of just a simple:
mhdp {
phy {
compatible = "fsl,imx8mq-hdptx-phy";
#phy-cells = <0>;
clocks = <&hdmi_phy_27m>, <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
clock-names = "ref", "apb";
};
};
I'll simplify the example in the next iteration.
--
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^ permalink raw reply
* Re: [PATCH v2 0/4] phy: phy-can-transceiver: Ad-hoc cleanups and refactoring
From: Josua Mayer @ 2026-04-27 13:41 UTC (permalink / raw)
To: Andy Shevchenko
Cc: linux-can@vger.kernel.org, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org, Marc Kleine-Budde, Vincent Mailhol,
Vinod Koul, Neil Armstrong, Ulf Hansson
In-Reply-To: <ae9l4n8wocbVegcJ@ashevche-desk.local>
Am 27.04.26 um 15:34 schrieb Andy Shevchenko:
> On Mon, Apr 27, 2026 at 11:09:48AM +0000, Josua Mayer wrote:
>> Am 14.04.26 um 20:43 schrieb Andy Shevchenko:
>>> On Tue, Mar 17, 2026 at 09:27:26PM +0100, Andy Shevchenko wrote:
>>>> The driver does two things that need to be addressed:
>>>> - includes subject to remove gpio.h
>>>> - checks for error code from device property APIs when it can be done in
>>>> a robust way
>>>>
>>>> This series addresses the above and adds a couple of additional refactoring.
>>> Any comments on this? Doesn't look like it being applied so far...
>> For unknown reason your patch-set did not arrive in my inbox.
>> Perhaps it went missing for others, too?
> Are you in the MAINTAINERS for this part of the kernel?
> The CAN NETWORK DRIVERS and GENERIC PHY FRAMEWORK do not list your name.
Correct. I touched can phy once related to mux only.
> If you think of mail delivery in general, it's delivered at least to the ML
> https://lore.kernel.org/all/20260317203001.2108568-1-andriy.shevchenko@linux.intel.com/
>
> TBH I don't know what to answer to your question as I don't know your expectations and
> how it should be fulfilled taking into account my above question...
Changelog v2:
- Cc'ed to Ulf and Josua due to above
This is why I expected it in my inbox.
Usually in this situation I blame my provider.
>
> But thanks for the reviewing! I will address the commit message in v3.
Great!
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^ permalink raw reply
* Re: [PATCH v2 0/4] phy: phy-can-transceiver: Ad-hoc cleanups and refactoring
From: Andy Shevchenko @ 2026-04-27 13:34 UTC (permalink / raw)
To: Josua Mayer
Cc: linux-can@vger.kernel.org, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org, Marc Kleine-Budde, Vincent Mailhol,
Vinod Koul, Neil Armstrong, Ulf Hansson
In-Reply-To: <7bcb68c4-e4bd-4ad9-bb75-99e0845b204c@solid-run.com>
On Mon, Apr 27, 2026 at 11:09:48AM +0000, Josua Mayer wrote:
> Am 14.04.26 um 20:43 schrieb Andy Shevchenko:
> > On Tue, Mar 17, 2026 at 09:27:26PM +0100, Andy Shevchenko wrote:
> >> The driver does two things that need to be addressed:
> >> - includes subject to remove gpio.h
> >> - checks for error code from device property APIs when it can be done in
> >> a robust way
> >>
> >> This series addresses the above and adds a couple of additional refactoring.
> > Any comments on this? Doesn't look like it being applied so far...
> For unknown reason your patch-set did not arrive in my inbox.
> Perhaps it went missing for others, too?
Are you in the MAINTAINERS for this part of the kernel?
The CAN NETWORK DRIVERS and GENERIC PHY FRAMEWORK do not list your name.
If you think of mail delivery in general, it's delivered at least to the ML
https://lore.kernel.org/all/20260317203001.2108568-1-andriy.shevchenko@linux.intel.com/
TBH I don't know what to answer to your question as I don't know your expectations and
how it should be fulfilled taking into account my above question...
But thanks for the reviewing! I will address the commit message in v3.
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* Re: [PATCH v5 3/5] phy: qcom: edp: Add SC7280/SC8180X swing/pre-emphasis tables
From: Konrad Dybcio @ 2026-04-27 13:21 UTC (permalink / raw)
To: Yongxing Mou, Vinod Koul, Neil Armstrong, Stephen Boyd,
Bjorn Andersson
Cc: linux-arm-msm, linux-phy, linux-kernel
In-Reply-To: <20260427-edp_phy-v5-3-3bb876824475@oss.qualcomm.com>
On 4/27/26 8:35 AM, Yongxing Mou wrote:
> SC7280 and SC8180X previously shared the same cfg because they did not use
> swing/pre-emphasis tables. Add the corresponding tables for these
> platforms. Since they have different PHY sub-versions, their eDP/DP mode
> tables also differ, so move SC8180X to its own cfg instead of reusing the
> SC7280 one.
>
> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
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* Re: [PATCH v22 4/8] drm: bridge: Cadence: Add MHDP8501 DP/HDMI driver
From: Luca Ceresoli @ 2026-04-27 12:59 UTC (permalink / raw)
To: Laurentiu Palcu, Parshuram Thombare, Swapnil Jakhade,
Dmitry Baryshkov, Nikhil Devshatwar, Jayesh Choudhary,
Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter
Cc: dri-devel, devicetree, linux-kernel, linux-phy, imx,
linux-arm-kernel, linux, Alexander Stein, Ying Liu
In-Reply-To: <20260424-dcss-hdmi-upstreaming-v22-4-30a28f89298d@oss.nxp.com>
Hello Laurentiu,
On Fri Apr 24, 2026 at 1:07 PM CEST, Laurentiu Palcu wrote:
> From: Sandor Yu <Sandor.yu@nxp.com>
>
> Add a new DRM DisplayPort and HDMI bridge driver for Candence MHDP8501
> used in i.MX8MQ SOC. MHDP8501 could support HDMI or DisplayPort
> standards according embedded Firmware running in the uCPU.
>
> For iMX8MQ SOC, the DisplayPort/HDMI FW was loaded and activated by
> SOC's ROM code. Bootload binary included respective specific firmware
> is required.
>
> Driver will check display connector type and
> then load the corresponding driver.
>
> Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
> Co-developed-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
> Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
...
> +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c
...
> +enum drm_connector_status cdns_mhdp8501_detect(struct drm_bridge *bridge,
> + struct drm_connector *connector)
> +{
> + struct cdns_mhdp8501_device *mhdp = bridge->driver_private;
Please don't use driver_private. Write a oneliner function wrapping
container_of(). There are many examples in bridges,
e.g. bridge_to_sn65dsi83().
> +static int cdns_mhdp8501_get_bridge_type(struct device_node *out_ep,
> + int *bridge_type)
> +{
> + struct device_node *incoming_ep, *node, *ep;
> + int ret = -ENODEV;
> +
> + incoming_ep = of_graph_get_remote_endpoint(out_ep);
> + if (!incoming_ep)
> + return -ENODEV;
> +
> + node = of_graph_get_port_parent(incoming_ep);
> + if (!node) {
> + of_node_put(incoming_ep);
> + return -ENODEV;
> + }
> +
> + if (of_device_is_compatible(node, "hdmi-connector")) {
> + *bridge_type = DRM_MODE_CONNECTOR_HDMIA;
> + ret = 0;
> + } else if (of_device_is_compatible(node, "dp-connector")) {
> + *bridge_type = DRM_MODE_CONNECTOR_DisplayPort;
> + ret = 0;
> + } else {
> + for_each_endpoint_of_node(node, ep) {
> + if (ep == incoming_ep)
> + continue;
> +
> + ret = cdns_mhdp8501_get_bridge_type(ep, bridge_type);
> + if (!ret) {
> + of_node_put(ep);
> + break;
> + }
> + }
> + }
I don't follow what this logic is doing. Can you provide a practical
example of the "next node" (@node variable) where you fall in the else
case?
Also, while this resursion will probably work in most, if not all,
realistic cases, it could take incorrect decisions. Consider the case there
in the else branch your @node points to some node having two input
endpoints: ep0 is the incoming_ep and ep1 is another input endpoint. In
such case you would recurse on ep1 and return its bridge type, which
however has nothing to to with the output and might be incorrect.
Another question is whether this driver should have two compatible strings,
one for hdmi and one for dp, and set the bridge_type based on that. This
would make it a lot simpler and remove the need for this function.
But if I guess right from the code, this device can output either hdmi or
dp, and the implementation infers the type based on this device tree
walk. Is it the case?
> +static int cdns_mhdp8501_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct cdns_mhdp8501_device *mhdp;
> + const struct drm_bridge_funcs *bridge_funcs;
> + enum phy_mode phy_mode;
> + struct resource *res;
> + u32 lane_mapping;
> + int bridge_type;
> + u32 reg;
> + int ret;
> +
> + ret = cdns_mhdp8501_dt_parse(pdev, &bridge_type, &lane_mapping);
> + if (ret < 0)
> + return ret;
> +
> + ret = devm_of_platform_populate(dev);
> + if (ret)
> + return ret;
> +
> + bridge_funcs = (bridge_type == DRM_MODE_CONNECTOR_HDMIA) ?
> + &cdns_hdmi_bridge_funcs : &cdns_dp_bridge_funcs;
> +
> + mhdp = devm_drm_bridge_alloc(dev, struct cdns_mhdp8501_device,
> + bridge, bridge_funcs);
> + if (!mhdp)
> + return -ENOMEM;
> +
> + mhdp->dev = dev;
> + mhdp->bridge_type = bridge_type;
> + mhdp->lane_mapping = lane_mapping;
> +
> + mhdp->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
> + if (IS_ERR(mhdp->next_bridge))
> + return dev_err_probe(dev, PTR_ERR(mhdp->next_bridge),
> + "failed to get next bridge\n");
devm_drm_of_get_bridge() is there to either create a new panel_bridge
wrapping a panel or return an existing bridge. However based on the
cdns_mhdp8501_get_bridge_type() code it seems to me that you will always
have another bridge after this bridge. And so instead of
devm_drm_of_get_bridge() you should use of_drm_find_and_get_bridge(),
which handles bridge refcounting.
When switching to it, you additionally can use the drm_bridge::next_bridge
pointer instead of having your mhdp->next_bridge. This will simplify
putting the bridge reference. An example of its usage is in [0].
[0] https://lore.kernel.org/lkml/20260109-drm-bridge-alloc-getput-drm_of_find_bridge-2-v2-4-8bad3ef90b9f@bootlin.com/
> +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c
...
> +static int cdns_dp_bridge_attach(struct drm_bridge *bridge,
> + struct drm_encoder *encoder,
> + enum drm_bridge_attach_flags flags)
> +{
> + struct cdns_mhdp8501_device *mhdp = bridge->driver_private;
> + int ret;
> +
> + ret = drm_bridge_attach(encoder, mhdp->next_bridge, bridge,
> + flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> + if (ret < 0)
> + return ret;
> +
> + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
> + dev_err(mhdp->dev, "do not support creating a drm_connector\n");
> + return -EINVAL;
> + }
Any good reason for doing this check after calling drm_bridge_attach()? It
looks to me that you should first check for valid arguments, and if they
pass take any actions.
Same below for the HDMI version.
Luca
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* Re: [PATCH v22 5/8] dt-bindings: phy: Add Freescale iMX8MQ DP and HDMI PHY
From: Luca Ceresoli @ 2026-04-27 12:59 UTC (permalink / raw)
To: Laurentiu Palcu, Vinod Koul, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam
Cc: dri-devel, devicetree, linux-kernel, linux-phy, imx,
linux-arm-kernel, linux, Alexander Stein, Ying Liu
In-Reply-To: <20260424-dcss-hdmi-upstreaming-v22-5-30a28f89298d@oss.nxp.com>
Hello Laurentiu,
On Fri Apr 24, 2026 at 1:07 PM CEST, Laurentiu Palcu wrote:
> From: Sandor Yu <Sandor.yu@nxp.com>
>
> Add bindings for Freescale iMX8MQ DP and HDMI PHY.
>
> Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
> Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
> ---
> .../bindings/phy/fsl,imx8mq-hdptx-phy.yaml | 80 ++++++++++++++++++++++
> 1 file changed, 80 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-hdptx-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mq-hdptx-phy.yaml
> new file mode 100644
> index 0000000000000..a24435139b8b3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-hdptx-phy.yaml
> @@ -0,0 +1,80 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/fsl,imx8mq-hdptx-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Cadence HDP-TX DP/HDMI PHY for Freescale i.MX8MQ SoC
> +
> +maintainers:
> + - Sandor Yu <sandor.yu@nxp.com>
Based on what you said in the cover, I guess this line will have to be
changed. Are you willing to maintain this binding?
> +description:
> + The Cadence HDP-TX DP/HDMI PHY is a child node of the MHDP8501 bridge,
> + sharing the same MMIO region as the parent bridge node.
> +
> +properties:
> + compatible:
> + const: fsl,imx8mq-hdptx-phy
> +
> + clocks:
> + items:
> + - description: PHY reference clock.
> + - description: APB clock.
> +
> + clock-names:
> + items:
> + - const: ref
> + - const: apb
> +
> + "#phy-cells":
> + const: 0
> +
> +required:
> + - compatible
> + - clocks
> + - clock-names
> + - "#phy-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx8mq-clock.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + display-bridge@32c00000 {
> + compatible = "fsl,imx8mq-mhdp8501";
> + reg = <0x32c00000 0x100000>;
> + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "plug_in", "plug_out";
> + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
> + phys = <&dp_phy>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
The ports are not mentioned in the properties. I'm not a DT maintainer, but
I think they should, e.g. to mention which port is the input and which is
the output.
> +
> + port@0 {
> + reg = <0>;
> + endpoint {
> + remote-endpoint = <&dcss_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + endpoint {
> + data-lanes = <2 1 0 3>;
Having a remote-endpoint property would be nice here, to make the example
more complete.
Luca
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* Re: [PATCH v2] phy: renesas: rcar-gen3-usb2: Simplify ID/VBUS detection logic
From: Lad, Prabhakar @ 2026-04-27 11:36 UTC (permalink / raw)
To: Vinod Koul
Cc: Yoshihiro Shimoda, Pavel Machek, Magnus Damm, Geert Uytterhoeven,
Neil Armstrong, linux-renesas-soc, linux-phy, linux-kernel,
Biju Das, Fabrizio Castro, Lad Prabhakar
In-Reply-To: <20260325112039.464992-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Vinod,
On Wed, Mar 25, 2026 at 11:20 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Read USB2_ADPCTRL once in rcar_gen3_check_id() instead of issuing
> multiple MMIO reads, and derive both IDDIG and VBUSVALID from the same
> value.
>
> Drop the redundant !! operator, as assigning a masked u32 value to a
> bool already performs the required normalization. Simplify the logic by
> comparing the ID and VBUS status directly, which is equivalent to the
> previous conditional but easier to follow.
>
> Reported-by: Pavel Machek <pavel@nabladev.com>
> Closes: https://lore.kernel.org/all/acJVCOdlchLiSe5n@duo.ucw.cz/
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2:
> - Rebased on top of latest next-20260324
> - Combined variable declarations and assignments and dropped
> redundant !! operator
> - Updated commit message
> - Corrected the link for closes tag
> ---
> drivers/phy/renesas/phy-rcar-gen3-usb2.c | 10 ++++------
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
Gentle ping.
Cheers,
Prabhakar
> diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> index 79e820e2fe55..9a45d840efeb 100644
> --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> @@ -314,13 +314,11 @@ static void rcar_gen3_init_from_a_peri_to_a_host(struct rcar_gen3_chan *ch)
> static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
> {
> if (ch->phy_data->vblvl_ctrl) {
> - bool vbus_valid;
> - bool device;
> + u32 val = readl(ch->base + USB2_ADPCTRL);
> + bool vbus_valid = val & USB2_ADPCTRL_VBUSVALID;
> + bool device = val & USB2_ADPCTRL_IDDIG;
>
> - device = !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
> - vbus_valid = !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_VBUSVALID);
> -
> - return vbus_valid ? device : !device;
> + return device == vbus_valid;
> }
>
> if (!ch->uses_otg_pins)
> --
> 2.53.0
>
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* Re: [PATCH v2 1/4] phy: phy-can-transceiver: Convert to use device property API
From: Josua Mayer @ 2026-04-27 11:26 UTC (permalink / raw)
To: Andy Shevchenko, linux-can@vger.kernel.org,
linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: Marc Kleine-Budde, Vincent Mailhol, Vinod Koul, Neil Armstrong,
Ulf Hansson
In-Reply-To: <20260317203001.2108568-2-andriy.shevchenko@linux.intel.com>
Hi Andy,
Am 17.03.26 um 21:27 schrieb Andy Shevchenko:
> It seems the driver is half-moved to use device property APIs.
> Finish that by converting everything to use that.
As per v7.1-rc1 it seems you really just drop the last of_* function call,
while you're no adding any new device property call.
>
> While at it, drop unneeded argument to devm_phy_create() which
> extracts device node from the given device by default.
This was counter-intuitive to me at first,
but I confirmed it by reading in phy-core.c.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
> drivers/phy/phy-can-transceiver.c | 8 +++-----
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/phy/phy-can-transceiver.c b/drivers/phy/phy-can-transceiver.c
> index 2b52e47f247a..80eece74f77d 100644
> --- a/drivers/phy/phy-can-transceiver.c
> +++ b/drivers/phy/phy-can-transceiver.c
> @@ -5,9 +5,9 @@
> * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
> *
> */
> -#include <linux/of.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> +#include <linux/property.h>
> #include <linux/module.h>
> #include <linux/gpio.h>
> #include <linux/gpio/consumer.h>
> @@ -152,7 +152,6 @@ static int can_transceiver_phy_probe(struct platform_device *pdev)
> struct can_transceiver_phy *can_transceiver_phy;
> struct can_transceiver_priv *priv;
> const struct can_transceiver_data *drvdata;
> - const struct of_device_id *match;
> struct phy *phy;
> struct gpio_desc *silent_gpio;
> struct gpio_desc *standby_gpio;
> @@ -161,8 +160,7 @@ static int can_transceiver_phy_probe(struct platform_device *pdev)
> u32 max_bitrate = 0;
> int err, i, num_ch = 1;
>
> - match = of_match_node(can_transceiver_phy_ids, pdev->dev.of_node);
> - drvdata = match->data;
> + drvdata = device_get_match_data(dev);
> if (drvdata->flags & CAN_TRANSCEIVER_DUAL_CH)
> num_ch = 2;
>
> @@ -187,7 +185,7 @@ static int can_transceiver_phy_probe(struct platform_device *pdev)
> can_transceiver_phy = &priv->can_transceiver_phy[i];
> can_transceiver_phy->priv = priv;
>
> - phy = devm_phy_create(dev, dev->of_node, &can_transceiver_phy_ops);
> + phy = devm_phy_create(dev, NULL, &can_transceiver_phy_ops);
> if (IS_ERR(phy)) {
> dev_err(dev, "failed to create can transceiver phy\n");
> return PTR_ERR(phy);
Commit message seems sub-optimal, but code change looks good.
Reviewed-by: Josua Mayer <josua@solid-run.com>
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