* Re: [PATCH 4/8] phy: tegra: xusb: Use devm_clk_get_optional to fetch USB2 tracking clock
From: sashiko-bot @ 2026-06-29 9:46 UTC (permalink / raw)
To: Wayne Chang
Cc: neil.armstrong, linux-phy, vkoul, devicetree, olteanv, robh,
conor+dt
In-Reply-To: <20260629093406.1118594-5-waynec@nvidia.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
Pre-existing issues:
- [High] Double free of pad allocations on `tegra_xusb_pad_init()` failure due to incorrect device cleanup.
- [High] Kernel panic due to NULL pointer dereference in `tegra_xusb_port_release()` when port initialization fails.
--
commit 9a7eb66c6206c1b8eab420ee00c7a1d273a708fe
Author: Sing-Han Chen <singhanc@nvidia.com>
Subject: phy: tegra: xusb: Use devm_clk_get_optional to fetch USB2 tracking clock
This patch switches the USB2 tracking clock retrieval to use
devm_clk_get_optional. This allows the probe sequence to proceed safely
when the clock is omitted from the devicetree.
> diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c
> index 60156aea27071..800be0cbb3f9f 100644
> --- a/drivers/phy/tegra/xusb-tegra186.c
> +++ b/drivers/phy/tegra/xusb-tegra186.c
> @@ -1045,7 +1045,7 @@ tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
> goto out;
> }
[Severity: High]
This isn't a bug introduced by this patch, but does the error path for
tegra_xusb_pad_init() just above this change cause a double free?
Looking at tegra186_usb2_pad_probe(), if tegra_xusb_pad_init() fails, it
calls kfree(usb2).
However, inside tegra_xusb_pad_init(), an error causes it to jump to the
unregister label and call device_unregister(&pad->dev). This drops the
device reference and invokes the release callback tegra_xusb_pad_release(),
which frees the pad object.
When tegra_xusb_pad_init() returns the error back to the probe function, the
explicit kfree(usb2) is executed. Could this lead to memory corruption when
initialization fails?
>
> - priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk");
> + priv->usb2_trk_clk = devm_clk_get_optional(&pad->dev, "trk");
> if (IS_ERR(priv->usb2_trk_clk)) {
> err = PTR_ERR(priv->usb2_trk_clk);
> dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err);
[ ... ]
[Severity: High]
This is another pre-existing issue in a related file, but does
tegra_xusb_port_release() trigger a NULL pointer dereference on
initialization failure?
In drivers/phy/tegra/xusb.c:tegra_xusb_add_usb2_port(), the port is
allocated via kzalloc() and then initialized:
err = tegra_xusb_port_init(&usb2->base, padctl, np, "usb2", index);
if (err < 0)
goto out;
usb2->base.ops = padctl->soc->ports.usb2.ops;
Notice that the ops pointer is assigned after initialization completes.
If tegra_xusb_port_init() fails, it drops the device refcount and calls
tegra_xusb_port_release(). That release function attempts to evaluate the
ops pointer:
if (port->ops->release)
port->ops->release(port);
Since port->ops is not yet assigned during the init error path, it will
still be NULL from the kzalloc() allocation. Could this cause a panic when
initialization fails?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260629093406.1118594-1-waynec@nvidia.com?part=4
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* Re: [PATCH 6/8] phy: tegra: xusb: Add Tegra264 support
From: sashiko-bot @ 2026-06-29 9:45 UTC (permalink / raw)
To: Wayne Chang
Cc: olteanv, vkoul, conor+dt, neil.armstrong, linux-phy, robh,
devicetree
In-Reply-To: <20260629093406.1118594-7-waynec@nvidia.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Missing `.has_per_pad_term = true` for `tegra264_xusb_padctl_soc` leads to incorrect USB2 PHY termination calibration.
- [Low] Missing prototype compiler warning for `tegra264_xusb_padctl_soc` when its specific config is disabled.
--
commit 22b0fd28aa94a55231606c8cbbf28effe50f3f35
Author: Wayne Chang <waynec@nvidia.com>
phy: tegra: xusb: Add Tegra264 support
Add support for the XUSB pad controller for Tegra264. Most of the Tegra264
XUSB PADCTL registers definition and programming sequence are the same as
Tegra234, and they can share the same driver.
> diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c
> index 9c1bcd4a72ac6..3eb60ed09b687 100644
> --- a/drivers/phy/tegra/xusb-tegra186.c
> +++ b/drivers/phy/tegra/xusb-tegra186.c
[ ... ]
> @@ -1753,6 +1754,29 @@ const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc = {
> .has_per_pad_term = true,
> };
> EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc);
> +
> +const struct tegra_xusb_padctl_soc tegra264_xusb_padctl_soc = {
> + .num_pads = ARRAY_SIZE(tegra194_pads),
> + .pads = tegra194_pads,
> + .ports = {
> + .usb2 = {
> + .ops = &tegra186_usb2_port_ops,
> + .count = 4,
> + },
> + .usb3 = {
> + .ops = &tegra186_usb3_port_ops,
> + .count = 4,
> + },
> + },
> + .ops = &tegra186_xusb_padctl_ops,
> + .supply_names = tegra194_xusb_padctl_supply_names,
> + .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
> + .supports_gen2 = true,
> + .poll_trk_completed = true,
> + .trk_hw_mode = true,
> + .supports_lp_cfg_en = true,
> +};
[Severity: Medium]
Since the commit message states Tegra264 shares the same programming sequence
as Tegra234, should this struct also include .has_per_pad_term = true?
Without this flag, tegra186_xusb_read_fuse_calibration() will default to
copying pad 0's calibration to pads 1-3 instead of reading their specific
hardware values.
> +EXPORT_SYMBOL_GPL(tegra264_xusb_padctl_soc);
> #endif
>
> MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>");
[ ... ]
> diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h
> index 77609e54de66a..d8d799d9e7522 100644
> --- a/drivers/phy/tegra/xusb.h
> +++ b/drivers/phy/tegra/xusb.h
> @@ -514,5 +514,8 @@ extern const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc;
> #if defined(CONFIG_ARCH_TEGRA_234_SOC)
> extern const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc;
> #endif
> +#if defined(CONFIG_ARCH_TEGRA_264_SOC)
> +extern const struct tegra_xusb_padctl_soc tegra264_xusb_padctl_soc;
> +#endif
[Severity: Low]
Does this create a missing prototype warning (-Wmissing-prototypes) when
building with CONFIG_ARCH_TEGRA_194_SOC=y but CONFIG_ARCH_TEGRA_264_SOC=n?
In xusb-tegra186.c, tegra264_xusb_padctl_soc is defined unconditionally if
any of the 194, 234, or 264 configs are enabled. However, the extern
declaration here in xusb.h is only visible if CONFIG_ARCH_TEGRA_264_SOC is set.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260629093406.1118594-1-waynec@nvidia.com?part=6
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* Re: [PATCH 3/8] arm64: tegra: Enable XUSB host function on Jetson AGX Thor
From: sashiko-bot @ 2026-06-29 9:44 UTC (permalink / raw)
To: Wayne Chang
Cc: vkoul, neil.armstrong, olteanv, linux-phy, conor+dt, robh,
devicetree
In-Reply-To: <20260629093406.1118594-4-waynec@nvidia.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The device tree nodes use `GIC_SPI 4096` and `GIC_SPI 4101` which incorrectly parse as hardware IRQs 4128 and 4133 due to the SPI offset of 32.
--
commit 0e16479e341627ad9fb569ac2ccd54f1ef421b1f
Author: Wayne Chang <waynec@nvidia.com>
arm64: tegra: Enable XUSB host function on Jetson AGX Thor
This commit enables XUSB host and pad controller on Jetson AGX Thor.
> diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> index 2d8e7e37830ff..3433587dc5725 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> @@ -4049,6 +4049,160 @@ pci@8480000 {
> nvidia,bpmp = <&bpmp 5>;
> status = "disabled";
> };
> +
> + xusb_padctl: padctl@8680000 {
> + compatible = "nvidia,tegra264-xusb-padctl";
> + reg = <0x00 0x8680000 0x00 0x20000>,
> + <0x00 0x86a0000 0x00 0x10000>;
> + reg-names = "padctl", "ao";
> + interrupts = <GIC_SPI 4101 IRQ_TYPE_LEVEL_HIGH>;
[Severity: High]
Does this map to the correct hardware IRQ? Using the GIC_SPI macro for an
ESPI INTID adds an offset of 32, mapping to hwirq 4133 instead of 4101.
The kernel will emit boot warnings about the SPI being out of range.
Should this be replaced with <GIC_ESPI 5 IRQ_TYPE_LEVEL_HIGH>?
[ ... ]
> + usb@aa10000 {
> + compatible = "nvidia,tegra264-xusb";
> + reg = <0x00 0xaa10000 0x00 0x40000>,
> + <0x00 0xaa00000 0x00 0x10000>,
> + <0x00 0xaa50000 0x00 0x10000>;
> + reg-names = "hcd", "fpci", "bar2";
> +
> + interrupts-extended = <&gic GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
> + <&gic GIC_SPI 4096 IRQ_TYPE_LEVEL_HIGH>,
[Severity: High]
Similar to the regression above, does this sequence map correctly? Using the
GIC_SPI macro adds an offset of 32, which maps to hwirq 4128 instead of 4096.
Should this be replaced with <GIC_ESPI 0 IRQ_TYPE_LEVEL_HIGH>?
[ ... ]
--
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* [PATCH 8/8] usb: host: xhci-tegra: Add Tegra264 XHCI support
From: Wayne Chang @ 2026-06-29 9:34 UTC (permalink / raw)
To: mathias.nyman, vkoul, neil.armstrong, robh, krzk+dt, conor+dt,
gregkh, thierry.reding, jonathanh
Cc: waynec, linux-usb, linux-tegra, linux-kernel, linux-phy,
devicetree
In-Reply-To: <20260629093406.1118594-1-waynec@nvidia.com>
This change adds Tegra264 XUSB host mode controller support.
The host controller is very similar to the existing Tegra234 XHCI,
except the number of max_num_wakes.
Signed-off-by: Wayne Chang <waynec@nvidia.com>
---
drivers/usb/host/xhci-tegra.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c
index 7d56f35ec9e7..9a55d5818efb 100644
--- a/drivers/usb/host/xhci-tegra.c
+++ b/drivers/usb/host/xhci-tegra.c
@@ -2752,12 +2752,40 @@ static const struct tegra_xusb_soc tegra234_soc = {
.enable_firmware_messages = true,
};
+static const struct tegra_xusb_soc tegra264_soc = {
+ .supply_names = tegra194_supply_names,
+ .num_supplies = ARRAY_SIZE(tegra194_supply_names),
+ .phy_types = tegra194_phy_types,
+ .num_types = ARRAY_SIZE(tegra194_phy_types),
+ .max_num_wakes = 8,
+ .context = &tegra186_xusb_context,
+ .ports = {
+ .usb3 = { .offset = 0, .count = 4, },
+ .usb2 = { .offset = 4, .count = 4, },
+ },
+ .scale_ss_clock = false,
+ .has_ipfs = false,
+ .otg_reset_sspi = false,
+ .ops = &tegra234_ops,
+ .mbox = {
+ .cmd = XUSB_BAR2_ARU_MBOX_CMD,
+ .data_in = XUSB_BAR2_ARU_MBOX_DATA_IN,
+ .data_out = XUSB_BAR2_ARU_MBOX_DATA_OUT,
+ .owner = XUSB_BAR2_ARU_MBOX_OWNER,
+ .smi_intr = XUSB_BAR2_ARU_SMI_INTR,
+ },
+ .lpm_support = true,
+ .has_bar2 = true,
+ .enable_firmware_messages = false,
+};
+
static const struct of_device_id tegra_xusb_of_match[] = {
{ .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
{ .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
{ .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc },
{ .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc },
{ .compatible = "nvidia,tegra234-xusb", .data = &tegra234_soc },
+ { .compatible = "nvidia,tegra264-xusb", .data = &tegra264_soc },
{ },
};
MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
--
2.25.1
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* [PATCH 6/8] phy: tegra: xusb: Add Tegra264 support
From: Wayne Chang @ 2026-06-29 9:34 UTC (permalink / raw)
To: mathias.nyman, vkoul, neil.armstrong, robh, krzk+dt, conor+dt,
gregkh, thierry.reding, jonathanh
Cc: waynec, linux-usb, linux-tegra, linux-kernel, linux-phy,
devicetree
In-Reply-To: <20260629093406.1118594-1-waynec@nvidia.com>
Add support for the XUSB pad controller for Tegra264. Most of
the Tegra264 XUSB PADCTL registers definition and programming sequence
are the same as Tegra234, Tegra264 XUSB PADCTL can share the same
driver with Tegra186, Tegra194, and Tegra234 XUSB PADCTL.
Signed-off-by: Wayne Chang <waynec@nvidia.com>
---
drivers/phy/tegra/Makefile | 1 +
drivers/phy/tegra/xusb-tegra186.c | 26 +++++++++++++++++++++++++-
drivers/phy/tegra/xusb.c | 6 ++++++
drivers/phy/tegra/xusb.h | 3 +++
4 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/tegra/Makefile b/drivers/phy/tegra/Makefile
index eeeea72de117..33a695d4ed59 100644
--- a/drivers/phy/tegra/Makefile
+++ b/drivers/phy/tegra/Makefile
@@ -8,4 +8,5 @@ phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o
phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o
phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_194_SOC) += xusb-tegra186.o
phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_234_SOC) += xusb-tegra186.o
+phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_264_SOC) += xusb-tegra186.o
obj-$(CONFIG_PHY_TEGRA194_P2U) += phy-tegra194-p2u.o
diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c
index 9c1bcd4a72ac..3eb60ed09b68 100644
--- a/drivers/phy/tegra/xusb-tegra186.c
+++ b/drivers/phy/tegra/xusb-tegra186.c
@@ -1668,7 +1668,8 @@ EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc);
#endif
#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
- IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
+ IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) || \
+ IS_ENABLED(CONFIG_ARCH_TEGRA_264_SOC)
static const char * const tegra194_xusb_padctl_supply_names[] = {
"avdd-usb",
"vclamp-usb",
@@ -1753,6 +1754,29 @@ const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc = {
.has_per_pad_term = true,
};
EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc);
+
+const struct tegra_xusb_padctl_soc tegra264_xusb_padctl_soc = {
+ .num_pads = ARRAY_SIZE(tegra194_pads),
+ .pads = tegra194_pads,
+ .ports = {
+ .usb2 = {
+ .ops = &tegra186_usb2_port_ops,
+ .count = 4,
+ },
+ .usb3 = {
+ .ops = &tegra186_usb3_port_ops,
+ .count = 4,
+ },
+ },
+ .ops = &tegra186_xusb_padctl_ops,
+ .supply_names = tegra194_xusb_padctl_supply_names,
+ .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
+ .supports_gen2 = true,
+ .poll_trk_completed = true,
+ .trk_hw_mode = true,
+ .supports_lp_cfg_en = true,
+};
+EXPORT_SYMBOL_GPL(tegra264_xusb_padctl_soc);
#endif
MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>");
diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c
index 9d74c0ecc31b..d0d0b252a205 100644
--- a/drivers/phy/tegra/xusb.c
+++ b/drivers/phy/tegra/xusb.c
@@ -77,6 +77,12 @@ static const struct of_device_id tegra_xusb_padctl_of_match[] = {
.compatible = "nvidia,tegra234-xusb-padctl",
.data = &tegra234_xusb_padctl_soc,
},
+#endif
+#if defined(CONFIG_ARCH_TEGRA_264_SOC)
+ {
+ .compatible = "nvidia,tegra264-xusb-padctl",
+ .data = &tegra264_xusb_padctl_soc,
+ },
#endif
{ }
};
diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h
index 77609e54de66..d8d799d9e752 100644
--- a/drivers/phy/tegra/xusb.h
+++ b/drivers/phy/tegra/xusb.h
@@ -514,5 +514,8 @@ extern const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc;
#if defined(CONFIG_ARCH_TEGRA_234_SOC)
extern const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc;
#endif
+#if defined(CONFIG_ARCH_TEGRA_264_SOC)
+extern const struct tegra_xusb_padctl_soc tegra264_xusb_padctl_soc;
+#endif
#endif /* __PHY_TEGRA_XUSB_H */
--
2.25.1
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* [PATCH 7/8] usb: host: xhci-tegra: Skip MBOX MSG_ENABLED on Tegra264
From: Wayne Chang @ 2026-06-29 9:34 UTC (permalink / raw)
To: mathias.nyman, vkoul, neil.armstrong, robh, krzk+dt, conor+dt,
gregkh, thierry.reding, jonathanh
Cc: waynec, linux-usb, linux-tegra, linux-kernel, linux-phy,
devicetree
In-Reply-To: <20260629093406.1118594-1-waynec@nvidia.com>
Tegra264 XUSB does not use the firmware mailbox handshake to enable
controller messages (MBOX_CMD_MSG_ENABLED). Add a per-SoC flag and
short-circuit __tegra_xusb_enable_firmware_messages() so both probe
and resume avoid sending the command.
Signed-off-by: Wayne Chang <waynec@nvidia.com>
---
drivers/usb/host/xhci-tegra.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c
index e7e6d569f1db..7d56f35ec9e7 100644
--- a/drivers/usb/host/xhci-tegra.c
+++ b/drivers/usb/host/xhci-tegra.c
@@ -250,6 +250,7 @@ struct tegra_xusb_soc {
bool otg_set_port_power;
bool has_bar2;
+ bool enable_firmware_messages;
};
struct tegra_xusb_context {
@@ -1260,6 +1261,9 @@ static int __tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
struct tegra_xusb_mbox_msg msg;
int err;
+ if (!tegra->soc->enable_firmware_messages)
+ return 0;
+
/* Enable firmware messages from controller. */
msg.cmd = MBOX_CMD_MSG_ENABLED;
msg.data = 0;
@@ -2580,6 +2584,7 @@ static const struct tegra_xusb_soc tegra124_soc = {
.owner = 0xf0,
.smi_intr = XUSB_CFG_ARU_SMI_INTR,
},
+ .enable_firmware_messages = true,
};
#if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) || IS_ENABLED(CONFIG_ARCH_TEGRA_132_SOC)
MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
@@ -2621,6 +2626,7 @@ static const struct tegra_xusb_soc tegra210_soc = {
.owner = 0xf0,
.smi_intr = XUSB_CFG_ARU_SMI_INTR,
},
+ .enable_firmware_messages = true,
};
#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
@@ -2670,6 +2676,7 @@ static const struct tegra_xusb_soc tegra186_soc = {
.smi_intr = XUSB_CFG_ARU_SMI_INTR,
},
.lpm_support = true,
+ .enable_firmware_messages = true,
};
static const char * const tegra194_supply_names[] = {
@@ -2704,6 +2711,7 @@ static const struct tegra_xusb_soc tegra194_soc = {
.smi_intr = XUSB_CFG_ARU_SMI_INTR,
},
.lpm_support = true,
+ .enable_firmware_messages = true,
};
#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
MODULE_FIRMWARE("nvidia/tegra194/xusb.bin");
@@ -2741,6 +2749,7 @@ static const struct tegra_xusb_soc tegra234_soc = {
},
.lpm_support = true,
.has_bar2 = true,
+ .enable_firmware_messages = true,
};
static const struct of_device_id tegra_xusb_of_match[] = {
--
2.25.1
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* [PATCH 5/8] phy: tegra: xusb: Increase timeout for USB2_TRK_COMPLETED polling
From: Wayne Chang @ 2026-06-29 9:34 UTC (permalink / raw)
To: mathias.nyman, vkoul, neil.armstrong, robh, krzk+dt, conor+dt,
gregkh, thierry.reding, jonathanh
Cc: waynec, linux-usb, linux-tegra, linux-kernel, linux-phy,
devicetree
In-Reply-To: <20260629093406.1118594-1-waynec@nvidia.com>
On Tegra264, the UTMI bias tracking circuit runs at 1 MHz and needs
more cycles for the biases to settle than on earlier SoCs such as
Tegra234. The existing timeout is therefore not long enough and can
cause spurious polling failures during bias pad power-on. Therefore,
increase the timeout to 200 cycles to support Tegra264 devices
Signed-off-by: Wayne Chang <waynec@nvidia.com>
---
drivers/phy/tegra/xusb-tegra186.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c
index 800be0cbb3f9..9c1bcd4a72ac 100644
--- a/drivers/phy/tegra/xusb-tegra186.c
+++ b/drivers/phy/tegra/xusb-tegra186.c
@@ -636,7 +636,7 @@ static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl)
if (padctl->soc->poll_trk_completed) {
err = padctl_readl_poll(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1,
- USB2_TRK_COMPLETED, USB2_TRK_COMPLETED, 100);
+ USB2_TRK_COMPLETED, USB2_TRK_COMPLETED, 200);
if (err) {
/* The failure with polling on trk complete will not
* cause the failure of powering on the bias pad.
--
2.25.1
--
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* [PATCH 3/8] arm64: tegra: Enable XUSB host function on Jetson AGX Thor
From: Wayne Chang @ 2026-06-29 9:34 UTC (permalink / raw)
To: mathias.nyman, vkoul, neil.armstrong, robh, krzk+dt, conor+dt,
gregkh, thierry.reding, jonathanh
Cc: waynec, linux-usb, linux-tegra, linux-kernel, linux-phy,
devicetree
In-Reply-To: <20260629093406.1118594-1-waynec@nvidia.com>
This commit enables XUSB host and pad controller on Jetson AGX Thor.
Signed-off-by: Wayne Chang <waynec@nvidia.com>
---
.../arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 50 ++++++
.../dts/nvidia/tegra264-p4071-0000+p3834.dtsi | 95 +++++++++++
arch/arm64/boot/dts/nvidia/tegra264.dtsi | 154 ++++++++++++++++++
3 files changed, 299 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
index 7e2c3e66c2ab..61802334452e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
@@ -35,4 +35,54 @@ cmdqv@6200000 {
status = "okay";
};
};
+
+ bus@a800000000 {
+ padctl@8680000 {
+ vclamp-usb-supply = <&vdd_ao_1v8>;
+ avdd-usb-supply = <&vdd_ao_3v3>;
+
+ ports {
+ usb2-0 {
+ vbus-supply = <&vdd_5v0_sys>;
+ };
+
+ usb2-1 {
+ vbus-supply = <&vdd_5v0_sys>;
+ };
+
+ usb2-2 {
+ vbus-supply = <&vdd_5v0_sys>;
+ };
+
+ usb2-3 {
+ vbus-supply = <&vdd_5v0_sys>;
+ };
+ };
+ };
+ };
+
+ vdd_5v0_sys: regulator-vdd-5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "VIN_SYS_5V0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_ao_1v8: regulator-vdd-1v8-ao {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-AO-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vdd_ao_3v3: regulator-vdd-3v3-ao {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-AO-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi
index 45f8df9bbfd6..9d6d0c31f881 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi
@@ -9,4 +9,99 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ bus@a800000000 {
+ padctl@8680000 {
+ status = "okay";
+
+ pads {
+ usb2 {
+ lanes {
+ usb2-0 {
+ status = "okay";
+ };
+
+ usb2-1 {
+ status = "okay";
+ };
+
+ usb2-2 {
+ status = "okay";
+ };
+
+ usb2-3 {
+ status = "okay";
+ };
+ };
+ };
+
+ usb3 {
+ lanes {
+ usb3-0 {
+ status = "okay";
+ };
+
+ usb3-1 {
+ status = "okay";
+ };
+
+ usb3-2 {
+ status = "okay";
+ };
+ };
+ };
+ };
+
+ ports {
+ usb2-0 {
+ mode = "host";
+ status = "okay";
+ };
+
+ usb2-1 {
+ mode = "host";
+ status = "okay";
+ };
+
+ usb2-2 {
+ mode = "host";
+ status = "okay";
+ };
+
+ usb2-3 {
+ mode = "host";
+ status = "okay";
+ };
+
+ usb3-0 {
+ nvidia,usb2-companion = <1>;
+ status = "okay";
+ };
+
+ usb3-1 {
+ nvidia,usb2-companion = <0>;
+ status = "okay";
+ };
+
+ usb3-2 {
+ nvidia,usb2-companion = <3>;
+ status = "okay";
+ };
+ };
+ };
+
+ usb@aa10000 {
+ status = "okay";
+
+ phys = <&{/bus@a800000000/padctl@8680000/pads/usb2/lanes/usb2-0}>,
+ <&{/bus@a800000000/padctl@8680000/pads/usb2/lanes/usb2-1}>,
+ <&{/bus@a800000000/padctl@8680000/pads/usb2/lanes/usb2-2}>,
+ <&{/bus@a800000000/padctl@8680000/pads/usb2/lanes/usb2-3}>,
+ <&{/bus@a800000000/padctl@8680000/pads/usb3/lanes/usb3-0}>,
+ <&{/bus@a800000000/padctl@8680000/pads/usb3/lanes/usb3-1}>,
+ <&{/bus@a800000000/padctl@8680000/pads/usb3/lanes/usb3-2}>;
+ phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3",
+ "usb3-0", "usb3-1", "usb3-2";
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index 2d8e7e37830f..3433587dc572 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -4049,6 +4049,160 @@ pci@8480000 {
nvidia,bpmp = <&bpmp 5>;
status = "disabled";
};
+
+ xusb_padctl: padctl@8680000 {
+ compatible = "nvidia,tegra264-xusb-padctl";
+ reg = <0x00 0x8680000 0x00 0x20000>,
+ <0x00 0x86a0000 0x00 0x10000>;
+ reg-names = "padctl", "ao";
+ interrupts = <GIC_SPI 4101 IRQ_TYPE_LEVEL_HIGH>;
+
+ resets = <&bpmp TEGRA264_RESET_XUSB1_PADCTL>;
+ reset-names = "padctl";
+
+ status = "disabled";
+
+ pads {
+ usb2 {
+ lanes {
+ usb2-0 {
+ nvidia,function = "xusb";
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
+ usb2-1 {
+ nvidia,function = "xusb";
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
+ usb2-2 {
+ nvidia,function = "xusb";
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
+ usb2-3 {
+ nvidia,function = "xusb";
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+ };
+ };
+
+ usb3 {
+ lanes {
+ usb3-0 {
+ nvidia,function = "xusb";
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
+ usb3-1 {
+ nvidia,function = "xusb";
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
+ usb3-2 {
+ nvidia,function = "xusb";
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
+ usb3-3 {
+ nvidia,function = "xusb";
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+ };
+ };
+ };
+
+ ports {
+ usb2-0 {
+ status = "disabled";
+ };
+
+ usb2-1 {
+ status = "disabled";
+ };
+
+ usb2-2 {
+ status = "disabled";
+ };
+
+ usb2-3 {
+ status = "disabled";
+ };
+
+ usb3-0 {
+ status = "disabled";
+ };
+
+ usb3-1 {
+ status = "disabled";
+ };
+
+ usb3-2 {
+ status = "disabled";
+ };
+
+ usb3-3 {
+ status = "disabled";
+ };
+ };
+ };
+
+ usb@aa10000 {
+ compatible = "nvidia,tegra264-xusb";
+ reg = <0x00 0xaa10000 0x00 0x40000>,
+ <0x00 0xaa00000 0x00 0x10000>,
+ <0x00 0xaa50000 0x00 0x10000>;
+ reg-names = "hcd", "fpci", "bar2";
+
+ interrupts-extended = <&gic GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 4096 IRQ_TYPE_LEVEL_HIGH>,
+ <&pmc 79 IRQ_TYPE_LEVEL_HIGH>,
+ <&pmc 80 IRQ_TYPE_LEVEL_HIGH>,
+ <&pmc 81 IRQ_TYPE_LEVEL_HIGH>,
+ <&pmc 82 IRQ_TYPE_LEVEL_HIGH>,
+ <&pmc 83 IRQ_TYPE_LEVEL_HIGH>,
+ <&pmc 84 IRQ_TYPE_LEVEL_HIGH>,
+ <&pmc 85 IRQ_TYPE_LEVEL_HIGH>,
+ <&pmc 86 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&bpmp TEGRA264_CLK_XUSB1_CORE_HOST>,
+ <&bpmp TEGRA264_CLK_XUSB1_FALCON>,
+ <&bpmp TEGRA264_CLK_XUSB1_CORE_SUPERSPEED>,
+ <&bpmp TEGRA264_CLK_XUSB1_SS>,
+ <&bpmp TEGRA264_CLK_OSC>,
+ <&bpmp TEGRA264_CLK_XUSB1_FS>,
+ <&bpmp TEGRA264_CLK_UTMI_PLL1>,
+ <&bpmp TEGRA264_CLK_OSC>,
+ <&bpmp TEGRA264_CLK_PLLE0>;
+ clock-names = "xusb_host", "xusb_falcon_src",
+ "xusb_ss", "xusb_ss_src", "xusb_hs_src",
+ "xusb_fs_src", "pll_u_480m", "clk_m",
+ "pll_e";
+ interconnects = <&mc TEGRA264_MEMORY_CLIENT_XUSB_DEVR &emc>,
+ <&mc TEGRA264_MEMORY_CLIENT_XUSB_DEVW &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu1 TEGRA264_SID_XUSB_DEV>,
+ <&smmu1 TEGRA264_SID_XUSB_DEV1>,
+ <&smmu1 TEGRA264_SID_XUSB_DEV2>,
+ <&smmu1 TEGRA264_SID_XUSB_DEV3>,
+ <&smmu1 TEGRA264_SID_XUSB_DEV4>;
+
+ power-domains = <&bpmp TEGRA264_POWER_DOMAIN_XUSB_HOST>,
+ <&bpmp TEGRA264_POWER_DOMAIN_XUSB_SS>;
+ power-domain-names = "xusb_host", "xusb_ss";
+
+ nvidia,xusb-padctl = <&xusb_padctl>;
+ dma-coherent;
+ status = "disabled";
+ };
};
cpus {
--
2.25.1
--
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* [PATCH 4/8] phy: tegra: xusb: Use devm_clk_get_optional to fetch USB2 tracking clock
From: Wayne Chang @ 2026-06-29 9:34 UTC (permalink / raw)
To: mathias.nyman, vkoul, neil.armstrong, robh, krzk+dt, conor+dt,
gregkh, thierry.reding, jonathanh
Cc: waynec, linux-usb, linux-tegra, linux-kernel, linux-phy,
devicetree, Sing-Han Chen
In-Reply-To: <20260629093406.1118594-1-waynec@nvidia.com>
From: Sing-Han Chen <singhanc@nvidia.com>
The USB2 PAD tracking clock is an optional clock so use
devm_clk_get_optional() so a missing clock in devicetree is
represented as NULL and probe can continue. clk_prepare_enable()
and clk_disable_unprepare() already treat a NULL clock as a no-op.
Signed-off-by: Sing-Han Chen <singhanc@nvidia.com>
Signed-off-by: Wayne Chang <waynec@nvidia.com>
---
drivers/phy/tegra/xusb-tegra186.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c
index 60156aea2707..800be0cbb3f9 100644
--- a/drivers/phy/tegra/xusb-tegra186.c
+++ b/drivers/phy/tegra/xusb-tegra186.c
@@ -1045,7 +1045,7 @@ tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
goto out;
}
- priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk");
+ priv->usb2_trk_clk = devm_clk_get_optional(&pad->dev, "trk");
if (IS_ERR(priv->usb2_trk_clk)) {
err = PTR_ERR(priv->usb2_trk_clk);
dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err);
--
2.25.1
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* [PATCH 2/8] dt-bindings: usb: Add Tegra264 XUSB host support
From: Wayne Chang @ 2026-06-29 9:34 UTC (permalink / raw)
To: mathias.nyman, vkoul, neil.armstrong, robh, krzk+dt, conor+dt,
gregkh, thierry.reding, jonathanh
Cc: waynec, linux-usb, linux-tegra, linux-kernel, linux-phy,
devicetree
In-Reply-To: <20260629093406.1118594-1-waynec@nvidia.com>
Extend the Tegra234 XUSB host binding to cover Tegra264:
- Add nvidia,tegra264-xusb compatible string
- Document optional USB wake interrupts for Tegra264
- Document Tegra264 PMC wake event to port mapping
- Allow up to five IOMMU specifiers for the additional XUSB host
stream IDs
Signed-off-by: Wayne Chang <waynec@nvidia.com>
---
.../bindings/usb/nvidia,tegra234-xusb.yaml | 115 ++++++++++++------
1 file changed, 80 insertions(+), 35 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml
index ec0993497fbb..94b1dbe2b02f 100644
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml
@@ -17,7 +17,9 @@ description: |
properties:
compatible:
- const: nvidia,tegra234-xusb
+ enum:
+ - nvidia,tegra234-xusb
+ - nvidia,tegra264-xusb
reg:
items:
@@ -31,37 +33,6 @@ properties:
- const: fpci
- const: bar2
- interrupts:
- minItems: 2
- items:
- - description: xHCI host interrupt
- - description: mailbox interrupt
- - description: USB wake event 0
- - description: USB wake event 1
- - description: USB wake event 2
- - description: USB wake event 3
- - description: USB wake event 4
- - description: USB wake event 5
- - description: USB wake event 6
- description: |
- The first two interrupts are required for the USB host controller. The
- remaining USB wake event interrupts are optional. Each USB wake event is
- independent; it is not necessary to use all of these events on a
- platform. The USB host controller can function even if no wake-up events
- are defined. The USB wake event interrupts are handled by the Tegra PMC;
- hence, the interrupt controller for these is the PMC and the interrupt
- IDs correspond to the PMC wake event IDs. A complete list of wake event
- IDs is provided below, and this information is also present in the Tegra
- TRM document.
-
- PMC wake-up 76 for USB3 port 0 wakeup
- PMC wake-up 77 for USB3 port 1 wakeup
- PMC wake-up 78 for USB3 port 2 and port 3 wakeup
- PMC wake-up 79 for USB2 port 0 wakeup
- PMC wake-up 80 for USB2 port 1 wakeup
- PMC wake-up 81 for USB2 port 2 wakeup
- PMC wake-up 82 for USB2 port 3 wakeup
-
clocks:
items:
- description: XUSB host clock
@@ -96,9 +67,6 @@ properties:
- const: dma-mem # read
- const: write
- iommus:
- maxItems: 1
-
nvidia,xusb-padctl:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the XUSB pad controller that is used to configure
@@ -137,6 +105,83 @@ properties:
allOf:
- $ref: usb-xhci.yaml
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra234-xusb
+ then:
+ properties:
+ interrupts:
+ minItems: 2
+ description: |
+ The first two interrupts are required for the USB host controller.
+ The remaining USB wake event interrupts are optional. Each USB wake
+ event is independent; it is not necessary to use all of these events
+ on a platform. The USB host controller can function even if no
+ wake-up events are defined. The USB wake event interrupts are
+ handled by the Tegra PMC; hence, the interrupt controller for these
+ is the PMC and the interrupt IDs correspond to the PMC wake event
+ IDs.
+
+ PMC wake-up 76 for USB3 port 0 wakeup
+ PMC wake-up 77 for USB3 port 1 wakeup
+ PMC wake-up 78 for USB3 port 2 and port 3 wakeup
+ PMC wake-up 79 for USB2 port 0 wakeup
+ PMC wake-up 80 for USB2 port 1 wakeup
+ PMC wake-up 81 for USB2 port 2 wakeup
+ PMC wake-up 82 for USB2 port 3 wakeup
+ items:
+ - description: xHCI host interrupt
+ - description: mailbox interrupt
+ - description: USB wake event 0
+ - description: USB wake event 1
+ - description: USB wake event 2
+ - description: USB wake event 3
+ - description: USB wake event 4
+ - description: USB wake event 5
+ - description: USB wake event 6
+ iommus:
+ maxItems: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra264-xusb
+ then:
+ properties:
+ interrupts:
+ minItems: 2
+ description: |
+ Same as Tegra234, with one additional optional USB wake event
+ interrupt. USB3 port 2 and port 3 each have a dedicated wake event
+ interrupt on Tegra264.
+
+ PMC wake-up 79 for USB3 port 0 wakeup
+ PMC wake-up 80 for USB3 port 1 wakeup
+ PMC wake-up 81 for USB3 port 2 wakeup
+ PMC wake-up 82 for USB3 port 3 wakeup
+ PMC wake-up 83 for USB2 port 0 wakeup
+ PMC wake-up 84 for USB2 port 1 wakeup
+ PMC wake-up 85 for USB2 port 2 wakeup
+ PMC wake-up 86 for USB2 port 3 wakeup
+ items:
+ - description: xHCI host interrupt
+ - description: mailbox interrupt
+ - description: USB wake event 0
+ - description: USB wake event 1
+ - description: USB wake event 2
+ - description: USB wake event 3
+ - description: USB wake event 4
+ - description: USB wake event 5
+ - description: USB wake event 6
+ - description: USB wake event 7
+ iommus:
+ maxItems: 5
+
unevaluatedProperties: false
examples:
--
2.25.1
--
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* [PATCH 1/8] dt-bindings: phy: tegra-xusb: Add support for Tegra264
From: Wayne Chang @ 2026-06-29 9:33 UTC (permalink / raw)
To: mathias.nyman, vkoul, neil.armstrong, robh, krzk+dt, conor+dt,
gregkh, thierry.reding, jonathanh
Cc: waynec, linux-usb, linux-tegra, linux-kernel, linux-phy,
devicetree
In-Reply-To: <20260629093406.1118594-1-waynec@nvidia.com>
Add the compatible string for the Tegra264 XUSB PHY.
Signed-off-by: Wayne Chang <waynec@nvidia.com>
---
.../devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml
index d8de900a4fce..f6fe3c90b5b0 100644
--- a/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml
+++ b/Documentation/devicetree/bindings/phy/nvidia,tegra194-xusb-padctl.yaml
@@ -45,6 +45,7 @@ properties:
enum:
- nvidia,tegra194-xusb-padctl
- nvidia,tegra234-xusb-padctl
+ - nvidia,tegra264-xusb-padctl
reg:
items:
--
2.25.1
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* [PATCH 0/8] Enable USB host functions on Jetson AGX Thor
From: Wayne Chang @ 2026-06-29 9:33 UTC (permalink / raw)
To: mathias.nyman, vkoul, neil.armstrong, robh, krzk+dt, conor+dt,
gregkh, thierry.reding, jonathanh
Cc: waynec, linux-usb, linux-tegra, linux-kernel, linux-phy,
devicetree
Enable support for USB host functions on the Tegra264 Jetson AGX Thor
platform
Sing-Han Chen (1):
phy: tegra: xusb: Use devm_clk_get_optional to fetch USB2 tracking
clock
Wayne Chang (7):
dt-bindings: phy: tegra-xusb: Add support for Tegra264
dt-bindings: usb: Add Tegra264 XUSB host support
arm64: tegra: Enable XUSB host function on Jetson AGX Thor
phy: tegra: xusb: Increase timeout for USB2_TRK_COMPLETED polling
phy: tegra: xusb: Add Tegra264 support
usb: host: xhci-tegra: Skip MBOX MSG_ENABLED on Tegra264
usb: host: xhci-tegra: Add Tegra264 XHCI support
.../phy/nvidia,tegra194-xusb-padctl.yaml | 1 +
.../bindings/usb/nvidia,tegra234-xusb.yaml | 115 +++++++++----
.../arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 50 ++++++
.../dts/nvidia/tegra264-p4071-0000+p3834.dtsi | 95 +++++++++++
arch/arm64/boot/dts/nvidia/tegra264.dtsi | 154 ++++++++++++++++++
drivers/phy/tegra/Makefile | 1 +
drivers/phy/tegra/xusb-tegra186.c | 30 +++-
drivers/phy/tegra/xusb.c | 6 +
drivers/phy/tegra/xusb.h | 3 +
drivers/usb/host/xhci-tegra.c | 37 +++++
10 files changed, 454 insertions(+), 38 deletions(-)
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
--
2.25.1
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* Re: [PATCH RFC v4 5/9] phy: qcom: qmp-pcie: Refactor pipe clk register and parse_dt helpers
From: Konrad Dybcio @ 2026-06-29 9:21 UTC (permalink / raw)
To: Qiang Yu
Cc: Dmitry Baryshkov, Manivannan Sadhasivam, Vinod Koul,
Neil Armstrong, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Philipp Zabel, Bjorn Andersson, Konrad Dybcio, linux-arm-msm,
linux-phy, devicetree, linux-kernel
In-Reply-To: <akII/X8OWO5XN9Gw@hu-qianyu-lv.qualcomm.com>
On 6/29/26 7:56 AM, Qiang Yu wrote:
> On Tue, Jun 16, 2026 at 04:05:43PM +0200, Konrad Dybcio wrote:
>> On 5/29/26 9:02 AM, Qiang Yu wrote:
>>> On Thu, May 28, 2026 at 04:48:24PM +0300, Dmitry Baryshkov wrote:
>>>> On Fri, May 22, 2026 at 04:27:35PM +0530, Manivannan Sadhasivam wrote:
>>>>> On Wed, May 20, 2026 at 07:25:01PM +0300, Dmitry Baryshkov wrote:
>>>>>> On Mon, May 18, 2026 at 10:47:16PM -0700, Qiang Yu wrote:
>>>>>>> Some QMP PCIe PHY hardware blocks can be split into multiple sub-PHYs
>>>>>>> under a single DT node, each requiring its own pipe clock registration and
>>>>>>> DT resource mapping. The current helpers are tightly coupled to a single
>>>>>>> qmp_pcie instance, which prevents reuse across sub-PHY instances.
>>>>>>>
>>>>>>> Refactor __phy_pipe_clk_register() as a generic helper and reduce
>>>>>>> phy_pipe_clk_register() to a thin wrapper around it. Similarly, extract
>>>>>>> qmp_pcie_parse_dt_common() from qmp_pcie_parse_dt() to hold the register-
>>>>>>> mapping and pipe-clock setup that will be shared between sub-PHY instances,
>>>>>>> with pipe clock names parameterised per instance.
>>>>>>>
>>>>>>> This is a preparatory step before adding multi-PHY support. No functional
>>>>>>> change for existing platforms.
>>>>>>>
>>>>>>> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
>>>>>>> ---
>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 76 ++++++++++++++++++--------------
>>>>>>> 1 file changed, 44 insertions(+), 32 deletions(-)
>>>>>>
>>>>>> I'd suggest splitting the Glymur PHY to a separate driver. Otherwise we
>>>>>> end up having too many single-platform, single-device specifics which
>>>>>> don't apply to other platforms.
>>>>>>
>>>>>
>>>>> I don't think that's really needed. This shared PHY concept is going to be
>>>>> applicable to upcoming SoCs as well. And moreover, the split won't be clean
>>>>> either. We still need to reuse a lot of common logic in the 'phy-qcom-qmp-pcie'
>>>>> driver and may only end up keeping very minimal code in
>>>>> 'phy-qcom-qmp-pcie-glymur'.
>>>>
>>>> Then splitting makes even more sense. Let's not clutter the existing
>>>> driver with too many conditions and options.
>>>>
>>>>>
>>>>> If you are concerned about the file size of 'phy-qcom-qmp-pcie', then we should
>>>>> move the SoC specific 'cfg' structs into a separate file as that's what
>>>>> occupying majority of the space.
>>>>
>>>> No, it's really the 'shared' part.
>>>>
>>>
>>> To confirm, are you okay with some code duplication between the new
>>> Glymur-specific driver and phy-qcom-qmp-pcie driver.
>>
>> That's a necessity, to some degree. See e.g. qmp-combo and qmp-usbc
>>
> I've already prototyped a separate Glymur driver, and it turned out better
> than expected — there's actually not much duplication. The parts that do
> overlap aren't fully identical either; they tend to diverge once the
> Glymur-specific handling is factored in.
>
> Currently, I meet an issue when tesing the patch, and will post it after
> fixing the issue.
Good, thank you!
Konrad
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* Re: [PATCH RFC v4 2/9] dt-bindings: phy: qcom-qmp: Add PHY selector and Glymur link-mode macros
From: Konrad Dybcio @ 2026-06-29 9:21 UTC (permalink / raw)
To: Qiang Yu
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Bjorn Andersson, Konrad Dybcio,
linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <akIAPK7daXxPH5JO@hu-qianyu-lv.qualcomm.com>
On 6/29/26 7:18 AM, Qiang Yu wrote:
> On Tue, Jun 16, 2026 at 04:07:27PM +0200, Konrad Dybcio wrote:
>> On 5/19/26 7:47 AM, Qiang Yu wrote:
>>> Add two sets of constants to phy-qcom-qmp.h to support upcoming multiple
>>> link mode QMP PHY:
>>>
>>> - QMP_PHY_SELECTOR_0 / QMP_PHY_SELECTOR_1: generic logical PHY index
>>> values for QMP providers that expose multiple PHY instances under a
>>> single DT node (i.e. #phy-cells = <1>).
>>>
>>> - QMP_PCIE_GLYMUR_MODE_X8 / QMP_PCIE_GLYMUR_MODE_X4X4: link-mode
>>> values for the Glymur Gen5x8 PCIe PHY "qcom,link-mode" syscon property,
>>> selecting between the x8 single-PHY and x4+x4 dual-PHY topologies.
>>>
>>> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
>>> ---
>>> include/dt-bindings/phy/phy-qcom-qmp.h | 8 ++++++++
>>> 1 file changed, 8 insertions(+)
>>>
>>> diff --git a/include/dt-bindings/phy/phy-qcom-qmp.h b/include/dt-bindings/phy/phy-qcom-qmp.h
>>> index 6b43ea9e0051..befa76f8392f 100644
>>> --- a/include/dt-bindings/phy/phy-qcom-qmp.h
>>> +++ b/include/dt-bindings/phy/phy-qcom-qmp.h
>>> @@ -21,4 +21,12 @@
>>> #define QMP_PCIE_PIPE_CLK 0
>>> #define QMP_PCIE_PHY_AUX_CLK 1
>>>
>>> +/* Generic QMP logical PHY selectors */
>>> +#define QMP_PHY_SELECTOR_0 0
>>> +#define QMP_PHY_SELECTOR_1 1
>>
>> Is this for the second phy cell? FWIW I think it's fine to use raw
>> numbers as they're just indices (i.e. "nth bifurcated phy") anyway
>
> I can't use lane numbers. In x4+x4 case, I need to tell phy the first 4
> lanes or second 4 lanes are required.
I didn't mean lane indices, but instead the same numbers you defined,
without the name. It's a minor difference though, and ultimately both
work for me.
Konrad
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* Re: [PATCH RFC v4 1/9] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add glymur-qmp-gen5x8-pcie-phy compatible
From: Konrad Dybcio @ 2026-06-29 9:20 UTC (permalink / raw)
To: Qiang Yu
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Bjorn Andersson, Konrad Dybcio,
linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <akH/N/ZwnSD5BkIj@hu-qianyu-lv.qualcomm.com>
On 6/29/26 7:14 AM, Qiang Yu wrote:
> On Tue, Jun 16, 2026 at 04:03:39PM +0200, Konrad Dybcio wrote:
>> On 5/19/26 7:47 AM, Qiang Yu wrote:
>>> The Glymur SoC uses a single PCIe Gen5 PHY hardware block for the
>>> PCIe3a/PCIe3b controllers. This block supports two link modes:
>>>
>>> 1. x4+x4: two 4-lane PHY instances are exposed
>>> 2. x8: one 8-lane PHY instance is exposed
>>>
>>> Add qcom,glymur-qmp-gen5x8-pcie-phy as a multi-mode PHY compatible and
>>> document the new link-mode property, which selects the active link mode
>>> via a TCSR syscon register.
>>>
>>> Document the required clocks, resets, and power-domains for both PHY
>>> instances active in x8 mode. Use #phy-cells = <1> for this compatible,
>>> where the cell value is the PHY index within the active link mode.
>>>
>>> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
>>> ---
>>
>> [...]
>>
>>> @@ -68,20 +69,29 @@ properties:
>>> - const: ref
>>> - enum: [rchng, refgen]
>>> - const: pipe
>>> - - const: pipediv2
>>> + - enum: [pipediv2, phy_b_aux]
>>
>> I'm surprised to learn 3A doesnm'doesn't have a PIPE_DIV2 clk.. it does have
>> a non-div2 one though.
>>
>> Seems like it's specifically not the case on Hamoa and Makena, so perhaps
>> it's better for maintainability if the Glymur list was separate
>>
> Do you mean splitting Glymur out into a separate YAML file for the PCIe3
> PHY? I'll add a new file if that's preferred and Krzysztof is on board.
I believe that may be the better approach since Glymur seems to be an
outlier with the clocks I mentioned above. Krzysztof?
Konrad
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* Re: [PATCH RFC v4 9/9] arm64: dts: qcom: glymur: Wire PCIe3a/3b to shared Gen5x8 PHY
From: Konrad Dybcio @ 2026-06-29 9:20 UTC (permalink / raw)
To: Qiang Yu
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Bjorn Andersson, Konrad Dybcio,
linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <akH9LKxqhciznM2x@hu-qianyu-lv.qualcomm.com>
On 6/29/26 7:05 AM, Qiang Yu wrote:
> On Wed, Jun 17, 2026 at 01:19:49PM +0200, Konrad Dybcio wrote:
>> On 5/19/26 7:47 AM, Qiang Yu wrote:
>>> Glymur PCIe3 uses a single shared Gen5x8 QMP PHY block. Model PCIe3a and
>>> PCIe3b as consumers of that shared PHY provider instead of separate PHY
>>> nodes.
>>>
>>> Update the DTS wiring to:
>>> - point GCC PCIe3A/3B pipe parents to the shared PHY clock outputs
>>> - add PCIe3a controller node and route PCIe3a/PCIe3b port phys to
>>> &pcie3_phy using two-cell PHY arguments
>>> - configure the shared PHY node with link-mode and dual pipe outputs
>>>
>>> Use QMP_PCIE_GLYMUR_MODE_* dt-binding macros for mode selection.
>>>
>>> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
>>> ---
>>
>> [...]
>>
>>> + pcie3a: pci@1c10000 {
>>> + device_type = "pci";
>>> + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
>>> + reg = <0x0 0x01c10000 0x0 0x3000>,
>>> + <0x0 0x70000000 0x0 0xf20>,
>>> + <0x0 0x70000f40 0x0 0xa8>,
>>> + <0x0 0x70001000 0x0 0x4000>,
>>> + <0x0 0x70100000 0x0 0x100000>,
>>> + <0x0 0x01c13000 0x0 0x1000>;
>>> + reg-names = "parf",
>>> + "dbi",
>>> + "elbi",
>>> + "atu",
>>> + "config",
>>> + "mhi";
>>> + #address-cells = <3>;
>>> + #size-cells = <2>;
>>> + ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>,
>>> + <0x02000000 0x0 0x70000000 0x0 0x70300000 0x0 0x3d00000>,
>>> + <0x03000000 0x7 0x00000000 0x7 0x00000000 0x0 0x40000000>,
>>> + <0x43000000 0x70 0x00000000 0x70 0x00000000 0x10 0x00000000>;
>>> +
>>> + bus-range = <0 0xff>;
>>> +
>>> + dma-coherent;
>>> +
>>> + linux,pci-domain = <3>;
>>> + num-lanes = <8>;
>>
>> Is it fine to keep num-lanes 8 here even for configurations with
>> bifurcated PHY?
>>
>> I would assume so, given essentially this is a x8 host, whose 4
>> lanes may simply be effectively NC
>>
> Actually, on existing platforms, the PCIe3a and PCIe3b controllers are
> never enabled at the same time. When PCIe3a is exposed, it is always in an
> x8 slot. But if we have a x4+x4 platform in future, we can simply override
> num-lanes to 4 in the board.dts.
My question is whether that will be necessary - if yes, sure, we
can do it, but if not, we can conclude on this early and not have
to fight over it in a couple months
Konrad
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* Re: [PATCH v15 1/9] drm/bridge: Implement generic USB Type-C DP HPD bridge
From: Chaoyi Chen @ 2026-06-29 9:09 UTC (permalink / raw)
To: Xu Yang, Heikki Krogerus
Cc: Chaoyi Chen, Greg Kroah-Hartman, Dmitry Baryshkov, Peter Chen,
Luca Ceresoli, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Vinod Koul, Kishon Vijay Abraham I, Heiko Stuebner, Sandy Huang,
Andy Yan, Yubing Zhang, Frank Wang, Andrzej Hajda, Neil Armstrong,
Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Amit Sunil Dhamne, Dragan Simic, Johan Jonker,
Diederik de Haas, Peter Robinson, Hugh Cole-Baker, linux-usb,
devicetree, linux-kernel, linux-phy, linux-arm-kernel,
linux-rockchip, dri-devel
In-Reply-To: <k53t2soc3nxhwugncatksektig6agxfgdkogkdwbhrhu2fn2g7@auvsfrv76wxy>
Hello Xu Yang, Heikki
On 6/29/2026 4:26 PM, Xu Yang wrote:
> On Mon, Jun 29, 2026 at 09:29:08AM +0800, Chaoyi Chen wrote:
>> Hello Xu Yang,
>>
>> On 6/26/2026 7:15 PM, Xu Yang wrote:
>>> On Wed, Mar 04, 2026 at 05:41:44PM +0800, Chaoyi Chen wrote:
>>>> From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
>>>>
>>>> The HPD function of Type-C DP is implemented through
>>>> drm_connector_oob_hotplug_event(). For embedded DP, it is required
>>>> that the DRM connector fwnode corresponds to the Type-C port fwnode.
>>>>
>>>> To describe the relationship between the DP controller and the Type-C
>>>> port device, we usually using drm_bridge to build a bridge chain.
>>>>
>>>> Now several USB-C controller drivers have already implemented the DP
>>>> HPD bridge function provided by aux-hpd-bridge.c, it will build a DP
>>>> HPD bridge on USB-C connector port device.
>>>>
>>>> But this requires the USB-C controller driver to manually register the
>>>> HPD bridge. If the driver does not implement this feature, the bridge
>>>> will not be create.
>>>>
>>>> So this patch implements a generic DP HPD bridge based on
>>>> aux-hpd-bridge.c. It will monitor Type-C bus events, and when a
>>>> Type-C port device containing the DP svid is registered, it will
>>>> create an HPD bridge for it without the need for the USB-C controller
>>>> driver to implement it.
>>>>
>>>> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
>>>> Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
>>>> ---
>>>>
>>>> (no changes since v14)
>>>>
>>>> Changes in v13:
>>>> - Only register drm dp hpd bridge for typec port altmode device.
>>>>
>>>> (no changes since v12)
>>>>
>>>> Changes in v11:
>>>> - Switch to using typec bus notifiers.
>>>>
>>>> (no changes since v10)
>>>>
>>>> Changes in v9:
>>>> - Remove the exposed DRM_AUX_HPD_BRIDGE option, and select
>>>> DRM_AUX_HPD_TYPEC_BRIDGE when it is available.
>>>> - Add more commit comment about problem background.
>>>>
>>>> Changes in v8:
>>>> - Merge generic DP HPD bridge into one module.
>>>> ---
>>>>
>>>> drivers/gpu/drm/bridge/Kconfig | 10 ++++
>>>> drivers/gpu/drm/bridge/Makefile | 1 +
>>>> .../gpu/drm/bridge/aux-hpd-typec-dp-bridge.c | 49 +++++++++++++++++++
>>>> 3 files changed, 60 insertions(+)
>>>> create mode 100644 drivers/gpu/drm/bridge/aux-hpd-typec-dp-bridge.c
>>>>
>>>> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
>>>> index a250afd8d662..559487aa09a9 100644
>>>> --- a/drivers/gpu/drm/bridge/Kconfig
>>>> +++ b/drivers/gpu/drm/bridge/Kconfig
>>>> @@ -30,6 +30,16 @@ config DRM_AUX_HPD_BRIDGE
>>>> Simple bridge that terminates the bridge chain and provides HPD
>>>> support.
>>>>
>>>> +if DRM_AUX_HPD_BRIDGE
>>>> +config DRM_AUX_HPD_TYPEC_BRIDGE
>>>> + tristate
>>>> + depends on TYPEC || !TYPEC
>>>> + default TYPEC
>>>> + help
>>>> + Simple bridge that terminates the bridge chain and provides HPD
>>>> + support. It build bridge on each USB-C connector device node.
>>>> +endif
>>>> +
>>>
>>> Should CONFIG_TYPEC_DP_ALTMODE select this one? Otherwise, we need to do it
>>> manually.
>>>
>>> $ grep -nr --include=Kconfig "select DRM_AUX_HPD_BRIDGE" .
>>> ./drivers/soc/qcom/Kconfig:118: select DRM_AUX_HPD_BRIDGE
>>> ./drivers/usb/typec/ucsi/Kconfig:88: select DRM_AUX_HPD_BRIDGE if DRM_BRIDGE && OF
>>> ./drivers/usb/typec/ucsi/Kconfig:99: select DRM_AUX_HPD_BRIDGE if DRM_BRIDGE && OF
>>> ./drivers/usb/typec/tcpm/Kconfig:62: select DRM_AUX_HPD_BRIDGE if DRM_BRIDGE && OF
>>> ./drivers/usb/typec/tcpm/Kconfig:85: select DRM_AUX_HPD_BRIDGE if DRM_BRIDGE && OF
>>>
>>
>> That's a fair point. But based on the previous discussion, Heikki
>> point out that configurations in the TYPEC subsystem should not
>> select configurations from DRM.
>
> I have just reviewed your previous patchsets but I did't find such opinion from
> Heikki. Otherwise, why are tcpm.c/ucsi.c already allowed to add the above select
> condition in their configs?
>
> I think Heikki means that the DRM_AUX_HPD_BRIDGE shouldn't been selected at the
> top level of Type-C subsystem. Because not all Type-C devices support the DP function.
>
> As a generic Type-C DP HPD bridge, displayport.c will likely need to use it in
> the future. Therefore, allowing displayport.c to select DRM_AUX_HPD_BRIDGE makes sense.
>
> According to my testing, it's impossible to build this driver in unless TYPEC_FUSB302
> or a relevant CONFIG is built in to select DRM_AUX_HPD_BRIDGE, or the defconfig is modified.
>
Yep. For me, I select DRM_AUX_HPD_BRIDGE in DRM.
@Heikki, what do you think of the following change?
Should we add a new patch for this? Thanks.
diff --git a/drivers/usb/typec/altmodes/Kconfig b/drivers/usb/typec/altmodes/Kconfig
index 7867fa7c405d..f89cdf3c949b 100644
--- a/drivers/usb/typec/altmodes/Kconfig
+++ b/drivers/usb/typec/altmodes/Kconfig
@@ -5,6 +5,7 @@ menu "USB Type-C Alternate Mode drivers"
config TYPEC_DP_ALTMODE
tristate "DisplayPort Alternate Mode driver"
depends on DRM
+ select DRM_AUX_HPD_BRIDGE
help
DisplayPort USB Type-C Alternate Mode allows DisplayPort
displays and adapters to be attached to the USB Type-C
--
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Chaoyi
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* Re: [PATCH v15 1/9] drm/bridge: Implement generic USB Type-C DP HPD bridge
From: Xu Yang @ 2026-06-29 8:26 UTC (permalink / raw)
To: Chaoyi Chen
Cc: Heikki Krogerus, Chaoyi Chen, Greg Kroah-Hartman,
Dmitry Baryshkov, Peter Chen, Luca Ceresoli, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Heiko Stuebner, Sandy Huang, Andy Yan,
Yubing Zhang, Frank Wang, Andrzej Hajda, Neil Armstrong,
Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Amit Sunil Dhamne, Dragan Simic, Johan Jonker,
Diederik de Haas, Peter Robinson, Hugh Cole-Baker, linux-usb,
devicetree, linux-kernel, linux-phy, linux-arm-kernel,
linux-rockchip, dri-devel
In-Reply-To: <56c6abb8-c127-449f-9368-12f94620c2bc@rock-chips.com>
On Mon, Jun 29, 2026 at 09:29:08AM +0800, Chaoyi Chen wrote:
> Hello Xu Yang,
>
> On 6/26/2026 7:15 PM, Xu Yang wrote:
> > On Wed, Mar 04, 2026 at 05:41:44PM +0800, Chaoyi Chen wrote:
> >> From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
> >>
> >> The HPD function of Type-C DP is implemented through
> >> drm_connector_oob_hotplug_event(). For embedded DP, it is required
> >> that the DRM connector fwnode corresponds to the Type-C port fwnode.
> >>
> >> To describe the relationship between the DP controller and the Type-C
> >> port device, we usually using drm_bridge to build a bridge chain.
> >>
> >> Now several USB-C controller drivers have already implemented the DP
> >> HPD bridge function provided by aux-hpd-bridge.c, it will build a DP
> >> HPD bridge on USB-C connector port device.
> >>
> >> But this requires the USB-C controller driver to manually register the
> >> HPD bridge. If the driver does not implement this feature, the bridge
> >> will not be create.
> >>
> >> So this patch implements a generic DP HPD bridge based on
> >> aux-hpd-bridge.c. It will monitor Type-C bus events, and when a
> >> Type-C port device containing the DP svid is registered, it will
> >> create an HPD bridge for it without the need for the USB-C controller
> >> driver to implement it.
> >>
> >> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
> >> Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
> >> ---
> >>
> >> (no changes since v14)
> >>
> >> Changes in v13:
> >> - Only register drm dp hpd bridge for typec port altmode device.
> >>
> >> (no changes since v12)
> >>
> >> Changes in v11:
> >> - Switch to using typec bus notifiers.
> >>
> >> (no changes since v10)
> >>
> >> Changes in v9:
> >> - Remove the exposed DRM_AUX_HPD_BRIDGE option, and select
> >> DRM_AUX_HPD_TYPEC_BRIDGE when it is available.
> >> - Add more commit comment about problem background.
> >>
> >> Changes in v8:
> >> - Merge generic DP HPD bridge into one module.
> >> ---
> >>
> >> drivers/gpu/drm/bridge/Kconfig | 10 ++++
> >> drivers/gpu/drm/bridge/Makefile | 1 +
> >> .../gpu/drm/bridge/aux-hpd-typec-dp-bridge.c | 49 +++++++++++++++++++
> >> 3 files changed, 60 insertions(+)
> >> create mode 100644 drivers/gpu/drm/bridge/aux-hpd-typec-dp-bridge.c
> >>
> >> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> >> index a250afd8d662..559487aa09a9 100644
> >> --- a/drivers/gpu/drm/bridge/Kconfig
> >> +++ b/drivers/gpu/drm/bridge/Kconfig
> >> @@ -30,6 +30,16 @@ config DRM_AUX_HPD_BRIDGE
> >> Simple bridge that terminates the bridge chain and provides HPD
> >> support.
> >>
> >> +if DRM_AUX_HPD_BRIDGE
> >> +config DRM_AUX_HPD_TYPEC_BRIDGE
> >> + tristate
> >> + depends on TYPEC || !TYPEC
> >> + default TYPEC
> >> + help
> >> + Simple bridge that terminates the bridge chain and provides HPD
> >> + support. It build bridge on each USB-C connector device node.
> >> +endif
> >> +
> >
> > Should CONFIG_TYPEC_DP_ALTMODE select this one? Otherwise, we need to do it
> > manually.
> >
> > $ grep -nr --include=Kconfig "select DRM_AUX_HPD_BRIDGE" .
> > ./drivers/soc/qcom/Kconfig:118: select DRM_AUX_HPD_BRIDGE
> > ./drivers/usb/typec/ucsi/Kconfig:88: select DRM_AUX_HPD_BRIDGE if DRM_BRIDGE && OF
> > ./drivers/usb/typec/ucsi/Kconfig:99: select DRM_AUX_HPD_BRIDGE if DRM_BRIDGE && OF
> > ./drivers/usb/typec/tcpm/Kconfig:62: select DRM_AUX_HPD_BRIDGE if DRM_BRIDGE && OF
> > ./drivers/usb/typec/tcpm/Kconfig:85: select DRM_AUX_HPD_BRIDGE if DRM_BRIDGE && OF
> >
>
> That's a fair point. But based on the previous discussion, Heikki
> point out that configurations in the TYPEC subsystem should not
> select configurations from DRM.
I have just reviewed your previous patchsets but I did't find such opinion from
Heikki. Otherwise, why are tcpm.c/ucsi.c already allowed to add the above select
condition in their configs?
I think Heikki means that the DRM_AUX_HPD_BRIDGE shouldn't been selected at the
top level of Type-C subsystem. Because not all Type-C devices support the DP function.
As a generic Type-C DP HPD bridge, displayport.c will likely need to use it in
the future. Therefore, allowing displayport.c to select DRM_AUX_HPD_BRIDGE makes sense.
According to my testing, it's impossible to build this driver in unless TYPEC_FUSB302
or a relevant CONFIG is built in to select DRM_AUX_HPD_BRIDGE, or the defconfig is modified.
Thanks,
Xu Yang
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* Re: [PATCH V1 0/2] arm64: dts: qcom: Shikra SD Card support
From: Monish Chunara @ 2026-06-29 7:13 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vinod Koul, Neil Armstrong, Wesley Cheng,
Ulf Hansson, Kernel Team, linux-arm-msm, devicetree, linux-kernel,
linux-phy, linux-mmc, Nitin Rawat, Pradeep Pragallapati,
Komal Bajaj, Konrad Dybcio
In-Reply-To: <boo7p6mgop7rarfu3rfsrfah6eq7zp6y3sf6mdq3hsejtacwxx@yl543m4lj47d>
On Tue, Jun 16, 2026 at 03:54:56AM +0300, Dmitry Baryshkov wrote:
> On Thu, Jun 04, 2026 at 05:50:43PM +0530, Monish Chunara wrote:
> > This series adds SD card support for the Shikra platform.
> >
> > The first patch adds the SDHC2 controller node and the necessary pinctrl
> > configurations to the base Shikra SoC dtsi. The second patch enables
> > this support on the Shikra EVK (CQS, CQM, and IQS variants) by defining
> > the regulator supplies and the card detection GPIO.
> >
> > Testing:
> > - Validated on Shikra EVK variants.
> >
> > This series depends on:
> > - https://lore.kernel.org/all/20260527-shikra-dt-v4-0-b5ca1fa0b392@oss.qualcomm.com/
> > - https://lore.kernel.org/all/20260521-shikra-rproc-v3-0-2fca0bbe1ad7@oss.qualcomm.com/
> > - https://lore.kernel.org/linux-devicetree/20260513-tsens_binding-v1-1-1780c6a6caf2@oss.qualcomm.com/
>
> If the SD card depends on remote proc, tsens or cpufreq, then something
> is wrong. Maybe, the way the serieas are organized and sent.
There is no technical dependency on tsens for SD card. The mentioned dependency
series was to ensure the changes get picked up without conflicts.
In the next patch series, only the actual dependenices will be mentioned in the
cover letter.
Regards,
Monish
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* Re: [PATCH RFC v4 5/9] phy: qcom: qmp-pcie: Refactor pipe clk register and parse_dt helpers
From: Qiang Yu @ 2026-06-29 5:56 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Dmitry Baryshkov, Manivannan Sadhasivam, Vinod Koul,
Neil Armstrong, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Philipp Zabel, Bjorn Andersson, Konrad Dybcio, linux-arm-msm,
linux-phy, devicetree, linux-kernel
In-Reply-To: <1bbccb16-b91e-4116-a4cd-213a46978fa1@oss.qualcomm.com>
On Tue, Jun 16, 2026 at 04:05:43PM +0200, Konrad Dybcio wrote:
> On 5/29/26 9:02 AM, Qiang Yu wrote:
> > On Thu, May 28, 2026 at 04:48:24PM +0300, Dmitry Baryshkov wrote:
> >> On Fri, May 22, 2026 at 04:27:35PM +0530, Manivannan Sadhasivam wrote:
> >>> On Wed, May 20, 2026 at 07:25:01PM +0300, Dmitry Baryshkov wrote:
> >>>> On Mon, May 18, 2026 at 10:47:16PM -0700, Qiang Yu wrote:
> >>>>> Some QMP PCIe PHY hardware blocks can be split into multiple sub-PHYs
> >>>>> under a single DT node, each requiring its own pipe clock registration and
> >>>>> DT resource mapping. The current helpers are tightly coupled to a single
> >>>>> qmp_pcie instance, which prevents reuse across sub-PHY instances.
> >>>>>
> >>>>> Refactor __phy_pipe_clk_register() as a generic helper and reduce
> >>>>> phy_pipe_clk_register() to a thin wrapper around it. Similarly, extract
> >>>>> qmp_pcie_parse_dt_common() from qmp_pcie_parse_dt() to hold the register-
> >>>>> mapping and pipe-clock setup that will be shared between sub-PHY instances,
> >>>>> with pipe clock names parameterised per instance.
> >>>>>
> >>>>> This is a preparatory step before adding multi-PHY support. No functional
> >>>>> change for existing platforms.
> >>>>>
> >>>>> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> >>>>> ---
> >>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 76 ++++++++++++++++++--------------
> >>>>> 1 file changed, 44 insertions(+), 32 deletions(-)
> >>>>
> >>>> I'd suggest splitting the Glymur PHY to a separate driver. Otherwise we
> >>>> end up having too many single-platform, single-device specifics which
> >>>> don't apply to other platforms.
> >>>>
> >>>
> >>> I don't think that's really needed. This shared PHY concept is going to be
> >>> applicable to upcoming SoCs as well. And moreover, the split won't be clean
> >>> either. We still need to reuse a lot of common logic in the 'phy-qcom-qmp-pcie'
> >>> driver and may only end up keeping very minimal code in
> >>> 'phy-qcom-qmp-pcie-glymur'.
> >>
> >> Then splitting makes even more sense. Let's not clutter the existing
> >> driver with too many conditions and options.
> >>
> >>>
> >>> If you are concerned about the file size of 'phy-qcom-qmp-pcie', then we should
> >>> move the SoC specific 'cfg' structs into a separate file as that's what
> >>> occupying majority of the space.
> >>
> >> No, it's really the 'shared' part.
> >>
> >
> > To confirm, are you okay with some code duplication between the new
> > Glymur-specific driver and phy-qcom-qmp-pcie driver.
>
> That's a necessity, to some degree. See e.g. qmp-combo and qmp-usbc
>
I've already prototyped a separate Glymur driver, and it turned out better
than expected — there's actually not much duplication. The parts that do
overlap aren't fully identical either; they tend to diverge once the
Glymur-specific handling is factored in.
Currently, I meet an issue when tesing the patch, and will post it after
fixing the issue.
- Qiang Yu
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* Re: [PATCH RFC v4 2/9] dt-bindings: phy: qcom-qmp: Add PHY selector and Glymur link-mode macros
From: Qiang Yu @ 2026-06-29 5:18 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Bjorn Andersson, Konrad Dybcio,
linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <bb3dd1d0-af41-4ecf-b23a-3800aa5414ce@oss.qualcomm.com>
On Tue, Jun 16, 2026 at 04:07:27PM +0200, Konrad Dybcio wrote:
> On 5/19/26 7:47 AM, Qiang Yu wrote:
> > Add two sets of constants to phy-qcom-qmp.h to support upcoming multiple
> > link mode QMP PHY:
> >
> > - QMP_PHY_SELECTOR_0 / QMP_PHY_SELECTOR_1: generic logical PHY index
> > values for QMP providers that expose multiple PHY instances under a
> > single DT node (i.e. #phy-cells = <1>).
> >
> > - QMP_PCIE_GLYMUR_MODE_X8 / QMP_PCIE_GLYMUR_MODE_X4X4: link-mode
> > values for the Glymur Gen5x8 PCIe PHY "qcom,link-mode" syscon property,
> > selecting between the x8 single-PHY and x4+x4 dual-PHY topologies.
> >
> > Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> > ---
> > include/dt-bindings/phy/phy-qcom-qmp.h | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/include/dt-bindings/phy/phy-qcom-qmp.h b/include/dt-bindings/phy/phy-qcom-qmp.h
> > index 6b43ea9e0051..befa76f8392f 100644
> > --- a/include/dt-bindings/phy/phy-qcom-qmp.h
> > +++ b/include/dt-bindings/phy/phy-qcom-qmp.h
> > @@ -21,4 +21,12 @@
> > #define QMP_PCIE_PIPE_CLK 0
> > #define QMP_PCIE_PHY_AUX_CLK 1
> >
> > +/* Generic QMP logical PHY selectors */
> > +#define QMP_PHY_SELECTOR_0 0
> > +#define QMP_PHY_SELECTOR_1 1
>
> Is this for the second phy cell? FWIW I think it's fine to use raw
> numbers as they're just indices (i.e. "nth bifurcated phy") anyway
I can't use lane numbers. In x4+x4 case, I need to tell phy the first 4
lanes or second 4 lanes are required.
- Qiang Yu
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* Re: [PATCH RFC v4 1/9] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add glymur-qmp-gen5x8-pcie-phy compatible
From: Qiang Yu @ 2026-06-29 5:14 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Bjorn Andersson, Konrad Dybcio,
linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <5dffdbe0-cbb9-429e-ba15-0afdf6f20fba@oss.qualcomm.com>
On Tue, Jun 16, 2026 at 04:03:39PM +0200, Konrad Dybcio wrote:
> On 5/19/26 7:47 AM, Qiang Yu wrote:
> > The Glymur SoC uses a single PCIe Gen5 PHY hardware block for the
> > PCIe3a/PCIe3b controllers. This block supports two link modes:
> >
> > 1. x4+x4: two 4-lane PHY instances are exposed
> > 2. x8: one 8-lane PHY instance is exposed
> >
> > Add qcom,glymur-qmp-gen5x8-pcie-phy as a multi-mode PHY compatible and
> > document the new link-mode property, which selects the active link mode
> > via a TCSR syscon register.
> >
> > Document the required clocks, resets, and power-domains for both PHY
> > instances active in x8 mode. Use #phy-cells = <1> for this compatible,
> > where the cell value is the PHY index within the active link mode.
> >
> > Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> > ---
>
> [...]
>
> > @@ -68,20 +69,29 @@ properties:
> > - const: ref
> > - enum: [rchng, refgen]
> > - const: pipe
> > - - const: pipediv2
> > + - enum: [pipediv2, phy_b_aux]
>
> I'm surprised to learn 3A doesnm'doesn't have a PIPE_DIV2 clk.. it does have
> a non-div2 one though.
>
> Seems like it's specifically not the case on Hamoa and Makena, so perhaps
> it's better for maintainability if the Glymur list was separate
>
Do you mean splitting Glymur out into a separate YAML file for the PCIe3
PHY? I'll add a new file if that's preferred and Krzysztof is on board.
- Qiang Yu
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* Re: [PATCH RFC v4 9/9] arm64: dts: qcom: glymur: Wire PCIe3a/3b to shared Gen5x8 PHY
From: Qiang Yu @ 2026-06-29 5:05 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Bjorn Andersson, Konrad Dybcio,
linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <ab21f1c7-f861-4961-9287-84cae280d8c1@oss.qualcomm.com>
On Wed, Jun 17, 2026 at 01:19:49PM +0200, Konrad Dybcio wrote:
> On 5/19/26 7:47 AM, Qiang Yu wrote:
> > Glymur PCIe3 uses a single shared Gen5x8 QMP PHY block. Model PCIe3a and
> > PCIe3b as consumers of that shared PHY provider instead of separate PHY
> > nodes.
> >
> > Update the DTS wiring to:
> > - point GCC PCIe3A/3B pipe parents to the shared PHY clock outputs
> > - add PCIe3a controller node and route PCIe3a/PCIe3b port phys to
> > &pcie3_phy using two-cell PHY arguments
> > - configure the shared PHY node with link-mode and dual pipe outputs
> >
> > Use QMP_PCIE_GLYMUR_MODE_* dt-binding macros for mode selection.
> >
> > Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> > ---
>
> [...]
>
> > + pcie3a: pci@1c10000 {
> > + device_type = "pci";
> > + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
> > + reg = <0x0 0x01c10000 0x0 0x3000>,
> > + <0x0 0x70000000 0x0 0xf20>,
> > + <0x0 0x70000f40 0x0 0xa8>,
> > + <0x0 0x70001000 0x0 0x4000>,
> > + <0x0 0x70100000 0x0 0x100000>,
> > + <0x0 0x01c13000 0x0 0x1000>;
> > + reg-names = "parf",
> > + "dbi",
> > + "elbi",
> > + "atu",
> > + "config",
> > + "mhi";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>,
> > + <0x02000000 0x0 0x70000000 0x0 0x70300000 0x0 0x3d00000>,
> > + <0x03000000 0x7 0x00000000 0x7 0x00000000 0x0 0x40000000>,
> > + <0x43000000 0x70 0x00000000 0x70 0x00000000 0x10 0x00000000>;
> > +
> > + bus-range = <0 0xff>;
> > +
> > + dma-coherent;
> > +
> > + linux,pci-domain = <3>;
> > + num-lanes = <8>;
>
> Is it fine to keep num-lanes 8 here even for configurations with
> bifurcated PHY?
>
> I would assume so, given essentially this is a x8 host, whose 4
> lanes may simply be effectively NC
>
Actually, on existing platforms, the PCIe3a and PCIe3b controllers are
never enabled at the same time. When PCIe3a is exposed, it is always in an
x8 slot. But if we have a x4+x4 platform in future, we can simply override
num-lanes to 4 in the board.dts.
- Qiang Yu
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* Re: [PATCH v15 1/9] drm/bridge: Implement generic USB Type-C DP HPD bridge
From: Chaoyi Chen @ 2026-06-29 1:29 UTC (permalink / raw)
To: Xu Yang, Heikki Krogerus
Cc: Chaoyi Chen, Greg Kroah-Hartman, Dmitry Baryshkov, Peter Chen,
Luca Ceresoli, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Vinod Koul, Kishon Vijay Abraham I, Heiko Stuebner, Sandy Huang,
Andy Yan, Yubing Zhang, Frank Wang, Andrzej Hajda, Neil Armstrong,
Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Amit Sunil Dhamne, Dragan Simic, Johan Jonker,
Diederik de Haas, Peter Robinson, Hugh Cole-Baker, linux-usb,
devicetree, linux-kernel, linux-phy, linux-arm-kernel,
linux-rockchip, dri-devel
In-Reply-To: <erx73m2ueuvbzjteadjli6aki5by4pr3hyertkkqqoqwhaa4v3@5cstmshcercx>
Hello Xu Yang,
On 6/26/2026 7:15 PM, Xu Yang wrote:
> On Wed, Mar 04, 2026 at 05:41:44PM +0800, Chaoyi Chen wrote:
>> From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
>>
>> The HPD function of Type-C DP is implemented through
>> drm_connector_oob_hotplug_event(). For embedded DP, it is required
>> that the DRM connector fwnode corresponds to the Type-C port fwnode.
>>
>> To describe the relationship between the DP controller and the Type-C
>> port device, we usually using drm_bridge to build a bridge chain.
>>
>> Now several USB-C controller drivers have already implemented the DP
>> HPD bridge function provided by aux-hpd-bridge.c, it will build a DP
>> HPD bridge on USB-C connector port device.
>>
>> But this requires the USB-C controller driver to manually register the
>> HPD bridge. If the driver does not implement this feature, the bridge
>> will not be create.
>>
>> So this patch implements a generic DP HPD bridge based on
>> aux-hpd-bridge.c. It will monitor Type-C bus events, and when a
>> Type-C port device containing the DP svid is registered, it will
>> create an HPD bridge for it without the need for the USB-C controller
>> driver to implement it.
>>
>> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
>> Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
>> ---
>>
>> (no changes since v14)
>>
>> Changes in v13:
>> - Only register drm dp hpd bridge for typec port altmode device.
>>
>> (no changes since v12)
>>
>> Changes in v11:
>> - Switch to using typec bus notifiers.
>>
>> (no changes since v10)
>>
>> Changes in v9:
>> - Remove the exposed DRM_AUX_HPD_BRIDGE option, and select
>> DRM_AUX_HPD_TYPEC_BRIDGE when it is available.
>> - Add more commit comment about problem background.
>>
>> Changes in v8:
>> - Merge generic DP HPD bridge into one module.
>> ---
>>
>> drivers/gpu/drm/bridge/Kconfig | 10 ++++
>> drivers/gpu/drm/bridge/Makefile | 1 +
>> .../gpu/drm/bridge/aux-hpd-typec-dp-bridge.c | 49 +++++++++++++++++++
>> 3 files changed, 60 insertions(+)
>> create mode 100644 drivers/gpu/drm/bridge/aux-hpd-typec-dp-bridge.c
>>
>> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
>> index a250afd8d662..559487aa09a9 100644
>> --- a/drivers/gpu/drm/bridge/Kconfig
>> +++ b/drivers/gpu/drm/bridge/Kconfig
>> @@ -30,6 +30,16 @@ config DRM_AUX_HPD_BRIDGE
>> Simple bridge that terminates the bridge chain and provides HPD
>> support.
>>
>> +if DRM_AUX_HPD_BRIDGE
>> +config DRM_AUX_HPD_TYPEC_BRIDGE
>> + tristate
>> + depends on TYPEC || !TYPEC
>> + default TYPEC
>> + help
>> + Simple bridge that terminates the bridge chain and provides HPD
>> + support. It build bridge on each USB-C connector device node.
>> +endif
>> +
>
> Should CONFIG_TYPEC_DP_ALTMODE select this one? Otherwise, we need to do it
> manually.
>
> $ grep -nr --include=Kconfig "select DRM_AUX_HPD_BRIDGE" .
> ./drivers/soc/qcom/Kconfig:118: select DRM_AUX_HPD_BRIDGE
> ./drivers/usb/typec/ucsi/Kconfig:88: select DRM_AUX_HPD_BRIDGE if DRM_BRIDGE && OF
> ./drivers/usb/typec/ucsi/Kconfig:99: select DRM_AUX_HPD_BRIDGE if DRM_BRIDGE && OF
> ./drivers/usb/typec/tcpm/Kconfig:62: select DRM_AUX_HPD_BRIDGE if DRM_BRIDGE && OF
> ./drivers/usb/typec/tcpm/Kconfig:85: select DRM_AUX_HPD_BRIDGE if DRM_BRIDGE && OF
>
That's a fair point. But based on the previous discussion, Heikki
point out that configurations in the TYPEC subsystem should not
select configurations from DRM.
--
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Chaoyi
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* Re: [PATCH] MAINTAINERS: Add Radhey Shyam Pandey as ZynqMP PHY maintainer
From: Laurent Pinchart @ 2026-06-28 21:12 UTC (permalink / raw)
To: Radhey Shyam Pandey
Cc: tomi.valkeinen, vkoul, michal.simek, linux-kernel, linux-phy,
linux-arm-kernel
In-Reply-To: <20260627162233.2803425-1-radhey.shyam.pandey@amd.com>
On Sat, Jun 27, 2026 at 09:52:33PM +0530, Radhey Shyam Pandey wrote:
> I am maintaining phy-zynqmp driver in xilinx tree and would like to
> maintain it in the mainline kernel as well. Hence adding myself as a
> maintainer.
>
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Thank you for volunteering.
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1705eb823dd0..90dd86437c5c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -29645,6 +29645,7 @@ F: drivers/edac/zynqmp_edac.c
>
> XILINX ZYNQMP PSGTR PHY DRIVER
> M: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
> +M: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
> L: linux-kernel@vger.kernel.org
> S: Supported
> T: git https://github.com/Xilinx/linux-xlnx.git
>
> base-commit: 3d5670d672ae08b8c534b7beed6f57c8b44e7b43
--
Regards,
Laurent Pinchart
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