* Re: [PATCH v4 3/4] phy: qcom-qusb2: Add support for Shikra
From: Krishna Kurapati @ 2026-07-02 15:54 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Neil Armstrong, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio, Xiangxu Yin,
Johan Hovold, Loic Poulain, Shawn Guo, Abel Vesa, Wesley Cheng,
linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <ym4zec5vw2mudnvhw36w6vkuqupbl6up4dqmhk2sqeabphotsf@sudiy6poyjyx>
On 7/2/2026 7:18 PM, Dmitry Baryshkov wrote:
> On Wed, Jul 01, 2026 at 10:20:50PM +0530, Krishna Kurapati wrote:
>> Add init sequence and phy configuration for Shikra.
>>
>> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
>> ---
>> drivers/phy/qualcomm/phy-qcom-qusb2.c | 16 ++++++++++++++++
>> 1 file changed, 16 insertions(+)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> index eb93015be841..ab7437e7b751 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> @@ -381,6 +381,19 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = {
>> .autoresume_en = BIT(3),
>> };
>>
>> +static const struct qusb2_phy_cfg shikra_phy_cfg = {
>> + .tbl = qcs615_init_tbl,
>> + .tbl_num = ARRAY_SIZE(qcs615_init_tbl),
>> + .regs = ipq6018_regs_layout,
>
> msm8996_regs_layout (otherwise you are programming the wrong register).
>
ACK. Will send v5 on top of your upcoming v2.
Regards,
Krishna,
>> +
>> + .has_pll_test = true,
>> + .se_clk_scheme_default = true,
>> + .disable_ctrl = CLAMP_N_EN | FREEZIO_N | POWER_DOWN,
>> + .mask_core_ready = PLL_LOCKED,
>> + .autoresume_en = BIT(3),
>> + .update_tune1_with_efuse = false,
>> +};
>> +
>> static const struct qusb2_phy_cfg sm6115_phy_cfg = {
>> .tbl = sm6115_init_tbl,
>> .tbl_num = ARRAY_SIZE(sm6115_init_tbl),
>> @@ -958,6 +971,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
>> }, {
>> .compatible = "qcom,sdm660-qusb2-phy",
>> .data = &sdm660_phy_cfg,
>> + }, {
>> + .compatible = "qcom,shikra-qusb2-phy",
>> + .data = &shikra_phy_cfg,
>> }, {
>> .compatible = "qcom,sm4250-qusb2-phy",
>> .data = &sm6115_phy_cfg,
>> --
>> 2.34.1
>>
>
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* Re: [PATCH] phy: renesas: rcar-gen3-usb2: Ignore missing VBUS regulator
From: Tommaso Merciai @ 2026-07-02 15:45 UTC (permalink / raw)
To: Prabhakar
Cc: Yoshihiro Shimoda, Vinod Koul, Neil Armstrong, Geert Uytterhoeven,
Magnus Damm, linux-renesas-soc, linux-phy, linux-kernel,
Prabhakar, Biju Das, Fabrizio Castro, Lad Prabhakar
In-Reply-To: <20260702125855.3157253-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Prabhakar,
Thanks for your patch.
On Thu, Jul 02, 2026 at 01:58:55PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Commit b6d7dd157763 ("phy: renesas: rcar-gen3-usb2: Add regulator for
> OTG VBUS control") introduced support for controlling OTG VBUS through
> the regulator framework.
>
> As part of this change, the driver started requesting an exclusive "vbus"
> regulator for OTG-capable PHYs with no_adp_ctrl set. The lookup failure
> was propagated unconditionally, causing probe to fail on platforms where
> no VBUS regulator is described.
>
> On RZ/V2H and RZ/V2N, which do not use a VBUS regulator, this results
> in the following error:
>
> phy_rcar_gen3_usb2 15800200.usb-phy:
> dummy supplies not allowed for exclusive requests (id=vbus)
>
> This failure completely prevents the USB 2.0 interface from initializing.
>
> Fix this by allowing the probe to continue if an external VBUS regulator
> is missing. Only propagate the error if the internal vbus-regulator node
> is explicitly present, or if the lookup returns -EPROBE_DEFER. For all
> other missing regulator errors, gracefully assume no external VBUS
> regulator is available and return 0.
>
Patch LGTM, tested on RZ/G3E.
Tested-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Thanks, Tommaso
> Fixes: b6d7dd157763 ("phy: renesas: rcar-gen3-usb2: Add regulator for OTG VBUS control")
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> drivers/phy/renesas/phy-rcar-gen3-usb2.c | 13 +++++++++++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> index ef38c3b365d4..9ae9975d3255 100644
> --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
> @@ -902,8 +902,17 @@ static int rcar_gen3_phy_usb2_vbus_regulator_get_exclusive_enable(struct rcar_ge
> int ret;
>
> channel->vbus = devm_regulator_get_exclusive(dev, "vbus");
> - if (IS_ERR(channel->vbus))
> - return PTR_ERR(channel->vbus);
> + if (IS_ERR(channel->vbus)) {
> + ret = PTR_ERR(channel->vbus);
> + /* If vbus-regulator node was present vbus regulator should be available */
> + if (channel->otg_internal_reg)
> + return ret;
> +
> + if (ret == -EPROBE_DEFER)
> + return ret;
> +
> + return 0;
> + }
>
> if (enable) {
> ret = regulator_enable(channel->vbus);
> --
> 2.54.0
>
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* Re: [PATCH v4 3/4] phy: qcom-qusb2: Add support for Shikra
From: Dmitry Baryshkov @ 2026-07-02 13:48 UTC (permalink / raw)
To: Krishna Kurapati
Cc: Neil Armstrong, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio, Xiangxu Yin,
Johan Hovold, Loic Poulain, Shawn Guo, Abel Vesa, Wesley Cheng,
linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <20260701165051.4122259-4-krishna.kurapati@oss.qualcomm.com>
On Wed, Jul 01, 2026 at 10:20:50PM +0530, Krishna Kurapati wrote:
> Add init sequence and phy configuration for Shikra.
>
> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qusb2.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> index eb93015be841..ab7437e7b751 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> @@ -381,6 +381,19 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = {
> .autoresume_en = BIT(3),
> };
>
> +static const struct qusb2_phy_cfg shikra_phy_cfg = {
> + .tbl = qcs615_init_tbl,
> + .tbl_num = ARRAY_SIZE(qcs615_init_tbl),
> + .regs = ipq6018_regs_layout,
msm8996_regs_layout (otherwise you are programming the wrong register).
> +
> + .has_pll_test = true,
> + .se_clk_scheme_default = true,
> + .disable_ctrl = CLAMP_N_EN | FREEZIO_N | POWER_DOWN,
> + .mask_core_ready = PLL_LOCKED,
> + .autoresume_en = BIT(3),
> + .update_tune1_with_efuse = false,
> +};
> +
> static const struct qusb2_phy_cfg sm6115_phy_cfg = {
> .tbl = sm6115_init_tbl,
> .tbl_num = ARRAY_SIZE(sm6115_init_tbl),
> @@ -958,6 +971,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
> }, {
> .compatible = "qcom,sdm660-qusb2-phy",
> .data = &sdm660_phy_cfg,
> + }, {
> + .compatible = "qcom,shikra-qusb2-phy",
> + .data = &shikra_phy_cfg,
> }, {
> .compatible = "qcom,sm4250-qusb2-phy",
> .data = &sm6115_phy_cfg,
> --
> 2.34.1
>
--
With best wishes
Dmitry
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* Re: [PATCH 1/2] phy: qcom-qusb2: don't unrelated bits if autoresume is not used
From: Dmitry Baryshkov @ 2026-07-02 13:46 UTC (permalink / raw)
To: Krishna Kurapati
Cc: Konrad Dybcio, Wesley Cheng, Vinod Koul, Neil Armstrong,
Kathiravan T, Baruch Siach, Dmitry Baryshkov, linux-arm-msm,
linux-phy, linux-kernel
In-Reply-To: <e39c9092-30f3-4c04-8bdc-c6400871cecf@oss.qualcomm.com>
On Thu, Jul 02, 2026 at 07:13:29PM +0530, Krishna Kurapati wrote:
>
>
> On 7/2/2026 5:54 PM, Konrad Dybcio wrote:
> > On 7/2/26 2:21 PM, Dmitry Baryshkov wrote:
> > > On Thu, Jul 02, 2026 at 02:00:06PM +0200, Konrad Dybcio wrote:
> > > > On 7/2/26 1:40 PM, Dmitry Baryshkov wrote:
> > > > > The IPQ6018 and QCS615 platforms don't need to toggle the autoresume
> > > > > bit.
> > > >
> > > > why?
> > >
> > > Here I have no idea, the HPG is unspecific, exact details are to be
> > > defined somewhere else. The platforms, when they were added, just stated
> > > that autoresume is to be skipped. Maybe original developers (in cc) can
> > > answer this question. Anyway, if autoresume is to be toggled, it should
> > > be coming as a separate fixup. I can reorder the patches though, so that
> > > at least register layout is correct.
> >
> > +Krishna, Wesley?
> >
[..]
>
> Also for qcs615, in downstream code, I see that auto-resume is being set.
> Its a mistake from my end when I added [1].
>
> [1]: https://lore.kernel.org/all/20241014084432.3310114-5-quic_kriskura@quicinc.com/
Ok, I'll fix it in v2.
Do we need to enable autoresume for IPQ6018 too?
--
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Dmitry
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* Re: [PATCH 1/2] phy: qcom-qusb2: don't unrelated bits if autoresume is not used
From: Krishna Kurapati @ 2026-07-02 13:43 UTC (permalink / raw)
To: Konrad Dybcio, Dmitry Baryshkov, Wesley Cheng
Cc: Vinod Koul, Neil Armstrong, Kathiravan T, Baruch Siach,
Dmitry Baryshkov, linux-arm-msm, linux-phy, linux-kernel
In-Reply-To: <3c533783-e2a5-48f3-8275-4cef5651938b@oss.qualcomm.com>
On 7/2/2026 5:54 PM, Konrad Dybcio wrote:
> On 7/2/26 2:21 PM, Dmitry Baryshkov wrote:
>> On Thu, Jul 02, 2026 at 02:00:06PM +0200, Konrad Dybcio wrote:
>>> On 7/2/26 1:40 PM, Dmitry Baryshkov wrote:
>>>> The IPQ6018 and QCS615 platforms don't need to toggle the autoresume
>>>> bit.
>>>
>>> why?
>>
>> Here I have no idea, the HPG is unspecific, exact details are to be
>> defined somewhere else. The platforms, when they were added, just stated
>> that autoresume is to be skipped. Maybe original developers (in cc) can
>> answer this question. Anyway, if autoresume is to be toggled, it should
>> be coming as a separate fixup. I can reorder the patches though, so that
>> at least register layout is correct.
>
> +Krishna, Wesley?
>
I checked downstream driver code and I see this:
1. If the phy is qusb2 v2, then we are setting and clearing BIT(0) of
TEST1 register.
2. If the phy is qusb2, then we are setting and clearing BIT(3) of
TEST_CTRL register.
For both IPQ6018 and QCS615, I checked and its BIT(3) of TEST_CTRL
register to be set.
For msm8998 it is BIT(0) of TEST1 register.
Also for qcs615, in downstream code, I see that auto-resume is being
set. Its a mistake from my end when I added [1].
[1]:
https://lore.kernel.org/all/20241014084432.3310114-5-quic_kriskura@quicinc.com/
Regards,
Krishna,
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* Re: [PATCH] phy: renesas: rcar-gen3-usb2: Ignore missing VBUS regulator
From: Lad, Prabhakar @ 2026-07-02 13:04 UTC (permalink / raw)
To: Yoshihiro Shimoda, Vinod Koul, Neil Armstrong, Geert Uytterhoeven,
Magnus Damm, Tommaso Merciai
Cc: linux-renesas-soc, linux-phy, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
In-Reply-To: <20260702125855.3157253-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
On Thu, Jul 2, 2026 at 1:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Commit b6d7dd157763 ("phy: renesas: rcar-gen3-usb2: Add regulator for
> OTG VBUS control") introduced support for controlling OTG VBUS through
> the regulator framework.
>
> As part of this change, the driver started requesting an exclusive "vbus"
> regulator for OTG-capable PHYs with no_adp_ctrl set. The lookup failure
> was propagated unconditionally, causing probe to fail on platforms where
> no VBUS regulator is described.
>
> On RZ/V2H and RZ/V2N, which do not use a VBUS regulator, this results
> in the following error:
>
> phy_rcar_gen3_usb2 15800200.usb-phy:
> dummy supplies not allowed for exclusive requests (id=vbus)
>
> This failure completely prevents the USB 2.0 interface from initializing.
>
> Fix this by allowing the probe to continue if an external VBUS regulator
> is missing. Only propagate the error if the internal vbus-regulator node
> is explicitly present, or if the lookup returns -EPROBE_DEFER. For all
> other missing regulator errors, gracefully assume no external VBUS
> regulator is available and return 0.
>
> Fixes: b6d7dd157763 ("phy: renesas: rcar-gen3-usb2: Add regulator for OTG VBUS control")
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> drivers/phy/renesas/phy-rcar-gen3-usb2.c | 13 +++++++++++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
>
Note, this patch applies on top of patch [0].
[0] https://lore.kernel.org/all/20260616104459.410743-9-biju.das.jz@bp.renesas.com/
Cheers,
Prabhakar
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* [PATCH] phy: renesas: rcar-gen3-usb2: Ignore missing VBUS regulator
From: Prabhakar @ 2026-07-02 12:58 UTC (permalink / raw)
To: Yoshihiro Shimoda, Vinod Koul, Neil Armstrong, Geert Uytterhoeven,
Magnus Damm, Tommaso Merciai
Cc: linux-renesas-soc, linux-phy, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Commit b6d7dd157763 ("phy: renesas: rcar-gen3-usb2: Add regulator for
OTG VBUS control") introduced support for controlling OTG VBUS through
the regulator framework.
As part of this change, the driver started requesting an exclusive "vbus"
regulator for OTG-capable PHYs with no_adp_ctrl set. The lookup failure
was propagated unconditionally, causing probe to fail on platforms where
no VBUS regulator is described.
On RZ/V2H and RZ/V2N, which do not use a VBUS regulator, this results
in the following error:
phy_rcar_gen3_usb2 15800200.usb-phy:
dummy supplies not allowed for exclusive requests (id=vbus)
This failure completely prevents the USB 2.0 interface from initializing.
Fix this by allowing the probe to continue if an external VBUS regulator
is missing. Only propagate the error if the internal vbus-regulator node
is explicitly present, or if the lookup returns -EPROBE_DEFER. For all
other missing regulator errors, gracefully assume no external VBUS
regulator is available and return 0.
Fixes: b6d7dd157763 ("phy: renesas: rcar-gen3-usb2: Add regulator for OTG VBUS control")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index ef38c3b365d4..9ae9975d3255 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -902,8 +902,17 @@ static int rcar_gen3_phy_usb2_vbus_regulator_get_exclusive_enable(struct rcar_ge
int ret;
channel->vbus = devm_regulator_get_exclusive(dev, "vbus");
- if (IS_ERR(channel->vbus))
- return PTR_ERR(channel->vbus);
+ if (IS_ERR(channel->vbus)) {
+ ret = PTR_ERR(channel->vbus);
+ /* If vbus-regulator node was present vbus regulator should be available */
+ if (channel->otg_internal_reg)
+ return ret;
+
+ if (ret == -EPROBE_DEFER)
+ return ret;
+
+ return 0;
+ }
if (enable) {
ret = regulator_enable(channel->vbus);
--
2.54.0
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* Re: [PATCH 0/4 v2] Serdes: s32g: Add support for serdes subsystem
From: Vincent Guittot @ 2026-07-02 12:46 UTC (permalink / raw)
To: Jan Petrous
Cc: vkoul, neil.armstrong, krzk+dt, conor+dt, ciprianmarian.costea,
s32, p.zabel, linux, ghennadi.procopciuc, Ionut.Vicovan,
linux-phy, devicetree, linux-kernel, linux-arm-kernel, netdev,
horms, Frank.li
In-Reply-To: <akZcpgDSjAg6gcok@lsv051416.swis.nl-cdc01.nxp.com>
On Thu, 2 Jul 2026 at 14:42, Jan Petrous <jan.petrous@oss.nxp.com> wrote:
>
> On Tue, Feb 03, 2026 at 05:19:13PM +0100, Vincent Guittot wrote:
> > s32g SoC family includes 2 serdes subsystems which are made of one PCIe
> > controller, 2 XPCS and a shared Phy. The Phy got 2 lanes that can be
> > configured to output PCIe lanes and/or SGMII.
> >
> > Implement PCIe phy and XPCS support.
> >
> > Change since v1:
> > - Fix compile_test
> > - Use devm_reset_control_get_exclusive()
> > - Fix s32g_serdes_phy_set_mode_ext()
> > - Manage devm_clk_bulk_get_all() returns 0
> > - Fix s32g_serdes_parse_lanes() error management
> > - Move xpcs filein drivers/net/pcs/
> > - Add pcs_inband_caps()
> > - Fix functions in phylink_pcs_ops
> > - Fix MAINTAINERS
> >
> >
> > Vincent Guittot (4):
> > dt-bindings: serdes: s32g: Add NXP serdes subsystem
> > phy: s32g: Add serdes subsystem phy
> > phy: s32g: Add serdes xpcs subsystem
> > MAINTAINERS: Add MAINTAINER for NXP S32G Serdes driver
> >
> > .../bindings/phy/nxp,s32g-serdes.yaml | 154 +++
> > MAINTAINERS | 10 +
> > drivers/net/pcs/Makefile | 1 +
> > drivers/net/pcs/pcs-nxp-s32g-xpcs.c | 1006 +++++++++++++++++
> > drivers/phy/freescale/Kconfig | 10 +
> > drivers/phy/freescale/Makefile | 1 +
> > drivers/phy/freescale/phy-nxp-s32g-serdes.c | 953 ++++++++++++++++
> > include/linux/pcs/pcs-nxp-s32g-xpcs.h | 50 +
> > 8 files changed, 2185 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/phy/nxp,s32g-serdes.yaml
> > create mode 100644 drivers/net/pcs/pcs-nxp-s32g-xpcs.c
> > create mode 100644 drivers/phy/freescale/phy-nxp-s32g-serdes.c
> > create mode 100644 include/linux/pcs/pcs-nxp-s32g-xpcs.h
> >
> > --
> > 2.43.0
> >
>
> Hi Vincent, all,
> I'm taking over the S32G SerDes/XPCS upstreaming. The effort has moved in-house
> at NXP and I'll be carrying it forward, continuing from this v2 rather than
> restarting from zero.
>
> Vincent, thanks for the v1->v2 groundwork. I'll keep your authorship on the
> patches that originate from your series (Co-developed-by plus your
> Signed-off-by) and build on top; I'll send you v3 off-list first, as you
> offered.
>
> A v3 is in preparation and will come as an RFC, with the v2 review comments
> addressed.
>
> Vincent, if you're OK with the handoff, a short ack here would help make the
> transition visible to the reviewers.
Ack
Thanks
Vincent
>
> Thanks.
> /Jan
>
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* Re: [PATCH 0/4 v2] Serdes: s32g: Add support for serdes subsystem
From: Jan Petrous @ 2026-07-02 12:42 UTC (permalink / raw)
To: Vincent Guittot
Cc: vkoul, neil.armstrong, krzk+dt, conor+dt, ciprianmarian.costea,
s32, p.zabel, linux, ghennadi.procopciuc, Ionut.Vicovan,
linux-phy, devicetree, linux-kernel, linux-arm-kernel, netdev,
horms, Frank.li
In-Reply-To: <20260203161917.1666696-1-vincent.guittot@linaro.org>
On Tue, Feb 03, 2026 at 05:19:13PM +0100, Vincent Guittot wrote:
> s32g SoC family includes 2 serdes subsystems which are made of one PCIe
> controller, 2 XPCS and a shared Phy. The Phy got 2 lanes that can be
> configured to output PCIe lanes and/or SGMII.
>
> Implement PCIe phy and XPCS support.
>
> Change since v1:
> - Fix compile_test
> - Use devm_reset_control_get_exclusive()
> - Fix s32g_serdes_phy_set_mode_ext()
> - Manage devm_clk_bulk_get_all() returns 0
> - Fix s32g_serdes_parse_lanes() error management
> - Move xpcs filein drivers/net/pcs/
> - Add pcs_inband_caps()
> - Fix functions in phylink_pcs_ops
> - Fix MAINTAINERS
>
>
> Vincent Guittot (4):
> dt-bindings: serdes: s32g: Add NXP serdes subsystem
> phy: s32g: Add serdes subsystem phy
> phy: s32g: Add serdes xpcs subsystem
> MAINTAINERS: Add MAINTAINER for NXP S32G Serdes driver
>
> .../bindings/phy/nxp,s32g-serdes.yaml | 154 +++
> MAINTAINERS | 10 +
> drivers/net/pcs/Makefile | 1 +
> drivers/net/pcs/pcs-nxp-s32g-xpcs.c | 1006 +++++++++++++++++
> drivers/phy/freescale/Kconfig | 10 +
> drivers/phy/freescale/Makefile | 1 +
> drivers/phy/freescale/phy-nxp-s32g-serdes.c | 953 ++++++++++++++++
> include/linux/pcs/pcs-nxp-s32g-xpcs.h | 50 +
> 8 files changed, 2185 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/nxp,s32g-serdes.yaml
> create mode 100644 drivers/net/pcs/pcs-nxp-s32g-xpcs.c
> create mode 100644 drivers/phy/freescale/phy-nxp-s32g-serdes.c
> create mode 100644 include/linux/pcs/pcs-nxp-s32g-xpcs.h
>
> --
> 2.43.0
>
Hi Vincent, all,
I'm taking over the S32G SerDes/XPCS upstreaming. The effort has moved in-house
at NXP and I'll be carrying it forward, continuing from this v2 rather than
restarting from zero.
Vincent, thanks for the v1->v2 groundwork. I'll keep your authorship on the
patches that originate from your series (Co-developed-by plus your
Signed-off-by) and build on top; I'll send you v3 off-list first, as you
offered.
A v3 is in preparation and will come as an RFC, with the v2 review comments
addressed.
Vincent, if you're OK with the handoff, a short ack here would help make the
transition visible to the reviewers.
Thanks.
/Jan
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* Re: [PATCH 1/2] phy: qcom-qusb2: don't unrelated bits if autoresume is not used
From: Konrad Dybcio @ 2026-07-02 12:24 UTC (permalink / raw)
To: Dmitry Baryshkov, Krishna Kurapati, Wesley Cheng
Cc: Vinod Koul, Neil Armstrong, Kathiravan T, Baruch Siach,
Dmitry Baryshkov, Krishna Kurapati, linux-arm-msm, linux-phy,
linux-kernel
In-Reply-To: <3goo36jai5g2v24ijlf7g4gehq5zdlk7uwizya7dimqtm5pmrs@norf4xbqdlw5>
On 7/2/26 2:21 PM, Dmitry Baryshkov wrote:
> On Thu, Jul 02, 2026 at 02:00:06PM +0200, Konrad Dybcio wrote:
>> On 7/2/26 1:40 PM, Dmitry Baryshkov wrote:
>>> The IPQ6018 and QCS615 platforms don't need to toggle the autoresume
>>> bit.
>>
>> why?
>
> Here I have no idea, the HPG is unspecific, exact details are to be
> defined somewhere else. The platforms, when they were added, just stated
> that autoresume is to be skipped. Maybe original developers (in cc) can
> answer this question. Anyway, if autoresume is to be toggled, it should
> be coming as a separate fixup. I can reorder the patches though, so that
> at least register layout is correct.
+Krishna, Wesley?
Konrad
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* Re: [PATCH 1/2] phy: qcom-qusb2: don't unrelated bits if autoresume is not used
From: Dmitry Baryshkov @ 2026-07-02 12:21 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Vinod Koul, Neil Armstrong, Kathiravan T, Baruch Siach,
Dmitry Baryshkov, Krishna Kurapati, linux-arm-msm, linux-phy,
linux-kernel
In-Reply-To: <64f7efcc-1cd6-40f5-80c0-ab5f882854a3@oss.qualcomm.com>
On Thu, Jul 02, 2026 at 02:00:06PM +0200, Konrad Dybcio wrote:
> On 7/2/26 1:40 PM, Dmitry Baryshkov wrote:
> > The IPQ6018 and QCS615 platforms don't need to toggle the autoresume
> > bit.
>
> why?
Here I have no idea, the HPG is unspecific, exact details are to be
defined somewhere else. The platforms, when they were added, just stated
that autoresume is to be skipped. Maybe original developers (in cc) can
answer this question. Anyway, if autoresume is to be toggled, it should
be coming as a separate fixup. I can reorder the patches though, so that
at least register layout is correct.
--
With best wishes
Dmitry
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* Re: [PATCH V3 2/2] arm64: dts: qcom: Enable SD card for Shikra EVK
From: Konrad Dybcio @ 2026-07-02 12:08 UTC (permalink / raw)
To: Monish Chunara, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul, Neil Armstrong,
Wesley Cheng, Ulf Hansson, Kernel Team
Cc: linux-arm-msm, devicetree, linux-kernel, linux-phy, linux-mmc,
Nitin Rawat, Pradeep Pragallapati, Komal Bajaj
In-Reply-To: <20260702073354.3641966-3-monish.chunara@oss.qualcomm.com>
On 7/2/26 9:33 AM, Monish Chunara wrote:
> Enable SD card for Shikra CQS, CQM and IQS EVK variants. Configure the
> vmmc/vqmmc regulators and gpio-based card detection for each board
> variant.
>
> Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
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* Re: [PATCH V3 1/2] arm64: dts: qcom: Add SD Card support for Shikra SoC
From: Konrad Dybcio @ 2026-07-02 12:08 UTC (permalink / raw)
To: Monish Chunara, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul, Neil Armstrong,
Wesley Cheng, Ulf Hansson, Kernel Team
Cc: linux-arm-msm, devicetree, linux-kernel, linux-phy, linux-mmc,
Nitin Rawat, Pradeep Pragallapati, Komal Bajaj
In-Reply-To: <20260702073354.3641966-2-monish.chunara@oss.qualcomm.com>
On 7/2/26 9:33 AM, Monish Chunara wrote:
> Add support for SD card on Shikra SoC and enable the required pinctrl
> configurations.
>
> Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
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* Re: [PATCH 2/2] phy: qcom-qusb2: fix autoresume handling
From: Konrad Dybcio @ 2026-07-02 12:03 UTC (permalink / raw)
To: Dmitry Baryshkov, Vinod Koul, Neil Armstrong, Kathiravan T,
Baruch Siach, Dmitry Baryshkov, Krishna Kurapati
Cc: linux-arm-msm, linux-phy, linux-kernel
In-Reply-To: <20260702-fix-qusb2-v1-2-b5cf55621524@oss.qualcomm.com>
On 7/2/26 1:40 PM, Dmitry Baryshkov wrote:
> There is a confusion regarding the autoresume bit. Some verions of the
> QUSB2 PHY have it in the TEST1 register, while on the others it is a
> part of the TEST_CTRL register. When adding support for autoresume bit,
> the code attempted to simplify the handling of those registers, putting
> both registers to the TEST1 layout entry. In the end,
> ipq6018_regs_layout ended up correctly definig TEST1 register at 0x98
> (because platforms using that layout didn't use autoresume), while
> msm8996_regs_layout used TEST_CTRL offset (0xb8) for the TEST1
> layout entry.
>
> Update the platform data to specify the register to be used for
> autoresume handling, define both TEST1 and TEST_CTRL registers and merge
> ipq6018_regs_layout and msm8996_regs_layout which become identical
> afterwards.
>
> Fixes: 891a96f65ac3 ("phy: qcom-qusb2: Add support for runtime PM")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
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* Re: [PATCH 1/2] phy: qcom-qusb2: don't unrelated bits if autoresume is not used
From: Konrad Dybcio @ 2026-07-02 12:02 UTC (permalink / raw)
To: Dmitry Baryshkov, Vinod Koul, Neil Armstrong, Kathiravan T,
Baruch Siach, Dmitry Baryshkov, Krishna Kurapati
Cc: linux-arm-msm, linux-phy, linux-kernel
In-Reply-To: <20260702-fix-qusb2-v1-1-b5cf55621524@oss.qualcomm.com>
On 7/2/26 1:40 PM, Dmitry Baryshkov wrote:
> The IPQ6018 and QCS615 platforms don't need to toggle the autoresume
> bit. However the driver ended up toggling a completely unrelated bit
> (BIT 0 in the TEST1 register) instead of skipping the autoresume bit
> programmign at all.
>
> Update those two platforms to specify 0 mask for the autoresume_en and
> skip programming if the mask is 0.
I'd say that we should just use the correct value of BIT(3) for both
and order this patch after the other one
Konrad
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* Re: [PATCH 1/2] phy: qcom-qusb2: don't unrelated bits if autoresume is not used
From: Konrad Dybcio @ 2026-07-02 12:00 UTC (permalink / raw)
To: Dmitry Baryshkov, Vinod Koul, Neil Armstrong, Kathiravan T,
Baruch Siach, Dmitry Baryshkov, Krishna Kurapati
Cc: linux-arm-msm, linux-phy, linux-kernel
In-Reply-To: <20260702-fix-qusb2-v1-1-b5cf55621524@oss.qualcomm.com>
On 7/2/26 1:40 PM, Dmitry Baryshkov wrote:
> The IPQ6018 and QCS615 platforms don't need to toggle the autoresume
> bit.
why?
Konrad
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* [PATCH 2/2] phy: qcom-qusb2: fix autoresume handling
From: Dmitry Baryshkov @ 2026-07-02 11:40 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Kathiravan T, Baruch Siach,
Dmitry Baryshkov, Krishna Kurapati
Cc: linux-arm-msm, linux-phy, linux-kernel
In-Reply-To: <20260702-fix-qusb2-v1-0-b5cf55621524@oss.qualcomm.com>
There is a confusion regarding the autoresume bit. Some verions of the
QUSB2 PHY have it in the TEST1 register, while on the others it is a
part of the TEST_CTRL register. When adding support for autoresume bit,
the code attempted to simplify the handling of those registers, putting
both registers to the TEST1 layout entry. In the end,
ipq6018_regs_layout ended up correctly definig TEST1 register at 0x98
(because platforms using that layout didn't use autoresume), while
msm8996_regs_layout used TEST_CTRL offset (0xb8) for the TEST1
layout entry.
Update the platform data to specify the register to be used for
autoresume handling, define both TEST1 and TEST_CTRL registers and merge
ipq6018_regs_layout and msm8996_regs_layout which become identical
afterwards.
Fixes: 891a96f65ac3 ("phy: qcom-qusb2: Add support for runtime PM")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 38 +++++++++++++++++------------------
1 file changed, 18 insertions(+), 20 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index 1109c480843e..ff3bc8fc2f18 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -131,6 +131,7 @@ enum qusb2phy_reg_layout {
QUSB2PHY_PORT_TUNE5,
QUSB2PHY_PORT_TEST1,
QUSB2PHY_PORT_TEST2,
+ QUSB2PHY_PORT_TEST_CTRL,
QUSB2PHY_PORT_POWERDOWN,
QUSB2PHY_INTR_CTRL,
};
@@ -164,19 +165,6 @@ static const struct qusb2_phy_init_tbl qcs615_init_tbl[] = {
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
};
-static const unsigned int ipq6018_regs_layout[] = {
- [QUSB2PHY_PLL_STATUS] = 0x38,
- [QUSB2PHY_PORT_TUNE1] = 0x80,
- [QUSB2PHY_PORT_TUNE2] = 0x84,
- [QUSB2PHY_PORT_TUNE3] = 0x88,
- [QUSB2PHY_PORT_TUNE4] = 0x8C,
- [QUSB2PHY_PORT_TUNE5] = 0x90,
- [QUSB2PHY_PORT_TEST1] = 0x98,
- [QUSB2PHY_PORT_TEST2] = 0x9C,
- [QUSB2PHY_PORT_POWERDOWN] = 0xB4,
- [QUSB2PHY_INTR_CTRL] = 0xBC,
-};
-
static const unsigned int msm8996_regs_layout[] = {
[QUSB2PHY_PLL_STATUS] = 0x38,
[QUSB2PHY_PORT_TUNE1] = 0x80,
@@ -184,8 +172,9 @@ static const unsigned int msm8996_regs_layout[] = {
[QUSB2PHY_PORT_TUNE3] = 0x88,
[QUSB2PHY_PORT_TUNE4] = 0x8c,
[QUSB2PHY_PORT_TUNE5] = 0x90,
- [QUSB2PHY_PORT_TEST1] = 0xb8,
+ [QUSB2PHY_PORT_TEST1] = 0x98,
[QUSB2PHY_PORT_TEST2] = 0x9c,
+ [QUSB2PHY_PORT_TEST_CTRL] = 0xb8,
[QUSB2PHY_PORT_POWERDOWN] = 0xb4,
[QUSB2PHY_INTR_CTRL] = 0xbc,
};
@@ -294,6 +283,7 @@ struct qusb2_phy_cfg {
unsigned int mask_core_ready;
unsigned int disable_ctrl;
unsigned int autoresume_en;
+ bool autoresume_in_test_ctrl;
/* true if PHY has PLL_TEST register to select clk_scheme */
bool has_pll_test;
@@ -318,6 +308,7 @@ static const struct qusb2_phy_cfg msm8996_phy_cfg = {
.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
.mask_core_ready = PLL_LOCKED,
.autoresume_en = BIT(3),
+ .autoresume_in_test_ctrl = true,
};
static const struct qusb2_phy_cfg msm8998_phy_cfg = {
@@ -336,7 +327,7 @@ static const struct qusb2_phy_cfg msm8998_phy_cfg = {
static const struct qusb2_phy_cfg ipq6018_phy_cfg = {
.tbl = ipq6018_init_tbl,
.tbl_num = ARRAY_SIZE(ipq6018_init_tbl),
- .regs = ipq6018_regs_layout,
+ .regs = msm8996_regs_layout,
.disable_ctrl = POWER_DOWN,
.mask_core_ready = PLL_LOCKED,
@@ -347,7 +338,7 @@ static const struct qusb2_phy_cfg ipq6018_phy_cfg = {
static const struct qusb2_phy_cfg qcs615_phy_cfg = {
.tbl = qcs615_init_tbl,
.tbl_num = ARRAY_SIZE(qcs615_init_tbl),
- .regs = ipq6018_regs_layout,
+ .regs = msm8996_regs_layout,
.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
.mask_core_ready = PLL_LOCKED,
@@ -379,6 +370,7 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = {
.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
.mask_core_ready = PLL_LOCKED,
.autoresume_en = BIT(3),
+ .autoresume_in_test_ctrl = true,
};
static const struct qusb2_phy_cfg sm6115_phy_cfg = {
@@ -391,6 +383,7 @@ static const struct qusb2_phy_cfg sm6115_phy_cfg = {
.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
.mask_core_ready = PLL_LOCKED,
.autoresume_en = BIT(3),
+ .autoresume_in_test_ctrl = true,
};
static const char * const qusb2_phy_vreg_names[] = {
@@ -678,11 +671,16 @@ static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev)
/* enable phy auto-resume only if device is connected on bus */
if (qphy->mode != PHY_MODE_INVALID && cfg->autoresume_en) {
- qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
- cfg->autoresume_en);
+ unsigned int reg;
+
+ if (cfg->autoresume_in_test_ctrl)
+ reg = cfg->regs[QUSB2PHY_PORT_TEST_CTRL];
+ else
+ reg = cfg->regs[QUSB2PHY_PORT_TEST1];
+
+ qusb2_setbits(qphy->base, reg, cfg->autoresume_en);
/* Autoresume bit has to be toggled in order to enable it */
- qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
- cfg->autoresume_en);
+ qusb2_clrbits(qphy->base, reg, cfg->autoresume_en);
}
if (!qphy->has_se_clk_scheme)
--
2.47.3
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* [PATCH 1/2] phy: qcom-qusb2: don't unrelated bits if autoresume is not used
From: Dmitry Baryshkov @ 2026-07-02 11:40 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Kathiravan T, Baruch Siach,
Dmitry Baryshkov, Krishna Kurapati
Cc: linux-arm-msm, linux-phy, linux-kernel
In-Reply-To: <20260702-fix-qusb2-v1-0-b5cf55621524@oss.qualcomm.com>
The IPQ6018 and QCS615 platforms don't need to toggle the autoresume
bit. However the driver ended up toggling a completely unrelated bit
(BIT 0 in the TEST1 register) instead of skipping the autoresume bit
programmign at all.
Update those two platforms to specify 0 mask for the autoresume_en and
skip programming if the mask is 0.
Fixes: 2cfbe6765b7a ("phy: qcom-qusb2: add QUSB2 support for IPQ6018")
Fixes: 8adbf20e0502 ("phy: qcom-qusb2: Add support for QCS615")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index eb93015be841..1109c480843e 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -341,7 +341,7 @@ static const struct qusb2_phy_cfg ipq6018_phy_cfg = {
.disable_ctrl = POWER_DOWN,
.mask_core_ready = PLL_LOCKED,
/* autoresume not used */
- .autoresume_en = BIT(0),
+ .autoresume_en = 0,
};
static const struct qusb2_phy_cfg qcs615_phy_cfg = {
@@ -352,7 +352,7 @@ static const struct qusb2_phy_cfg qcs615_phy_cfg = {
.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
.mask_core_ready = PLL_LOCKED,
/* autoresume not used */
- .autoresume_en = BIT(0),
+ .autoresume_en = 0,
};
static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
@@ -677,7 +677,7 @@ static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev)
}
/* enable phy auto-resume only if device is connected on bus */
- if (qphy->mode != PHY_MODE_INVALID) {
+ if (qphy->mode != PHY_MODE_INVALID && cfg->autoresume_en) {
qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
cfg->autoresume_en);
/* Autoresume bit has to be toggled in order to enable it */
--
2.47.3
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* [PATCH 0/2] phy: qcom-qusb2: sort out register layouts
From: Dmitry Baryshkov @ 2026-07-02 11:40 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Kathiravan T, Baruch Siach,
Dmitry Baryshkov, Krishna Kurapati
Cc: linux-arm-msm, linux-phy, linux-kernel
IPQ6018 and MSM8996 use the same register layout, however for historical
reasons ipq6018_regs_layout ended up correctly definig TEST1 register at
0x98 (because platforms using that layout didn't use autoresume), while
msm8996_regs_layout used TEST_CTRL offset (0xb8) for the TEST1 layout
entry. Fix handling of the autoresume register and definitions of those
regs layouts.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
Dmitry Baryshkov (2):
phy: qcom-qusb2: don't unrelated bits if autoresume is not used
phy: qcom-qusb2: fix autoresume handling
drivers/phy/qualcomm/phy-qcom-qusb2.c | 44 +++++++++++++++++------------------
1 file changed, 21 insertions(+), 23 deletions(-)
---
base-commit: be5c93fa674f0fc3c8f359c2143abce6bbb422e6
change-id: 20260702-fix-qusb2-3600a65bfcae
Best regards,
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* Re: [PATCH v10 5/5] phy: airoha: Add support for Airoha AN7581 USB PHY
From: sashiko-bot @ 2026-07-02 10:26 UTC (permalink / raw)
To: Christian Marangi
Cc: conor+dt, linux-phy, robh, devicetree, vkoul, neil.armstrong,
olteanv
In-Reply-To: <20260702093812.15918-6-ansuelsmth@gmail.com>
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Incorrect usage of `regmap_set_bits` with `FIELD_PREP` corrupts multi-bit register field
- [Medium] Missing PHY Lifecycle Management for SerDes PHY
- [Medium] Computed slew rate calibration value is not clamped, risking silent wraparound
--
Note: The format of this review has been altered to use free-form summaries
instead of inline diff quoting due to strict recitation restrictions.
commit 4d1e2d05354e7c1aad9463afa3c9c7ffd853f726
Author: Christian Marangi <ansuelsmth@gmail.com>
phy: airoha: Add support for Airoha AN7581 USB PHY
This commit adds support for the Airoha AN7581 USB PHY driver, which supports
up to two USB ports. USB 2.0 is always supported, while USB 3.0 requires the
SerDes port to be configured. It also introduces USB 2.0 slew rate calibration
using a mandatory monitor clock.
[Severity: Medium]
In an7581_usb_phy_init() and an7581_usb_phy_power_on(), the driver sets the
mode of the SerDes PHY but does not call phy_init(), phy_power_on(),
phy_power_off(), or phy_exit() for the priv->serdes_phy. Is it safe to omit
these generic PHY lifecycle calls?
Even if the current SerDes PHY driver for this SoC only implements the
set_mode callback, omitting these lifecycle management functions might cause
failures if the SerDes PHY driver is updated to require hardware
initialization, or if this driver is used on a SoC variant where the
underlying SerDes PHY requires power management to function.
[Severity: High]
In an7581_usb_phy_u3_init(), regmap_set_bits() is used alongside FIELD_PREP()
to write a 16-bit value into the AIROHA_USB_PHY_SSUSB_XTAL_TOP_RESERVE
register. Does this unintentionally leave old bits set in the multi-bit field?
Since regmap_set_bits() performs a bitwise OR and does not clear previously
set bits like regmap_update_bits() does, any pre-existing overlapping bits
from hardware defaults or bootloader initialization will remain set. This
could result in a corrupted XTAL/PLL configuration and cause an unstable
USB 3.0 clock or probe failures.
[Severity: Medium]
In an7581_usb_phy_u2_slew_rate_calibration(), the dynamically computed srctrl
value is passed directly to FIELD_PREP() for the 3-bit
AIROHA_USB_PHY_USB20_HSTX_SRCTRL field. Could this silently wrap around if
fm_out is unexpectedly small?
If a transient clock issue causes fm_out to drop below expected values, the
computed srctrl can exceed the maximum value of 7. Because FIELD_PREP()
masks the value, an srctrl of 8 would silently wrap around to 0. This would
convert what should be a maximum slew rate calibration into the minimum
calibration, risking severe USB 2.0 signal degradation. Should the srctrl
value be clamped before insertion?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260702093812.15918-1-ansuelsmth@gmail.com?part=5
--
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^ permalink raw reply
* Re: [PATCH v10 4/5] phy: move and rename Airoha PCIe PHY driver to dedicated directory
From: sashiko-bot @ 2026-07-02 10:14 UTC (permalink / raw)
To: Christian Marangi
Cc: linux-phy, robh, conor+dt, olteanv, devicetree, vkoul,
neil.armstrong
In-Reply-To: <20260702093812.15918-5-ansuelsmth@gmail.com>
Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [Low] The driver Kconfig symbol, file names, and platform driver name are incorrectly renamed using the 'AN7581' prefix instead of 'EN7581', creating a mismatch with the hardware name and device tree bindings.
- [Low] The include guard in `phy-an7581-pcie-regs.h` was not updated after the file was renamed.
- [Low] Incorrect SPDX-License-Identifier comment style for a C header file.
- [Low] The newly added `Kconfig` and `Makefile` for the `drivers/phy/airoha/` directory are missing from the `MAINTAINERS` file.
--
commit 6b7c73648fcebc4627d82c8ab33128623756a453
Author: Christian Marangi <ansuelsmth@gmail.com>
phy: move and rename Airoha PCIe PHY driver to dedicated directory
This commit moves the PCIe PHY driver for the Airoha AN7581 SoC to a dedicated
directory to keep the generic PHY directory tidy. It also renames the driver
and files to include the specific SoC name in preparation for adding AN7583
support, and updates the Kconfig symbol accordingly.
> To keep the generic PHY directory tidy, move the PCIe PHY driver for
> Airoha AN7581 SoC to a dedicated directory.
>
> Also rename the driver and add the relevant SoC name to the .c and .h
> file in preparation for support of PCIe and USB PHY driver for Airoha
> AN7583 SoC
[Severity: Low]
This isn't a bug, but there might be a typo in the commit message. Is the
SoC name EN7581 instead of AN7581, given the existing device tree bindings
mention en7581?
> diff --git a/MAINTAINERS b/MAINTAINERS
> index cb7836a27b177..bbfaca572118c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -765,8 +765,8 @@ M: Lorenzo Bianconi <lorenzo@kernel.org>
> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> S: Maintained
> F: Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml
> -F: drivers/phy/phy-airoha-pcie-regs.h
> -F: drivers/phy/phy-airoha-pcie.c
> +F: drivers/phy/airoha/phy-an7581-pcie-regs.h
> +F: drivers/phy/airoha/phy-an7581-pcie.c
[Severity: Low]
By explicitly listing only the source files, the newly added Kconfig and
Makefile in the drivers/phy/airoha/ directory are left without a maintainer
mapping. Would it be better to use a directory wildcard like
F: drivers/phy/airoha/ to include the new build files?
> diff --git a/drivers/phy/airoha/Kconfig b/drivers/phy/airoha/Kconfig
> new file mode 100644
> index 0000000000000..9a1b625a77012
> --- /dev/null
> +++ b/drivers/phy/airoha/Kconfig
> @@ -0,0 +1,13 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +#
> +# Phy drivers for Airoha devices
> +#
> +config PHY_AIROHA_AN7581_PCIE
> + tristate "Airoha AN7581 PCIe-PHY Driver"
[Severity: Low]
Does this Kconfig symbol and prompt incorrectly use the AN7581 prefix
despite the SoC hardware and device tree binding being named EN7581?
> diff --git a/drivers/phy/phy-airoha-pcie-regs.h b/drivers/phy/airoha/phy-an7581-pcie-regs.h
> similarity index 99%
> rename from drivers/phy/phy-airoha-pcie-regs.h
> rename to drivers/phy/airoha/phy-an7581-pcie-regs.h
> index 58572c7937223..b938a7b468fee 100644
> --- a/drivers/phy/phy-airoha-pcie-regs.h
> +++ b/drivers/phy/airoha/phy-an7581-pcie-regs.h
> @@ -1,4 +1,4 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> +// SPDX-License-Identifier: GPL-2.0-only
[Severity: Low]
Does this change to a C++ style line comment violate the kernel's SPDX
license identifier rules for C header files, which require the /* ... */
block comment style?
[Severity: Low]
Also, since this file was renamed, does the include guard further down in the
file (currently #ifndef _PHY_AIROHA_PCIE_H) need to be updated to match the
new filename?
> diff --git a/drivers/phy/phy-airoha-pcie.c b/drivers/phy/airoha/phy-an7581-pcie.c
> similarity index 99%
> rename from drivers/phy/phy-airoha-pcie.c
> rename to drivers/phy/airoha/phy-an7581-pcie.c
> index 56e9ade8a9fd3..81ddf0e7638b7 100644
> --- a/drivers/phy/phy-airoha-pcie.c
> +++ b/drivers/phy/airoha/phy-an7581-pcie.c
[ ... ]
> @@ -1279,12 +1279,12 @@ MODULE_DEVICE_TABLE(of, airoha_pcie_phy_of_match);
> static struct platform_driver airoha_pcie_phy_driver = {
> .probe = airoha_pcie_phy_probe,
> .driver = {
> - .name = "airoha-pcie-phy",
> + .name = "airoha-an7581-pcie-phy",
[Severity: Low]
Does this platform driver name incorrectly use the misspelled an7581 prefix
instead of en7581?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260702093812.15918-1-ansuelsmth@gmail.com?part=4
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* Re: [PATCH v10 2/5] dt-bindings: phy: Add documentation for Airoha AN7581 USB PHY
From: sashiko-bot @ 2026-07-02 9:54 UTC (permalink / raw)
To: Christian Marangi
Cc: robh, vkoul, olteanv, neil.armstrong, conor+dt, devicetree,
linux-phy
In-Reply-To: <20260702093812.15918-3-ansuelsmth@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Encoding fixed internal SoC routing in the device tree via the `airoha,usb2-monitor-clk-sel` property.
--
commit 82d75d6a8695c967604982f45c3db95efe45a784
Author: Christian Marangi <ansuelsmth@gmail.com>
dt-bindings: phy: Add documentation for Airoha AN7581 USB PHY
This commit adds device tree binding documentation for the Airoha AN7581
USB PHY. It details properties for configuring the always-supported USB 2.0
mode and the optional USB 3.0 mode, including slew rate calibration and
Serdes configuration.
> diff --git a/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml
> new file mode 100644
> index 0000000000000..f42e3d49a61fd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml
> @@ -0,0 +1,62 @@
[ ... ]
> + reg:
> + maxItems: 1
> +
> + airoha,usb2-monitor-clk-sel:
> + description: Describe what oscillator across the available 4
> + should be selected for USB 2.0 Slew Rate calibration.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2, 3]
[Severity: Low]
Since the commit message mentions that each port has only one of the 4 monitor
clocks actually connected in HW, does this property encode a fixed internal
SoC routing rather than a board-specific configuration?
Could the driver deduce the correct clock selection internally (for example,
from the port's register address) instead of requiring a DT property for a
fixed SoC hardware characteristic?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260702093812.15918-1-ansuelsmth@gmail.com?part=2
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* Re: [PATCH v10 1/5] dt-bindings: clock: airoha: Add PHY binding for Serdes port
From: sashiko-bot @ 2026-07-02 9:48 UTC (permalink / raw)
To: Christian Marangi
Cc: linux-phy, conor+dt, robh, vkoul, devicetree, neil.armstrong,
olteanv
In-Reply-To: <20260702093812.15918-2-ansuelsmth@gmail.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The `#phy-cells` property is implicitly allowed for the `econet,en751221-scu` compatible, contradicting the commit message which states it is exclusive to the Airoha AN7581 SoC.
- [Medium] The `airoha,en7581-scu` variant gains a new PHY provider capability, but `#phy-cells` is not added to its required properties, and the schema example is not updated.
--
commit 6d3a613072b0007e76d5846629212f75c8dfc300
Author: Christian Marangi <ansuelsmth@gmail.com>
dt-bindings: clock: airoha: Add PHY binding for Serdes port
This commit adds the #phy-cells property for Serdes port selection,
specifying that it is currently supported only for the Airoha AN7581 SoC.
> diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
> index eb24a5687639e..913ddc16182b8 100644
> --- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
> +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
[ ... ]
> @@ -65,6 +72,8 @@ allOf:
> reg:
> minItems: 2
>
> + '#phy-cells': false
> +
> - if:
> properties:
> compatible:
[Severity: Medium]
The commit message states that the #phy-cells property is currently supported
only for the Airoha AN7581 SoC. However, looking at the allOf conditional
block:
- if:
properties:
compatible:
enum:
- airoha,en7581-scu
- econet,en751221-scu
Since econet,en751221-scu shares this block and does not explicitly have
'#phy-cells': false like the previous block, does this implicitly allow the
property for it and contradict the commit message?
[Severity: Medium]
Additionally, since the airoha,en7581-scu variant gains a new PHY provider
capability, should #phy-cells be added to its required properties list?
The example for airoha,en7581-scu in the same file is also missing the
property:
scuclk: clock-controller@1fb00000 {
compatible = "airoha,en7581-scu";
reg = <0x0 0x1fb00000 0x0 0x970>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Would it be better to update the schema to mandate the property and update
the example to include #phy-cells = <1> so incomplete device tree nodes do
not silently pass schema validation?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260702093812.15918-1-ansuelsmth@gmail.com?part=1
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* [PATCH v10 5/5] phy: airoha: Add support for Airoha AN7581 USB PHY
From: Christian Marangi @ 2026-07-02 9:38 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Christian Marangi, Vinod Koul,
Neil Armstrong, Lorenzo Bianconi, Felix Fietkau, linux-clk,
devicetree, linux-kernel, linux-arm-kernel, linux-phy
In-Reply-To: <20260702093812.15918-1-ansuelsmth@gmail.com>
Add support for Airoha AN7581 USB PHY driver. AN7581 supports up to 2
USB port with USB 2.0 mode always supported and USB 3.0 mode available
only if the Serdes port is correctly configured for USB 3.0.
If the USB 3.0 mode is not configured, the modes needs to be also
disabled in the xHCI node or the driver will report unsable clock and
fail probe.
For USB 2.0 Slew Rate calibration, airoha,usb2-monitor-clk-sel is
mandatory and is used to select the monitor clock for calibration.
Normally it's 1 for USB port 1 and 2 for USB port 2.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
MAINTAINERS | 1 +
drivers/phy/airoha/Kconfig | 11 +
drivers/phy/airoha/Makefile | 1 +
drivers/phy/airoha/phy-an7581-usb.c | 559 ++++++++++++++++++++++++++++
4 files changed, 572 insertions(+)
create mode 100644 drivers/phy/airoha/phy-an7581-usb.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 952653034c4c..844f676254ac 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -782,6 +782,7 @@ M: Christian Marangi <ansuelsmth@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml
+F: drivers/phy/airoha/phy-an7581-usb.c
AIRSPY MEDIA DRIVER
L: linux-media@vger.kernel.org
diff --git a/drivers/phy/airoha/Kconfig b/drivers/phy/airoha/Kconfig
index 9a1b625a7701..634448ee39b5 100644
--- a/drivers/phy/airoha/Kconfig
+++ b/drivers/phy/airoha/Kconfig
@@ -11,3 +11,14 @@ config PHY_AIROHA_AN7581_PCIE
Say Y here to add support for Airoha AN7581 PCIe PHY driver.
This driver create the basic PHY instance and provides initialize
callback for PCIe GEN3 port.
+
+config PHY_AIROHA_AN7581_USB
+ tristate "Airoha AN7581 USB PHY Driver"
+ depends on ARCH_AIROHA || COMPILE_TEST
+ depends on OF
+ select GENERIC_PHY
+ select REGMAP_MMIO
+ help
+ Say 'Y' here to add support for Airoha AN7581 USB PHY driver.
+ This driver create the basic PHY instance and provides initialize
+ callback for USB port.
diff --git a/drivers/phy/airoha/Makefile b/drivers/phy/airoha/Makefile
index 912f3e11a061..944bf842deba 100644
--- a/drivers/phy/airoha/Makefile
+++ b/drivers/phy/airoha/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_PHY_AIROHA_AN7581_PCIE) += phy-an7581-pcie.o
+obj-$(CONFIG_PHY_AIROHA_AN7581_USB) += phy-an7581-usb.o
diff --git a/drivers/phy/airoha/phy-an7581-usb.c b/drivers/phy/airoha/phy-an7581-usb.c
new file mode 100644
index 000000000000..92c5e5c2fbf3
--- /dev/null
+++ b/drivers/phy/airoha/phy-an7581-usb.c
@@ -0,0 +1,559 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/soc/airoha,scu-ssr.h>
+#include <linux/bitfield.h>
+#include <linux/math.h>
+#include <linux/module.h>
+#include <linux/mfd/syscon.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+/* U2PHY */
+#define AIROHA_USB_PHY_FMCR0 0x100
+#define AIROHA_USB_PHY_MONCLK_SEL GENMASK(27, 26)
+#define AIROHA_USB_PHY_MONCLK_SEL0 FIELD_PREP_CONST(AIROHA_USB_PHY_MONCLK_SEL, 0x0)
+#define AIROHA_USB_PHY_MONCLK_SEL1 FIELD_PREP_CONST(AIROHA_USB_PHY_MONCLK_SEL, 0x1)
+#define AIROHA_USB_PHY_MONCLK_SEL2 FIELD_PREP_CONST(AIROHA_USB_PHY_MONCLK_SEL, 0x2)
+#define AIROHA_USB_PHY_MONCLK_SEL3 FIELD_PREP_CONST(AIROHA_USB_PHY_MONCLK_SEL, 0x3)
+#define AIROHA_USB_PHY_FREQDET_EN BIT(24)
+#define AIROHA_USB_PHY_CYCLECNT GENMASK(23, 0)
+#define AIROHA_USB_PHY_FMMONR0 0x10c
+#define AIROHA_USB_PHY_USB_FM_OUT GENMASK(31, 0)
+#define AIROHA_USB_PHY_FMMONR1 0x110
+#define AIROHA_USB_PHY_FRCK_EN BIT(8)
+
+#define AIROHA_USB_PHY_USBPHYACR4 0x310
+#define AIROHA_USB_PHY_USB20_FS_CR GENMASK(10, 8)
+#define AIROHA_USB_PHY_USB20_FS_CR_MAX FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_FS_CR, 0x0)
+#define AIROHA_USB_PHY_USB20_FS_CR_NORMAL FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_FS_CR, 0x2)
+#define AIROHA_USB_PHY_USB20_FS_CR_SMALLER FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_FS_CR, 0x4)
+#define AIROHA_USB_PHY_USB20_FS_CR_MIN FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_FS_CR, 0x6)
+#define AIROHA_USB_PHY_USB20_FS_SR GENMASK(2, 0)
+#define AIROHA_USB_PHY_USB20_FS_SR_MAX FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_FS_SR, 0x0)
+#define AIROHA_USB_PHY_USB20_FS_SR_NORMAL FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_FS_SR, 0x2)
+#define AIROHA_USB_PHY_USB20_FS_SR_SMALLER FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_FS_SR, 0x4)
+#define AIROHA_USB_PHY_USB20_FS_SR_MIN FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_FS_SR, 0x6)
+#define AIROHA_USB_PHY_USBPHYACR5 0x314
+#define AIROHA_USB_PHY_USB20_HSTX_SRCAL_EN BIT(15)
+#define AIROHA_USB_PHY_USB20_HSTX_SRCTRL GENMASK(14, 12)
+#define AIROHA_USB_PHY_USBPHYACR6 0x318
+#define AIROHA_USB_PHY_USB20_BC11_SW_EN BIT(23)
+#define AIROHA_USB_PHY_USB20_DISCTH GENMASK(7, 4)
+#define AIROHA_USB_PHY_USB20_DISCTH_400 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x0)
+#define AIROHA_USB_PHY_USB20_DISCTH_420 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x1)
+#define AIROHA_USB_PHY_USB20_DISCTH_440 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x2)
+#define AIROHA_USB_PHY_USB20_DISCTH_460 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x3)
+#define AIROHA_USB_PHY_USB20_DISCTH_480 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x4)
+#define AIROHA_USB_PHY_USB20_DISCTH_500 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x5)
+#define AIROHA_USB_PHY_USB20_DISCTH_520 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x6)
+#define AIROHA_USB_PHY_USB20_DISCTH_540 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x7)
+#define AIROHA_USB_PHY_USB20_DISCTH_560 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x8)
+#define AIROHA_USB_PHY_USB20_DISCTH_580 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0x9)
+#define AIROHA_USB_PHY_USB20_DISCTH_600 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0xa)
+#define AIROHA_USB_PHY_USB20_DISCTH_620 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0xb)
+#define AIROHA_USB_PHY_USB20_DISCTH_640 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0xc)
+#define AIROHA_USB_PHY_USB20_DISCTH_660 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0xd)
+#define AIROHA_USB_PHY_USB20_DISCTH_680 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0xe)
+#define AIROHA_USB_PHY_USB20_DISCTH_700 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_DISCTH, 0xf)
+#define AIROHA_USB_PHY_USB20_SQTH GENMASK(3, 0)
+#define AIROHA_USB_PHY_USB20_SQTH_85 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x0)
+#define AIROHA_USB_PHY_USB20_SQTH_90 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x1)
+#define AIROHA_USB_PHY_USB20_SQTH_95 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x2)
+#define AIROHA_USB_PHY_USB20_SQTH_100 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x3)
+#define AIROHA_USB_PHY_USB20_SQTH_105 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x4)
+#define AIROHA_USB_PHY_USB20_SQTH_110 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x5)
+#define AIROHA_USB_PHY_USB20_SQTH_115 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x6)
+#define AIROHA_USB_PHY_USB20_SQTH_120 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x7)
+#define AIROHA_USB_PHY_USB20_SQTH_125 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x8)
+#define AIROHA_USB_PHY_USB20_SQTH_130 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0x9)
+#define AIROHA_USB_PHY_USB20_SQTH_135 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0xa)
+#define AIROHA_USB_PHY_USB20_SQTH_140 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0xb)
+#define AIROHA_USB_PHY_USB20_SQTH_145 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0xc)
+#define AIROHA_USB_PHY_USB20_SQTH_150 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0xd)
+#define AIROHA_USB_PHY_USB20_SQTH_155 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0xe)
+#define AIROHA_USB_PHY_USB20_SQTH_160 FIELD_PREP_CONST(AIROHA_USB_PHY_USB20_SQTH, 0xf)
+
+#define AIROHA_USB_PHY_U2PHYDTM1 0x36c
+#define AIROHA_USB_PHY_FORCE_IDDIG BIT(9)
+#define AIROHA_USB_PHY_IDDIG BIT(1)
+
+#define AIROHA_USB_PHY_GPIO_CTLD 0x80c
+#define AIROHA_USB_PHY_C60802_GPIO_CTLD GENMASK(31, 0)
+#define AIROHA_USB_PHY_SSUSB_IP_SW_RST BIT(31)
+#define AIROHA_USB_PHY_MCU_BUS_CK_GATE_EN BIT(30)
+#define AIROHA_USB_PHY_FORCE_SSUSB_IP_SW_RST BIT(29)
+#define AIROHA_USB_PHY_SSUSB_SW_RST BIT(28)
+
+#define AIROHA_USB_PHY_U3_PHYA_REG0 0xb00
+#define AIROHA_USB_PHY_SSUSB_BG_DIV GENMASK(29, 28)
+#define AIROHA_USB_PHY_SSUSB_BG_DIV_2 FIELD_PREP_CONST(AIROHA_USB_PHY_SSUSB_BG_DIV, 0x0)
+#define AIROHA_USB_PHY_SSUSB_BG_DIV_4 FIELD_PREP_CONST(AIROHA_USB_PHY_SSUSB_BG_DIV, 0x1)
+#define AIROHA_USB_PHY_SSUSB_BG_DIV_8 FIELD_PREP_CONST(AIROHA_USB_PHY_SSUSB_BG_DIV, 0x2)
+#define AIROHA_USB_PHY_SSUSB_BG_DIV_16 FIELD_PREP_CONST(AIROHA_USB_PHY_SSUSB_BG_DIV, 0x3)
+#define AIROHA_USB_PHY_U3_PHYA_REG1 0xb04
+#define AIROHA_USB_PHY_SSUSB_XTAL_TOP_RESERVE GENMASK(25, 10)
+#define AIROHA_USB_PHY_U3_PHYA_REG6 0xb18
+#define AIROHA_USB_PHY_SSUSB_CDR_RESERVE GENMASK(31, 24)
+#define AIROHA_USB_PHY_U3_PHYA_REG8 0xb20
+#define AIROHA_USB_PHY_SSUSB_CDR_RST_DLY GENMASK(7, 6)
+#define AIROHA_USB_PHY_SSUSB_CDR_RST_DLY_32 FIELD_PREP_CONST(AIROHA_USB_PHY_SSUSB_CDR_RST_DLY, 0x0)
+#define AIROHA_USB_PHY_SSUSB_CDR_RST_DLY_64 FIELD_PREP_CONST(AIROHA_USB_PHY_SSUSB_CDR_RST_DLY, 0x1)
+#define AIROHA_USB_PHY_SSUSB_CDR_RST_DLY_128 FIELD_PREP_CONST(AIROHA_USB_PHY_SSUSB_CDR_RST_DLY, 0x2)
+#define AIROHA_USB_PHY_SSUSB_CDR_RST_DLY_216 FIELD_PREP_CONST(AIROHA_USB_PHY_SSUSB_CDR_RST_DLY, 0x3)
+
+#define AIROHA_USB_PHY_U3_PHYA_DA_REG19 0xc38
+#define AIROHA_USB_PHY_SSUSB_PLL_SSC_DELTA1_U3 GENMASK(15, 0)
+
+#define AIROHA_USB_PHY_U2_FM_DET_CYCLE_CNT 1024
+#define AIROHA_USB_PHY_REF_CK 20
+#define AIROHA_USB_PHY_U2_SR_COEF 28
+#define AIROHA_USB_PHY_U2_SR_COEF_DIVISOR 1000
+
+#define AIROHA_USB_PHY_DEFAULT_SR_CALIBRATION 0x5
+#define AIROHA_USB_PHY_FREQDET_SLEEP 1000 /* 1ms */
+#define AIROHA_USB_PHY_FREQDET_TIMEOUT (AIROHA_USB_PHY_FREQDET_SLEEP * 10)
+
+struct an7581_usb_phy_instance {
+ struct phy *phy;
+ u32 type;
+};
+
+enum an7581_usb_phy_instance_type {
+ AIROHA_PHY_USB2,
+ AIROHA_PHY_USB3,
+
+ AIROHA_PHY_USB_MAX,
+};
+
+struct an7581_usb_phy_priv {
+ struct device *dev;
+ struct regmap *regmap;
+
+ unsigned int monclk_sel;
+
+ struct phy *serdes_phy;
+ struct an7581_usb_phy_instance *phys[AIROHA_PHY_USB_MAX];
+};
+
+static void an7581_usb_phy_u2_slew_rate_calibration(struct an7581_usb_phy_priv *priv)
+{
+ u32 fm_out = 0;
+ u32 srctrl;
+
+ /* Enable HS TX SR calibration */
+ regmap_set_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR5,
+ AIROHA_USB_PHY_USB20_HSTX_SRCAL_EN);
+
+ usleep_range(1000, 1500);
+
+ /* Enable Free run clock */
+ regmap_set_bits(priv->regmap, AIROHA_USB_PHY_FMMONR1,
+ AIROHA_USB_PHY_FRCK_EN);
+
+ /* Select Monitor Clock */
+ regmap_update_bits(priv->regmap, AIROHA_USB_PHY_FMCR0,
+ AIROHA_USB_PHY_MONCLK_SEL,
+ FIELD_PREP(AIROHA_USB_PHY_MONCLK_SEL,
+ priv->monclk_sel));
+
+ /* Set cyclecnt */
+ regmap_update_bits(priv->regmap, AIROHA_USB_PHY_FMCR0,
+ AIROHA_USB_PHY_CYCLECNT,
+ FIELD_PREP(AIROHA_USB_PHY_CYCLECNT,
+ AIROHA_USB_PHY_U2_FM_DET_CYCLE_CNT));
+
+ /* Enable Frequency meter */
+ regmap_set_bits(priv->regmap, AIROHA_USB_PHY_FMCR0,
+ AIROHA_USB_PHY_FREQDET_EN);
+
+ /* Timeout can happen and we will apply workaround at the end */
+ regmap_read_poll_timeout(priv->regmap, AIROHA_USB_PHY_FMMONR0, fm_out,
+ fm_out, AIROHA_USB_PHY_FREQDET_SLEEP,
+ AIROHA_USB_PHY_FREQDET_TIMEOUT);
+
+ /* Disable Frequency meter */
+ regmap_clear_bits(priv->regmap, AIROHA_USB_PHY_FMCR0,
+ AIROHA_USB_PHY_FREQDET_EN);
+
+ /* Disable Free run clock */
+ regmap_clear_bits(priv->regmap, AIROHA_USB_PHY_FMMONR1,
+ AIROHA_USB_PHY_FRCK_EN);
+
+ /* Disable HS TX SR calibration */
+ regmap_clear_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR5,
+ AIROHA_USB_PHY_USB20_HSTX_SRCAL_EN);
+
+ usleep_range(1000, 1500);
+
+ /* Frequency was not detected, use default SR calibration value */
+ if (!fm_out) {
+ srctrl = AIROHA_USB_PHY_DEFAULT_SR_CALIBRATION;
+ dev_err(priv->dev, "Frequency not detected, using default SR calibration.\n");
+ } else {
+ /* (1024 / FM_OUT) * REF_CK * U2_SR_COEF (round to the nearest digits) */
+ srctrl = AIROHA_USB_PHY_REF_CK * AIROHA_USB_PHY_U2_SR_COEF;
+ srctrl = (srctrl * AIROHA_USB_PHY_U2_FM_DET_CYCLE_CNT) / fm_out;
+ srctrl = DIV_ROUND_CLOSEST(srctrl, AIROHA_USB_PHY_U2_SR_COEF_DIVISOR);
+ dev_dbg(priv->dev, "SR calibration applied: %x\n", srctrl);
+ }
+
+ regmap_update_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR5,
+ AIROHA_USB_PHY_USB20_HSTX_SRCTRL,
+ FIELD_PREP(AIROHA_USB_PHY_USB20_HSTX_SRCTRL, srctrl));
+}
+
+static void an7581_usb_phy_u2_init(struct an7581_usb_phy_priv *priv)
+{
+ regmap_update_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR4,
+ AIROHA_USB_PHY_USB20_FS_CR,
+ AIROHA_USB_PHY_USB20_FS_CR_MIN);
+
+ regmap_update_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR4,
+ AIROHA_USB_PHY_USB20_FS_SR,
+ AIROHA_USB_PHY_USB20_FS_SR_NORMAL);
+
+ /* FIXME: evaluate if needed */
+ regmap_update_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR6,
+ AIROHA_USB_PHY_USB20_SQTH,
+ AIROHA_USB_PHY_USB20_SQTH_130);
+
+ regmap_update_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR6,
+ AIROHA_USB_PHY_USB20_DISCTH,
+ AIROHA_USB_PHY_USB20_DISCTH_600);
+
+ /* Enable the USB port and then disable after calibration */
+ regmap_clear_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR6,
+ AIROHA_USB_PHY_USB20_BC11_SW_EN);
+
+ an7581_usb_phy_u2_slew_rate_calibration(priv);
+
+ regmap_set_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR6,
+ AIROHA_USB_PHY_USB20_BC11_SW_EN);
+
+ usleep_range(1000, 1500);
+}
+
+/*
+ * USB 3.0 mode can only work if USB serdes is correctly set.
+ * This is validated in xLate function.
+ */
+static void an7581_usb_phy_u3_init(struct an7581_usb_phy_priv *priv)
+{
+ regmap_update_bits(priv->regmap, AIROHA_USB_PHY_U3_PHYA_REG8,
+ AIROHA_USB_PHY_SSUSB_CDR_RST_DLY,
+ AIROHA_USB_PHY_SSUSB_CDR_RST_DLY_32);
+
+ regmap_update_bits(priv->regmap, AIROHA_USB_PHY_U3_PHYA_REG6,
+ AIROHA_USB_PHY_SSUSB_CDR_RESERVE,
+ FIELD_PREP(AIROHA_USB_PHY_SSUSB_CDR_RESERVE, 0xe));
+
+ regmap_update_bits(priv->regmap, AIROHA_USB_PHY_U3_PHYA_REG0,
+ AIROHA_USB_PHY_SSUSB_BG_DIV,
+ AIROHA_USB_PHY_SSUSB_BG_DIV_4);
+
+ regmap_set_bits(priv->regmap, AIROHA_USB_PHY_U3_PHYA_REG1,
+ FIELD_PREP(AIROHA_USB_PHY_SSUSB_XTAL_TOP_RESERVE, 0x600));
+
+ regmap_update_bits(priv->regmap, AIROHA_USB_PHY_U3_PHYA_DA_REG19,
+ AIROHA_USB_PHY_SSUSB_PLL_SSC_DELTA1_U3,
+ FIELD_PREP(AIROHA_USB_PHY_SSUSB_PLL_SSC_DELTA1_U3, 0x43));
+}
+
+static int an7581_usb_phy_init(struct phy *phy)
+{
+ struct an7581_usb_phy_instance *instance = phy_get_drvdata(phy);
+ struct an7581_usb_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
+ int ret;
+
+ switch (instance->type) {
+ case PHY_TYPE_USB2:
+ an7581_usb_phy_u2_init(priv);
+ break;
+ case PHY_TYPE_USB3:
+ ret = phy_set_mode(priv->serdes_phy, PHY_MODE_USB_DEVICE_SS);
+ if (ret)
+ return ret;
+
+ an7581_usb_phy_u3_init(priv);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int an7581_usb_phy_u2_power_on(struct an7581_usb_phy_priv *priv)
+{
+ regmap_clear_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR6,
+ AIROHA_USB_PHY_USB20_BC11_SW_EN);
+
+ usleep_range(1000, 1500);
+
+ return 0;
+}
+
+static int an7581_usb_phy_u3_power_on(struct an7581_usb_phy_priv *priv)
+{
+ regmap_clear_bits(priv->regmap, AIROHA_USB_PHY_GPIO_CTLD,
+ AIROHA_USB_PHY_SSUSB_IP_SW_RST |
+ AIROHA_USB_PHY_MCU_BUS_CK_GATE_EN |
+ AIROHA_USB_PHY_FORCE_SSUSB_IP_SW_RST |
+ AIROHA_USB_PHY_SSUSB_SW_RST);
+
+ usleep_range(1000, 1500);
+
+ return 0;
+}
+
+static int an7581_usb_phy_power_on(struct phy *phy)
+{
+ struct an7581_usb_phy_instance *instance = phy_get_drvdata(phy);
+ struct an7581_usb_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
+
+ switch (instance->type) {
+ case PHY_TYPE_USB2:
+ an7581_usb_phy_u2_power_on(priv);
+ break;
+ case PHY_TYPE_USB3:
+ an7581_usb_phy_u3_power_on(priv);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int an7581_usb_phy_u2_power_off(struct an7581_usb_phy_priv *priv)
+{
+ regmap_set_bits(priv->regmap, AIROHA_USB_PHY_USBPHYACR6,
+ AIROHA_USB_PHY_USB20_BC11_SW_EN);
+
+ usleep_range(1000, 1500);
+
+ return 0;
+}
+
+static int an7581_usb_phy_u3_power_off(struct an7581_usb_phy_priv *priv)
+{
+ regmap_set_bits(priv->regmap, AIROHA_USB_PHY_GPIO_CTLD,
+ AIROHA_USB_PHY_SSUSB_IP_SW_RST |
+ AIROHA_USB_PHY_FORCE_SSUSB_IP_SW_RST);
+
+ usleep_range(1000, 1500);
+
+ return 0;
+}
+
+static int an7581_usb_phy_power_off(struct phy *phy)
+{
+ struct an7581_usb_phy_instance *instance = phy_get_drvdata(phy);
+ struct an7581_usb_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
+
+ switch (instance->type) {
+ case PHY_TYPE_USB2:
+ an7581_usb_phy_u2_power_off(priv);
+ break;
+ case PHY_TYPE_USB3:
+ an7581_usb_phy_u3_power_off(priv);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int an7581_usb_phy_u2_set_mode(struct an7581_usb_phy_priv *priv,
+ enum phy_mode mode)
+{
+ u32 val;
+
+ /*
+ * For Device and Host mode, enable force IDDIG.
+ * For Device set IDDIG, for Host clear IDDIG.
+ * For OTG disable force and clear IDDIG bit while at it.
+ */
+ switch (mode) {
+ case PHY_MODE_USB_DEVICE:
+ val = AIROHA_USB_PHY_FORCE_IDDIG |
+ AIROHA_USB_PHY_IDDIG;
+ break;
+ case PHY_MODE_USB_HOST:
+ val = AIROHA_USB_PHY_FORCE_IDDIG;
+ break;
+ case PHY_MODE_USB_OTG:
+ val = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ regmap_update_bits(priv->regmap, AIROHA_USB_PHY_U2PHYDTM1,
+ AIROHA_USB_PHY_FORCE_IDDIG |
+ AIROHA_USB_PHY_IDDIG, val);
+
+ return 0;
+}
+
+static int an7581_usb_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
+{
+ struct an7581_usb_phy_instance *instance = phy_get_drvdata(phy);
+ struct an7581_usb_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
+
+ switch (instance->type) {
+ case PHY_TYPE_USB2:
+ return an7581_usb_phy_u2_set_mode(priv, mode);
+ default:
+ return 0;
+ }
+}
+
+static struct phy *an7581_usb_phy_xlate(struct device *dev,
+ const struct of_phandle_args *args)
+{
+ struct an7581_usb_phy_priv *priv = dev_get_drvdata(dev);
+ struct an7581_usb_phy_instance *instance = NULL;
+ unsigned int index, phy_type;
+
+ if (args->args_count != 1) {
+ dev_err(dev, "invalid number of cells in 'phy' property\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ phy_type = args->args[0];
+ if (!(phy_type == PHY_TYPE_USB2 || phy_type == PHY_TYPE_USB3)) {
+ dev_err(dev, "unsupported device type: %d\n", phy_type);
+ return ERR_PTR(-EINVAL);
+ }
+
+ for (index = 0; index < AIROHA_PHY_USB_MAX; index++)
+ if (priv->phys[index] &&
+ phy_type == priv->phys[index]->type) {
+ instance = priv->phys[index];
+ break;
+ }
+
+ if (!instance) {
+ dev_err(dev, "failed to find appropriate phy\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ if (instance->type == PHY_TYPE_USB3 && !priv->serdes_phy) {
+ dev_err(dev, "missing serdes phy for USB 3.0\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ return instance->phy;
+}
+
+static const struct phy_ops airoha_phy = {
+ .init = an7581_usb_phy_init,
+ .power_on = an7581_usb_phy_power_on,
+ .power_off = an7581_usb_phy_power_off,
+ .set_mode = an7581_usb_phy_set_mode,
+ .owner = THIS_MODULE,
+};
+
+static const struct regmap_config an7581_usb_phy_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static int an7581_usb_phy_probe(struct platform_device *pdev)
+{
+ struct phy_provider *phy_provider;
+ struct an7581_usb_phy_priv *priv;
+ struct device *dev = &pdev->dev;
+ unsigned int index;
+ void __iomem *base;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+
+ ret = of_property_read_u32(dev->of_node, "airoha,usb2-monitor-clk-sel",
+ &priv->monclk_sel);
+ if (ret)
+ return dev_err_probe(dev, ret, "Monitor clock selection is mandatory for USB PHY calibration\n");
+
+ if (priv->monclk_sel > 3)
+ return dev_err_probe(dev, -EINVAL, "only 4 Monitor clock are selectable on the SoC\n");
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ priv->regmap = devm_regmap_init_mmio(dev, base, &an7581_usb_phy_regmap_config);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ platform_set_drvdata(pdev, priv);
+
+ for (index = 0; index < AIROHA_PHY_USB_MAX; index++) {
+ struct an7581_usb_phy_instance *instance;
+ u32 phy_type;
+
+ switch (index) {
+ case AIROHA_PHY_USB2:
+ phy_type = PHY_TYPE_USB2;
+ break;
+ case AIROHA_PHY_USB3:
+ phy_type = PHY_TYPE_USB3;
+ break;
+ }
+
+ if (phy_type == PHY_TYPE_USB3) {
+ priv->serdes_phy = devm_phy_optional_get(dev, NULL);
+ if (IS_ERR(priv->serdes_phy))
+ return dev_err_probe(dev, PTR_ERR(priv->serdes_phy), "error on serdes phy for USB 3.0\n");
+ }
+
+ instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
+ if (!instance)
+ return -ENOMEM;
+
+ instance->type = phy_type;
+ priv->phys[index] = instance;
+
+ instance->phy = devm_phy_create(dev, NULL, &airoha_phy);
+ if (IS_ERR(instance->phy))
+ return dev_err_probe(dev, PTR_ERR(instance->phy), "failed to create phy\n");
+
+ phy_set_drvdata(instance->phy, instance);
+ }
+
+ phy_provider = devm_of_phy_provider_register(&pdev->dev, an7581_usb_phy_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id airoha_phy_id_table[] = {
+ { .compatible = "airoha,an7581-usb-phy" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, airoha_phy_id_table);
+
+static struct platform_driver an7581_usb_driver = {
+ .probe = an7581_usb_phy_probe,
+ .driver = {
+ .name = "airoha-an7581-usb-phy",
+ .of_match_table = airoha_phy_id_table,
+ },
+};
+
+module_platform_driver(an7581_usb_driver);
+
+MODULE_DESCRIPTION("Airoha AN7581 USB PHY driver");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_LICENSE("GPL");
--
2.53.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v10 4/5] phy: move and rename Airoha PCIe PHY driver to dedicated directory
From: Christian Marangi @ 2026-07-02 9:38 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Christian Marangi, Vinod Koul,
Neil Armstrong, Lorenzo Bianconi, Felix Fietkau, linux-clk,
devicetree, linux-kernel, linux-arm-kernel, linux-phy
In-Reply-To: <20260702093812.15918-1-ansuelsmth@gmail.com>
To keep the generic PHY directory tidy, move the PCIe PHY driver for
Airoha AN7581 SoC to a dedicated directory.
Also rename the driver and add the relevant SoC name to the .c and .h
file in preparation for support of PCIe and USB PHY driver for Airoha
AN7583 SoC that use a completely different implementation and
calibration for PHYs and will have their own dedicated drivers.
The rename permits to better identify the specific usage of the driver
in the future once the airoha PHY directory will have multiple driver
for multiple SoC.
The config is changed from PHY_AIROHA_PCIE to PHY_AIROHA_AN7581_PCIE.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
MAINTAINERS | 4 ++--
drivers/phy/Kconfig | 11 +----------
drivers/phy/Makefile | 4 ++--
drivers/phy/airoha/Kconfig | 13 +++++++++++++
drivers/phy/airoha/Makefile | 3 +++
.../phy-an7581-pcie-regs.h} | 2 +-
.../{phy-airoha-pcie.c => airoha/phy-an7581-pcie.c} | 6 +++---
7 files changed, 25 insertions(+), 18 deletions(-)
create mode 100644 drivers/phy/airoha/Kconfig
create mode 100644 drivers/phy/airoha/Makefile
rename drivers/phy/{phy-airoha-pcie-regs.h => airoha/phy-an7581-pcie-regs.h} (99%)
rename drivers/phy/{phy-airoha-pcie.c => airoha/phy-an7581-pcie.c} (99%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 05e90c3f7fe0..952653034c4c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -765,8 +765,8 @@ M: Lorenzo Bianconi <lorenzo@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml
-F: drivers/phy/phy-airoha-pcie-regs.h
-F: drivers/phy/phy-airoha-pcie.c
+F: drivers/phy/airoha/phy-an7581-pcie-regs.h
+F: drivers/phy/airoha/phy-an7581-pcie.c
AIROHA SPI SNFI DRIVER
M: Lorenzo Bianconi <lorenzo@kernel.org>
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 19f3b7d12b7d..e93951a4a898 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -46,16 +46,6 @@ config GENERIC_PHY_MIPI_DPHY
Provides a number of helpers a core functions for MIPI D-PHY
drivers to us.
-config PHY_AIROHA_PCIE
- tristate "Airoha PCIe-PHY Driver"
- depends on ARCH_AIROHA || COMPILE_TEST
- depends on OF
- select GENERIC_PHY
- help
- Say Y here to add support for Airoha PCIe PHY driver.
- This driver create the basic PHY instance and provides initialize
- callback for PCIe GEN3 port.
-
config PHY_CAN_TRANSCEIVER
tristate "CAN transceiver PHY"
select GENERIC_PHY
@@ -168,6 +158,7 @@ config PHY_XGENE
help
This option enables support for APM X-Gene SoC multi-purpose PHY.
+source "drivers/phy/airoha/Kconfig"
source "drivers/phy/allwinner/Kconfig"
source "drivers/phy/amlogic/Kconfig"
source "drivers/phy/apple/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index d7aa516bcc49..4ca4a07963fc 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,7 +7,6 @@ obj-$(CONFIG_PHY_COMMON_PROPS) += phy-common-props.o
obj-$(CONFIG_PHY_COMMON_PROPS_TEST) += phy-common-props-test.o
obj-$(CONFIG_GENERIC_PHY) += phy-core.o
obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o
-obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
obj-$(CONFIG_PHY_CAN_TRANSCEIVER) += phy-can-transceiver.o
obj-$(CONFIG_PHY_ECONET_PCIE) += phy-econet-pcie.o
obj-$(CONFIG_PHY_EYEQ5_ETH) += phy-eyeq5-eth.o
@@ -20,7 +19,8 @@ obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o
obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
-obj-$(CONFIG_GENERIC_PHY) += allwinner/ \
+obj-$(CONFIG_GENERIC_PHY) += airoha/ \
+ allwinner/ \
amlogic/ \
apple/ \
axiado/ \
diff --git a/drivers/phy/airoha/Kconfig b/drivers/phy/airoha/Kconfig
new file mode 100644
index 000000000000..9a1b625a7701
--- /dev/null
+++ b/drivers/phy/airoha/Kconfig
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Phy drivers for Airoha devices
+#
+config PHY_AIROHA_AN7581_PCIE
+ tristate "Airoha AN7581 PCIe-PHY Driver"
+ depends on ARCH_AIROHA || COMPILE_TEST
+ depends on OF
+ select GENERIC_PHY
+ help
+ Say Y here to add support for Airoha AN7581 PCIe PHY driver.
+ This driver create the basic PHY instance and provides initialize
+ callback for PCIe GEN3 port.
diff --git a/drivers/phy/airoha/Makefile b/drivers/phy/airoha/Makefile
new file mode 100644
index 000000000000..912f3e11a061
--- /dev/null
+++ b/drivers/phy/airoha/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_PHY_AIROHA_AN7581_PCIE) += phy-an7581-pcie.o
diff --git a/drivers/phy/phy-airoha-pcie-regs.h b/drivers/phy/airoha/phy-an7581-pcie-regs.h
similarity index 99%
rename from drivers/phy/phy-airoha-pcie-regs.h
rename to drivers/phy/airoha/phy-an7581-pcie-regs.h
index 58572c793722..b938a7b468fe 100644
--- a/drivers/phy/phy-airoha-pcie-regs.h
+++ b/drivers/phy/airoha/phy-an7581-pcie-regs.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2024 AIROHA Inc
* Author: Lorenzo Bianconi <lorenzo@kernel.org>
diff --git a/drivers/phy/phy-airoha-pcie.c b/drivers/phy/airoha/phy-an7581-pcie.c
similarity index 99%
rename from drivers/phy/phy-airoha-pcie.c
rename to drivers/phy/airoha/phy-an7581-pcie.c
index 56e9ade8a9fd..81ddf0e7638b 100644
--- a/drivers/phy/phy-airoha-pcie.c
+++ b/drivers/phy/airoha/phy-an7581-pcie.c
@@ -13,7 +13,7 @@
#include <linux/platform_device.h>
#include <linux/slab.h>
-#include "phy-airoha-pcie-regs.h"
+#include "phy-an7581-pcie-regs.h"
#define LEQ_LEN_CTRL_MAX_VAL 7
#define FREQ_LOCK_MAX_ATTEMPT 10
@@ -1279,12 +1279,12 @@ MODULE_DEVICE_TABLE(of, airoha_pcie_phy_of_match);
static struct platform_driver airoha_pcie_phy_driver = {
.probe = airoha_pcie_phy_probe,
.driver = {
- .name = "airoha-pcie-phy",
+ .name = "airoha-an7581-pcie-phy",
.of_match_table = airoha_pcie_phy_of_match,
},
};
module_platform_driver(airoha_pcie_phy_driver);
-MODULE_DESCRIPTION("Airoha PCIe PHY driver");
+MODULE_DESCRIPTION("Airoha AN7581 PCIe PHY driver");
MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
MODULE_LICENSE("GPL");
--
2.53.0
--
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