From: Huang Rui <ray.huang@amd.com>
To: "Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
Viresh Kumar <viresh.kumar@linaro.org>,
Shuah Khan <skhan@linuxfoundation.org>,
"Borislav Petkov" <bp@suse.de>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@kernel.org>,
Giovanni Gherdovich <ggherdovich@suse.cz>,
Steven Rostedt <rostedt@goodmis.org>, <linux-pm@vger.kernel.org>
Cc: Deepak Sharma <deepak.sharma@amd.com>,
Alex Deucher <alexander.deucher@amd.com>,
Mario Limonciello <mario.limonciello@amd.com>,
Steven Noonan <steven@valvesoftware.com>,
Nathan Fontenot <nathan.fontenot@amd.com>,
Jinzhou Su <Jinzhou.Su@amd.com>,
Xiaojian Du <Xiaojian.Du@amd.com>, <linux-kernel@vger.kernel.org>,
<x86@kernel.org>, Huang Rui <ray.huang@amd.com>
Subject: [PATCH v7 01/14] x86/cpufeatures: Add AMD Collaborative Processor Performance Control feature flag
Date: Fri, 24 Dec 2021 09:04:55 +0800 [thread overview]
Message-ID: <20211224010508.110159-2-ray.huang@amd.com> (raw)
In-Reply-To: <20211224010508.110159-1-ray.huang@amd.com>
Add Collaborative Processor Performance Control feature flag for AMD
processors.
This feature flag will be used on the following AMD P-State driver. The
AMD P-State driver has two approaches to implement the frequency control
behavior. That depends on the CPU hardware implementation. One is "Full
MSR Support" and another is "Shared Memory Support". The feature flag
indicates the current processors with "Full MSR Support".
Acked-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
arch/x86/include/asm/cpufeatures.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index d5b5f2ab87a0..18de5f76f198 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -315,6 +315,7 @@
#define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */
#define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
#define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
+#define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */
/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
--
2.25.1
next prev parent reply other threads:[~2021-12-24 1:05 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-24 1:04 [PATCH v7 00/14] cpufreq: Introduce a new AMD CPU frequency control mechanism Huang Rui
2021-12-24 1:04 ` Huang Rui [this message]
2021-12-24 1:04 ` [PATCH v7 02/14] x86/msr: Add AMD CPPC MSR definitions Huang Rui
2021-12-30 16:55 ` Borislav Petkov
2021-12-24 1:04 ` [PATCH v7 03/14] ACPI: CPPC: Implement support for SystemIO registers Huang Rui
2021-12-24 1:04 ` [PATCH v7 04/14] ACPI: CPPC: Check present CPUs for determining _CPC is valid Huang Rui
2021-12-24 1:04 ` [PATCH v7 05/14] ACPI: CPPC: Add CPPC enable register function Huang Rui
2021-12-24 1:05 ` [PATCH v7 06/14] cpufreq: amd-pstate: Introduce a new AMD P-State driver to support future processors Huang Rui
2021-12-24 1:05 ` [PATCH v7 07/14] cpufreq: amd-pstate: Add fast switch function for AMD P-State Huang Rui
2021-12-24 1:05 ` [PATCH v7 08/14] cpufreq: amd-pstate: Introduce the support for the processors with shared memory solution Huang Rui
2021-12-24 1:05 ` [PATCH v7 09/14] cpufreq: amd-pstate: Add trace for AMD P-State module Huang Rui
2021-12-24 1:05 ` [PATCH v7 10/14] cpufreq: amd-pstate: Add boost mode support for AMD P-State Huang Rui
2021-12-24 1:05 ` [PATCH v7 11/14] cpufreq: amd-pstate: Add AMD P-State frequencies attributes Huang Rui
2021-12-24 1:05 ` [PATCH v7 12/14] cpufreq: amd-pstate: Add AMD P-State performance attributes Huang Rui
2021-12-24 1:05 ` [PATCH v7 13/14] Documentation: amd-pstate: Add AMD P-State driver introduction Huang Rui
2021-12-24 1:05 ` [PATCH v7 14/14] MAINTAINERS: Add AMD P-State driver maintainer entry Huang Rui
2021-12-30 15:56 ` [PATCH v7 00/14] cpufreq: Introduce a new AMD CPU frequency control mechanism Rafael J. Wysocki
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