From: Huang Rui <ray.huang@amd.com>
To: "Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
Viresh Kumar <viresh.kumar@linaro.org>,
Shuah Khan <skhan@linuxfoundation.org>,
"Borislav Petkov" <bp@suse.de>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@kernel.org>,
Giovanni Gherdovich <ggherdovich@suse.cz>,
Steven Rostedt <rostedt@goodmis.org>, <linux-pm@vger.kernel.org>
Cc: Deepak Sharma <deepak.sharma@amd.com>,
Alex Deucher <alexander.deucher@amd.com>,
Mario Limonciello <mario.limonciello@amd.com>,
Steven Noonan <steven@valvesoftware.com>,
Nathan Fontenot <nathan.fontenot@amd.com>,
Jinzhou Su <Jinzhou.Su@amd.com>,
Xiaojian Du <Xiaojian.Du@amd.com>, <linux-kernel@vger.kernel.org>,
<x86@kernel.org>, Huang Rui <ray.huang@amd.com>
Subject: [PATCH v7 03/14] ACPI: CPPC: Implement support for SystemIO registers
Date: Fri, 24 Dec 2021 09:04:57 +0800 [thread overview]
Message-ID: <20211224010508.110159-4-ray.huang@amd.com> (raw)
In-Reply-To: <20211224010508.110159-1-ray.huang@amd.com>
From: Steven Noonan <steven@valvesoftware.com>
According to the ACPI v6.2 (and later) specification, SystemIO can be
used for _CPC registers. This teaches cppc_acpi how to handle such
registers.
This patch was tested using the amd_pstate driver on my Zephyrus G15
(model GA503QS) using the current version 410 BIOS, which uses
a SystemIO register for the HighestPerformance element in _CPC.
Signed-off-by: Steven Noonan <steven@valvesoftware.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/acpi/cppc_acpi.c | 52 +++++++++++++++++++++++++++++++++++++---
1 file changed, 49 insertions(+), 3 deletions(-)
diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index a85c351589be..df2933c28bec 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -118,6 +118,8 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
*/
#define NUM_RETRIES 500ULL
+#define OVER_16BTS_MASK ~0xFFFFULL
+
#define define_one_cppc_ro(_name) \
static struct kobj_attribute _name = \
__ATTR(_name, 0444, show_##_name, NULL)
@@ -746,9 +748,26 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
goto out_free;
cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
}
+ } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
+ if (gas_t->access_width < 1 || gas_t->access_width > 3) {
+ /*
+ * 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit.
+ * SystemIO doesn't implement 64-bit
+ * registers.
+ */
+ pr_debug("Invalid access width %d for SystemIO register\n",
+ gas_t->access_width);
+ goto out_free;
+ }
+ if (gas_t->address & OVER_16BTS_MASK) {
+ /* SystemIO registers use 16-bit integer addresses */
+ pr_debug("Invalid IO port %llu for SystemIO register\n",
+ gas_t->address);
+ goto out_free;
+ }
} else {
if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
- /* Support only PCC ,SYS MEM and FFH type regs */
+ /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */
pr_debug("Unsupported register type: %d\n", gas_t->space_id);
goto out_free;
}
@@ -923,7 +942,21 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
}
*val = 0;
- if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
+
+ if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
+ u32 width = 8 << (reg->access_width - 1);
+ acpi_status status;
+
+ status = acpi_os_read_port((acpi_io_address)reg->address,
+ (u32 *)val, width);
+ if (ACPI_FAILURE(status)) {
+ pr_debug("Error: Failed to read SystemIO port %llx\n",
+ reg->address);
+ return -EFAULT;
+ }
+
+ return 0;
+ } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
vaddr = reg_res->sys_mem_vaddr;
@@ -962,7 +995,20 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
struct cpc_reg *reg = ®_res->cpc_entry.reg;
- if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
+ if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
+ u32 width = 8 << (reg->access_width - 1);
+ acpi_status status;
+
+ status = acpi_os_write_port((acpi_io_address)reg->address,
+ (u32)val, width);
+ if (ACPI_FAILURE(status)) {
+ pr_debug("Error: Failed to write SystemIO port %llx\n",
+ reg->address);
+ return -EFAULT;
+ }
+
+ return 0;
+ } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
vaddr = reg_res->sys_mem_vaddr;
--
2.25.1
next prev parent reply other threads:[~2021-12-24 1:05 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-24 1:04 [PATCH v7 00/14] cpufreq: Introduce a new AMD CPU frequency control mechanism Huang Rui
2021-12-24 1:04 ` [PATCH v7 01/14] x86/cpufeatures: Add AMD Collaborative Processor Performance Control feature flag Huang Rui
2021-12-24 1:04 ` [PATCH v7 02/14] x86/msr: Add AMD CPPC MSR definitions Huang Rui
2021-12-30 16:55 ` Borislav Petkov
2021-12-24 1:04 ` Huang Rui [this message]
2021-12-24 1:04 ` [PATCH v7 04/14] ACPI: CPPC: Check present CPUs for determining _CPC is valid Huang Rui
2021-12-24 1:04 ` [PATCH v7 05/14] ACPI: CPPC: Add CPPC enable register function Huang Rui
2021-12-24 1:05 ` [PATCH v7 06/14] cpufreq: amd-pstate: Introduce a new AMD P-State driver to support future processors Huang Rui
2021-12-24 1:05 ` [PATCH v7 07/14] cpufreq: amd-pstate: Add fast switch function for AMD P-State Huang Rui
2021-12-24 1:05 ` [PATCH v7 08/14] cpufreq: amd-pstate: Introduce the support for the processors with shared memory solution Huang Rui
2021-12-24 1:05 ` [PATCH v7 09/14] cpufreq: amd-pstate: Add trace for AMD P-State module Huang Rui
2021-12-24 1:05 ` [PATCH v7 10/14] cpufreq: amd-pstate: Add boost mode support for AMD P-State Huang Rui
2021-12-24 1:05 ` [PATCH v7 11/14] cpufreq: amd-pstate: Add AMD P-State frequencies attributes Huang Rui
2021-12-24 1:05 ` [PATCH v7 12/14] cpufreq: amd-pstate: Add AMD P-State performance attributes Huang Rui
2021-12-24 1:05 ` [PATCH v7 13/14] Documentation: amd-pstate: Add AMD P-State driver introduction Huang Rui
2021-12-24 1:05 ` [PATCH v7 14/14] MAINTAINERS: Add AMD P-State driver maintainer entry Huang Rui
2021-12-30 15:56 ` [PATCH v7 00/14] cpufreq: Introduce a new AMD CPU frequency control mechanism Rafael J. Wysocki
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