From: Borislav Petkov <bp@suse.de>
To: Huang Rui <ray.huang@amd.com>
Cc: "Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
Viresh Kumar <viresh.kumar@linaro.org>,
Shuah Khan <skhan@linuxfoundation.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@kernel.org>,
Giovanni Gherdovich <ggherdovich@suse.cz>,
Steven Rostedt <rostedt@goodmis.org>,
linux-pm@vger.kernel.org, Deepak Sharma <deepak.sharma@amd.com>,
Alex Deucher <alexander.deucher@amd.com>,
Mario Limonciello <mario.limonciello@amd.com>,
Steven Noonan <steven@valvesoftware.com>,
Nathan Fontenot <nathan.fontenot@amd.com>,
Jinzhou Su <Jinzhou.Su@amd.com>,
Xiaojian Du <Xiaojian.Du@amd.com>,
linux-kernel@vger.kernel.org, x86@kernel.org
Subject: Re: [PATCH v7 02/14] x86/msr: Add AMD CPPC MSR definitions
Date: Thu, 30 Dec 2021 17:55:10 +0100 [thread overview]
Message-ID: <Yc3kbiZWeLBcCrw9@zn.tnic> (raw)
In-Reply-To: <20211224010508.110159-3-ray.huang@amd.com>
On Fri, Dec 24, 2021 at 09:04:56AM +0800, Huang Rui wrote:
> AMD CPPC (Collaborative Processor Performance Control) function uses MSR
> registers to manage the performance hints. So add the MSR register macro
> here.
>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
> arch/x86/include/asm/msr-index.h | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
Acked-by: Borislav Petkov <bp@suse.de>
--
Regards/Gruss,
Boris.
SUSE Software Solutions Germany GmbH, GF: Ivo Totev, HRB 36809, AG Nürnberg
next prev parent reply other threads:[~2021-12-30 16:55 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-24 1:04 [PATCH v7 00/14] cpufreq: Introduce a new AMD CPU frequency control mechanism Huang Rui
2021-12-24 1:04 ` [PATCH v7 01/14] x86/cpufeatures: Add AMD Collaborative Processor Performance Control feature flag Huang Rui
2021-12-24 1:04 ` [PATCH v7 02/14] x86/msr: Add AMD CPPC MSR definitions Huang Rui
2021-12-30 16:55 ` Borislav Petkov [this message]
2021-12-24 1:04 ` [PATCH v7 03/14] ACPI: CPPC: Implement support for SystemIO registers Huang Rui
2021-12-24 1:04 ` [PATCH v7 04/14] ACPI: CPPC: Check present CPUs for determining _CPC is valid Huang Rui
2021-12-24 1:04 ` [PATCH v7 05/14] ACPI: CPPC: Add CPPC enable register function Huang Rui
2021-12-24 1:05 ` [PATCH v7 06/14] cpufreq: amd-pstate: Introduce a new AMD P-State driver to support future processors Huang Rui
2021-12-24 1:05 ` [PATCH v7 07/14] cpufreq: amd-pstate: Add fast switch function for AMD P-State Huang Rui
2021-12-24 1:05 ` [PATCH v7 08/14] cpufreq: amd-pstate: Introduce the support for the processors with shared memory solution Huang Rui
2021-12-24 1:05 ` [PATCH v7 09/14] cpufreq: amd-pstate: Add trace for AMD P-State module Huang Rui
2021-12-24 1:05 ` [PATCH v7 10/14] cpufreq: amd-pstate: Add boost mode support for AMD P-State Huang Rui
2021-12-24 1:05 ` [PATCH v7 11/14] cpufreq: amd-pstate: Add AMD P-State frequencies attributes Huang Rui
2021-12-24 1:05 ` [PATCH v7 12/14] cpufreq: amd-pstate: Add AMD P-State performance attributes Huang Rui
2021-12-24 1:05 ` [PATCH v7 13/14] Documentation: amd-pstate: Add AMD P-State driver introduction Huang Rui
2021-12-24 1:05 ` [PATCH v7 14/14] MAINTAINERS: Add AMD P-State driver maintainer entry Huang Rui
2021-12-30 15:56 ` [PATCH v7 00/14] cpufreq: Introduce a new AMD CPU frequency control mechanism Rafael J. Wysocki
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