Re: [PATCH v3 6/6] Documentation: power/cpuidle: Document the CPU system wakeup latency QoS

[Dhruva Gole <d-gole@ti.com>]

On Nov 21, 2025 at 11:03:12 +0100, Ulf Hansson wrote:
> Let's document how the new CPU system wakeup latency QoS limit can be used
> from user space, along with how the constraint is taken into account for
> s2idle and cpuidle.
> 
> Cc: Jonathan Corbet <corbet@lwn.net>
> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
> ---
> 
> Changes in v3:
> 	- Improved documentation.
> 	- Updated commit message.
> 
> Changes in v2:
> 	- New patch.
> 
> ---
>  Documentation/admin-guide/pm/cpuidle.rst | 9 +++++++++
>  Documentation/power/pm_qos_interface.rst | 9 +++++----
>  2 files changed, 14 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/admin-guide/pm/cpuidle.rst b/Documentation/admin-guide/pm/cpuidle.rst
> index 0c090b076224..c39ad6ab99d9 100644
> --- a/Documentation/admin-guide/pm/cpuidle.rst
> +++ b/Documentation/admin-guide/pm/cpuidle.rst
> @@ -580,6 +580,15 @@ the given CPU as the upper limit for the exit latency of the idle states that
>  they are allowed to select for that CPU.  They should never select any idle
>  states with exit latency beyond that limit.
>  
> +While the above CPU QoS constraints applies to CPU idle time management, user

Nit: s/applies/apply

> +space may also request a CPU system wakeup latency QoS limit, via the
> +`cpu_wakeup_latency` file.  This QoS constraint is respected when selecting a
> +suitable idle state for the CPUs, while entering the system-wide suspend-to-idle
> +sleep state, but also to the regular CPU idle time management.
> +
> +Note that, the management of the `cpu_wakeup_latency` file works according to
> +the 'cpu_dma_latency' file from user space point of view.  Moreover, the unit
> +is also microseconds.
>  
>  Idle States Control Via Kernel Command Line
>  ===========================================
> diff --git a/Documentation/power/pm_qos_interface.rst b/Documentation/power/pm_qos_interface.rst
> index 5019c79c7710..4c008e2202f0 100644
> --- a/Documentation/power/pm_qos_interface.rst
> +++ b/Documentation/power/pm_qos_interface.rst
> @@ -55,7 +55,8 @@ int cpu_latency_qos_request_active(handle):
>  
>  From user space:
>  
> -The infrastructure exposes one device node, /dev/cpu_dma_latency, for the CPU
> +The infrastructure exposes two separate device nodes, /dev/cpu_dma_latency for
> +the CPU latency QoS and /dev/cpu_wakeup_latency for the CPU system wakeup
>  latency QoS.
>  
>  Only processes can register a PM QoS request.  To provide for automatic
> @@ -63,15 +64,15 @@ cleanup of a process, the interface requires the process to register its
>  parameter requests as follows.
>  
>  To register the default PM QoS target for the CPU latency QoS, the process must
> -open /dev/cpu_dma_latency.
> +open /dev/cpu_dma_latency.  To register a CPU system wakeup QoS limit, the
> +process must open /dev/cpu_wakeup_latency.
>  
>  As long as the device node is held open that process has a registered
>  request on the parameter.
>  
>  To change the requested target value, the process needs to write an s32 value to
>  the open device node.  Alternatively, it can write a hex string for the value
> -using the 10 char long format e.g. "0x12345678".  This translates to a
> -cpu_latency_qos_update_request() call.
> +using the 10 char long format e.g. "0x12345678".

LGTM,
Reviewed-by: Dhruva Gole <d-gole@ti.com>

-- 
Best regards,
Dhruva Gole
Texas Instruments Incorporated