[PATCH 00/11] arm64: renesas: r8a78000: Add PWM support

[PATCH 00/11] arm64: renesas: r8a78000: Add PWM support

[Geert Uytterhoeven]

	Hi all,

This patch series enables PWM support for the Renesas R-Car X5H SoC, as
found on the Renesas Ironhide development board.  On this board, clocks,
power-domains, and resets must be accessed only through SCMI firmware.

Just like its GPIO counterpart[1], this series is a bit special, in that
several patches are not meant to be applied upstream yet:
  1. The first patch, targeting the PWM tree, documents support for the
     16-Bit Timer Pulse Unit (TPU) on R-Car X5H; no driver changes are
     needed,
  2. Patches 2-6, targeting the PWM tree too, document and add support
     for the PWM instances on R-Car X5H, after a few customary
     refactorings,
  3. Patch 7, targeting a shared DT bindings branch, adds PWM clock
     definitions,
  4. Patch 8, targeting renesas-devel, adds the various PWM device nodes
     to the R-Car X5H .dtsi file,
  5. The remaining patches are marked DNI, and depend on code or DTS
     that is not yet upstream.  More detail can be found in the
     individual patches.

PWM instances 0 to 5 and TPU channels 0 and 1 have been tested on
Ironhide using a set of blinkenlights and a logic analyzer.

Thanks for your comments!

[1] "[PATCH 0/7] arm64: renesas: r8a78000: Enable GPIO support"
    https://lore.kernel.org/cover.1792776697.git.geert+renesas@glider.be

Geert Uytterhoeven (10):
  dt-bindings: pwm: renesas,pwm-rcar: Add support for R-Car X5H
  pwm: rcar: Use FIELD_PREP() for PWMCR_CC0 access
  pwm: rcar: Add helper variable dev to rcar_pwm_probe()
  pwm: rcar: Parametrize cycle counter field size
  pwm: rcar: Add support for R-Car Gen5
  dt-bindings: clock: renesas,r8a78000-cpg: Add PWM clocks
  arm64: dts: renesas: r8a78000: Add PWM nodes
  [DNI] clk: renesas: r8a78000: Add PWM clocks
  [DNI] pmdomain: renesas: r8a78000: Add PWM support
  [DNI] arm64: dts: renesas: ironhide: Enable PWM

Khanh Le (1):
  dt-bindings: pwm: renesas,tpu-pwm: Add support for R-Car X5H

 .../bindings/pwm/renesas,pwm-rcar.yaml        |  61 +++++----
 .../bindings/pwm/renesas,tpu-pwm.yaml         |   1 +
 .../boot/dts/renesas/r8a78000-ironhide.dts    |  84 ++++++++++++
 arch/arm64/boot/dts/renesas/r8a78000.dtsi     | 121 ++++++++++++++++++
 drivers/clk/renesas/r8a78000-cpg.c            |   6 +
 drivers/pmdomain/renesas/r8a78000-mdlc.c      |   2 +
 drivers/pwm/pwm-rcar.c                        |  92 ++++++++-----
 .../dt-bindings/clock/renesas,r8a78000-cpg.h  |   3 +
 8 files changed, 312 insertions(+), 58 deletions(-)

-- 
2.43.0

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH 01/11] dt-bindings: pwm: renesas,tpu-pwm: Add support for R-Car X5H

[Geert Uytterhoeven]

From: Khanh Le <khanh.le.xr@renesas.com>

Document support for the 16-Bit Timer Pulse Unit (TPU) in the Renesas
R-Car X5H (R8A78000) SoC.

Signed-off-by: Khanh Le <khanh.le.xr@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
index f85ee5d20ccbb3f9..144a88ff53e5633b 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
@@ -33,6 +33,7 @@ properties:
           - renesas,tpu-r8a779a0  # R-Car V3U
           - renesas,tpu-r8a779g0  # R-Car V4H
           - renesas,tpu-r8a779h0  # R-Car V4M
+          - renesas,tpu-r8a78000  # R-Car X5H
       - const: renesas,tpu
 
   reg:
-- 
2.43.0

[PATCH 02/11] dt-bindings: pwm: renesas,pwm-rcar: Add support for R-Car X5H

[Geert Uytterhoeven]

Document support for the Pulse Width Modulation (PWM) module in the
Renesas R-Car X5H (R8A78000) SoC.

R-Car Gen5 enlarged the PWM output cycle and high-level period fields
from 10 to 24 bits.  While the added register bits have initial states
of all-zeroes, and thus look compatible with previous generations, the
register bits may have been modified before Linux boots.  Hence no
fallback to renesas,pwm-rcar is included.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 .../bindings/pwm/renesas,pwm-rcar.yaml        | 61 ++++++++++---------
 1 file changed, 33 insertions(+), 28 deletions(-)

diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml
index 2fe1992e29088c9a..424ca1e2df15354c 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml
+++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml
@@ -11,34 +11,39 @@ maintainers:
 
 properties:
   compatible:
-    items:
-      - enum:
-          - renesas,pwm-r8a7742   # RZ/G1H
-          - renesas,pwm-r8a7743   # RZ/G1M
-          - renesas,pwm-r8a7744   # RZ/G1N
-          - renesas,pwm-r8a7745   # RZ/G1E
-          - renesas,pwm-r8a77470  # RZ/G1C
-          - renesas,pwm-r8a774a1  # RZ/G2M
-          - renesas,pwm-r8a774b1  # RZ/G2N
-          - renesas,pwm-r8a774c0  # RZ/G2E
-          - renesas,pwm-r8a774e1  # RZ/G2H
-          - renesas,pwm-r8a7778   # R-Car M1A
-          - renesas,pwm-r8a7779   # R-Car H1
-          - renesas,pwm-r8a7790   # R-Car H2
-          - renesas,pwm-r8a7791   # R-Car M2-W
-          - renesas,pwm-r8a7794   # R-Car E2
-          - renesas,pwm-r8a7795   # R-Car H3
-          - renesas,pwm-r8a7796   # R-Car M3-W
-          - renesas,pwm-r8a77961  # R-Car M3-W+
-          - renesas,pwm-r8a77965  # R-Car M3-N
-          - renesas,pwm-r8a77970  # R-Car V3M
-          - renesas,pwm-r8a77980  # R-Car V3H
-          - renesas,pwm-r8a77990  # R-Car E3
-          - renesas,pwm-r8a77995  # R-Car D3
-          - renesas,pwm-r8a779a0  # R-Car V3U
-          - renesas,pwm-r8a779g0  # R-Car V4H
-          - renesas,pwm-r8a779h0  # R-Car V4M
-      - const: renesas,pwm-rcar
+    oneOf:
+      - items:
+          - enum:
+              - renesas,pwm-r8a7742   # RZ/G1H
+              - renesas,pwm-r8a7743   # RZ/G1M
+              - renesas,pwm-r8a7744   # RZ/G1N
+              - renesas,pwm-r8a7745   # RZ/G1E
+              - renesas,pwm-r8a77470  # RZ/G1C
+              - renesas,pwm-r8a774a1  # RZ/G2M
+              - renesas,pwm-r8a774b1  # RZ/G2N
+              - renesas,pwm-r8a774c0  # RZ/G2E
+              - renesas,pwm-r8a774e1  # RZ/G2H
+              - renesas,pwm-r8a7778   # R-Car M1A
+              - renesas,pwm-r8a7779   # R-Car H1
+              - renesas,pwm-r8a7790   # R-Car H2
+              - renesas,pwm-r8a7791   # R-Car M2-W
+              - renesas,pwm-r8a7794   # R-Car E2
+              - renesas,pwm-r8a7795   # R-Car H3
+              - renesas,pwm-r8a7796   # R-Car M3-W
+              - renesas,pwm-r8a77961  # R-Car M3-W+
+              - renesas,pwm-r8a77965  # R-Car M3-N
+              - renesas,pwm-r8a77970  # R-Car V3M
+              - renesas,pwm-r8a77980  # R-Car V3H
+              - renesas,pwm-r8a77990  # R-Car E3
+              - renesas,pwm-r8a77995  # R-Car D3
+              - renesas,pwm-r8a779a0  # R-Car V3U
+              - renesas,pwm-r8a779g0  # R-Car V4H
+              - renesas,pwm-r8a779h0  # R-Car V4M
+          - const: renesas,pwm-rcar
+      - items:
+          - enum:
+              - renesas,pwm-r8a78000  # R-Car X5H
+          - const: renesas,rcar-gen5-pwm
 
   reg:
     # base address and length of the registers block for the PWM.
-- 
2.43.0

[PATCH 03/11] pwm: rcar: Use FIELD_PREP() for PWMCR_CC0 access

[Geert Uytterhoeven]

Use the FIELD_PREP() helper instead of open-coding the same operation.
Drop the now unused RCAR_PWMCR_CC0_SHIFT definition, and redefine
RCAR_PWMCR_CC0_SHIFT using GENMASK() while at it.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/pwm/pwm-rcar.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/pwm/pwm-rcar.c b/drivers/pwm/pwm-rcar.c
index 1733cd700693713e..4641f258df531baf 100644
--- a/drivers/pwm/pwm-rcar.c
+++ b/drivers/pwm/pwm-rcar.c
@@ -25,8 +25,7 @@
 #define RCAR_PWM_MAX_CYCLE	1023
 
 #define RCAR_PWMCR		0x00
-#define  RCAR_PWMCR_CC0_MASK	0x000f0000
-#define  RCAR_PWMCR_CC0_SHIFT	16
+#define  RCAR_PWMCR_CC0_MASK	GENMASK(19, 16)
 #define  RCAR_PWMCR_CCMD	BIT(15)
 #define  RCAR_PWMCR_SYNC	BIT(11)
 #define  RCAR_PWMCR_SS0		BIT(4)
@@ -99,7 +98,7 @@ static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp,
 
 	div >>= 1;
 
-	value |= div << RCAR_PWMCR_CC0_SHIFT;
+	value |= FIELD_PREP(RCAR_PWMCR_CC0_MASK, div);
 	rcar_pwm_write(rp, value, RCAR_PWMCR);
 }
 
-- 
2.43.0

[PATCH 04/11] pwm: rcar: Add helper variable dev to rcar_pwm_probe()

[Geert Uytterhoeven]

rcar_pwm_probe() has many users of "&pdev->dev".
Introduce a shorthand to simplify the code.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/pwm/pwm-rcar.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/pwm/pwm-rcar.c b/drivers/pwm/pwm-rcar.c
index 4641f258df531baf..f1f68bfe016f729f 100644
--- a/drivers/pwm/pwm-rcar.c
+++ b/drivers/pwm/pwm-rcar.c
@@ -202,11 +202,12 @@ static const struct pwm_ops rcar_pwm_ops = {
 
 static int rcar_pwm_probe(struct platform_device *pdev)
 {
-	struct pwm_chip *chip;
+	struct device *dev = &pdev->dev;
 	struct rcar_pwm_chip *rcar_pwm;
+	struct pwm_chip *chip;
 	int ret;
 
-	chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*rcar_pwm));
+	chip = devm_pwmchip_alloc(dev, 1, sizeof(*rcar_pwm));
 	if (IS_ERR(chip))
 		return PTR_ERR(chip);
 	rcar_pwm = to_rcar_pwm_chip(chip);
@@ -215,9 +216,9 @@ static int rcar_pwm_probe(struct platform_device *pdev)
 	if (IS_ERR(rcar_pwm->base))
 		return PTR_ERR(rcar_pwm->base);
 
-	rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL);
+	rcar_pwm->clk = devm_clk_get(dev, NULL);
 	if (IS_ERR(rcar_pwm->clk)) {
-		dev_err(&pdev->dev, "cannot get clock\n");
+		dev_err(dev, "cannot get clock\n");
 		return PTR_ERR(rcar_pwm->clk);
 	}
 
@@ -225,12 +226,12 @@ static int rcar_pwm_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, chip);
 
-	pm_runtime_enable(&pdev->dev);
+	pm_runtime_enable(dev);
 
 	ret = pwmchip_add(chip);
 	if (ret < 0) {
-		dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret);
-		pm_runtime_disable(&pdev->dev);
+		dev_err(dev, "failed to register PWM chip: %d\n", ret);
+		pm_runtime_disable(dev);
 		return ret;
 	}
 
-- 
2.43.0

[PATCH 05/11] pwm: rcar: Parametrize cycle counter field size

[Geert Uytterhoeven]

Prepare for the advent of PWM blocks with output cycle and high-level
period fields larger than 10 bits by parametrizing the field size.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/pwm/pwm-rcar.c | 51 +++++++++++++++++++++++++++---------------
 1 file changed, 33 insertions(+), 18 deletions(-)

diff --git a/drivers/pwm/pwm-rcar.c b/drivers/pwm/pwm-rcar.c
index f1f68bfe016f729f..3813094c601efc8c 100644
--- a/drivers/pwm/pwm-rcar.c
+++ b/drivers/pwm/pwm-rcar.c
@@ -22,7 +22,7 @@
 #include <linux/slab.h>
 
 #define RCAR_PWM_MAX_DIVISION	24
-#define RCAR_PWM_MAX_CYCLE	1023
+#define RCAR_PWM_MAX_CYCLE(rp)	GENMASK(rp->cycle_bits - 1, 0)
 
 #define RCAR_PWMCR		0x00
 #define  RCAR_PWMCR_CC0_MASK	GENMASK(19, 16)
@@ -32,14 +32,17 @@
 #define  RCAR_PWMCR_EN0		BIT(0)
 
 #define RCAR_PWMCNT		0x04
-#define  RCAR_PWMCNT_CYC0_MASK	0x03ff0000
-#define  RCAR_PWMCNT_CYC0_SHIFT	16
-#define  RCAR_PWMCNT_PH0_MASK	0x000003ff
-#define  RCAR_PWMCNT_PH0_SHIFT	0
+#define  RCAR_PWMCNT_CYC0_MASK	GENMASK(31, 16)
+#define  RCAR_PWMCNT_PH0_MASK	GENMASK(15, 0)
 
 struct rcar_pwm_chip {
 	void __iomem *base;
 	struct clk *clk;
+	unsigned int cycle_bits;
+};
+
+struct rcar_pwm_info {
+	unsigned int cycle_bits;
 };
 
 static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip)
@@ -77,7 +80,7 @@ static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns)
 	if (clk_rate == 0)
 		return -EINVAL;
 
-	div = (u64)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE;
+	div = mul_u32_u32(NSEC_PER_SEC, RCAR_PWM_MAX_CYCLE(rp));
 	tmp = (u64)period_ns * clk_rate + div - 1;
 	tmp = div64_u64(tmp, div);
 	div = ilog2(tmp - 1) + 1;
@@ -111,21 +114,19 @@ static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, u64 duty_ns,
 
 	/* div <= 24 == RCAR_PWM_MAX_DIVISION, so the shift doesn't overflow. */
 	tmp = mul_u64_u64_div_u64(period_ns, clk_rate, (u64)NSEC_PER_SEC << div);
-	if (tmp > FIELD_MAX(RCAR_PWMCNT_CYC0_MASK))
-		tmp = FIELD_MAX(RCAR_PWMCNT_CYC0_MASK);
-
-	cyc = FIELD_PREP(RCAR_PWMCNT_CYC0_MASK, tmp);
+	cyc = min(tmp, RCAR_PWM_MAX_CYCLE(rp));
 
 	tmp = mul_u64_u64_div_u64(duty_ns, clk_rate, (u64)NSEC_PER_SEC << div);
-	if (tmp > FIELD_MAX(RCAR_PWMCNT_PH0_MASK))
-		tmp = FIELD_MAX(RCAR_PWMCNT_PH0_MASK);
-	ph = FIELD_PREP(RCAR_PWMCNT_PH0_MASK, tmp);
+	ph = min(tmp, RCAR_PWM_MAX_CYCLE(rp));
 
 	/* Avoid prohibited setting */
 	if (cyc == 0 || ph == 0)
 		return -EINVAL;
 
-	rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT);
+	rcar_pwm_write(rp,
+		       FIELD_PREP(RCAR_PWMCNT_CYC0_MASK, cyc) |
+		       FIELD_PREP(RCAR_PWMCNT_PH0_MASK, ph),
+		       RCAR_PWMCNT);
 
 	return 0;
 }
@@ -142,12 +143,15 @@ static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
 
 static int rcar_pwm_enable(struct rcar_pwm_chip *rp)
 {
-	u32 value;
+	u32 value, cyc, ph;
 
 	/* Don't enable the PWM device if CYC0 or PH0 is 0 */
 	value = rcar_pwm_read(rp, RCAR_PWMCNT);
-	if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 ||
-	    (value & RCAR_PWMCNT_PH0_MASK) == 0)
+	cyc = FIELD_GET(RCAR_PWMCNT_CYC0_MASK, value);
+	ph = FIELD_GET(RCAR_PWMCNT_PH0_MASK, value);
+
+	if ((cyc & RCAR_PWM_MAX_CYCLE(rp)) == 0 ||
+	    (ph & RCAR_PWM_MAX_CYCLE(rp)) == 0)
 		return -EINVAL;
 
 	rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR);
@@ -202,11 +206,16 @@ static const struct pwm_ops rcar_pwm_ops = {
 
 static int rcar_pwm_probe(struct platform_device *pdev)
 {
+	const struct rcar_pwm_info *info;
 	struct device *dev = &pdev->dev;
 	struct rcar_pwm_chip *rcar_pwm;
 	struct pwm_chip *chip;
 	int ret;
 
+	info = of_device_get_match_data(dev);
+	if (!info)
+		return -ENODEV;
+
 	chip = devm_pwmchip_alloc(dev, 1, sizeof(*rcar_pwm));
 	if (IS_ERR(chip))
 		return PTR_ERR(chip);
@@ -222,6 +231,8 @@ static int rcar_pwm_probe(struct platform_device *pdev)
 		return PTR_ERR(rcar_pwm->clk);
 	}
 
+	rcar_pwm->cycle_bits = info->cycle_bits;
+
 	chip->ops = &rcar_pwm_ops;
 
 	platform_set_drvdata(pdev, chip);
@@ -247,8 +258,12 @@ static void rcar_pwm_remove(struct platform_device *pdev)
 	pm_runtime_disable(&pdev->dev);
 }
 
+static const struct rcar_pwm_info rcar_pwm_info = {
+	.cycle_bits = 10,
+};
+
 static const struct of_device_id rcar_pwm_of_table[] = {
-	{ .compatible = "renesas,pwm-rcar" },
+	{ .compatible = "renesas,pwm-rcar", .data = &rcar_pwm_info },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
-- 
2.43.0

[PATCH 06/11] pwm: rcar: Add support for R-Car Gen5

[Geert Uytterhoeven]

R-Car Gen5 enlarged the PWM output cycle and high-level period fields
from 10 to 24 bits.  The high parts of each field are stored in a new
register.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/pwm/pwm-rcar.c | 27 ++++++++++++++++++++++-----
 1 file changed, 22 insertions(+), 5 deletions(-)

diff --git a/drivers/pwm/pwm-rcar.c b/drivers/pwm/pwm-rcar.c
index 3813094c601efc8c..5e91509de7a7c162 100644
--- a/drivers/pwm/pwm-rcar.c
+++ b/drivers/pwm/pwm-rcar.c
@@ -31,7 +31,8 @@
 #define  RCAR_PWMCR_SS0		BIT(4)
 #define  RCAR_PWMCR_EN0		BIT(0)
 
-#define RCAR_PWMCNT		0x04
+#define RCAR_PWMCNTA		0x04		/* Low part */
+#define RCAR_PWMCNTB		0x08		/* High part (R-Car Gen5) */
 #define  RCAR_PWMCNT_CYC0_MASK	GENMASK(31, 16)
 #define  RCAR_PWMCNT_PH0_MASK	GENMASK(15, 0)
 
@@ -124,9 +125,15 @@ static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, u64 duty_ns,
 		return -EINVAL;
 
 	rcar_pwm_write(rp,
-		       FIELD_PREP(RCAR_PWMCNT_CYC0_MASK, cyc) |
-		       FIELD_PREP(RCAR_PWMCNT_PH0_MASK, ph),
-		       RCAR_PWMCNT);
+		       FIELD_PREP(RCAR_PWMCNT_CYC0_MASK, lower_16_bits(cyc)) |
+		       FIELD_PREP(RCAR_PWMCNT_PH0_MASK, lower_16_bits(ph)),
+		       RCAR_PWMCNTA);
+
+	if (rp->cycle_bits >= 16)
+		rcar_pwm_write(rp,
+		       FIELD_PREP(RCAR_PWMCNT_CYC0_MASK, upper_16_bits(cyc)) |
+		       FIELD_PREP(RCAR_PWMCNT_PH0_MASK, upper_16_bits(ph)),
+		       RCAR_PWMCNTB);
 
 	return 0;
 }
@@ -146,9 +153,14 @@ static int rcar_pwm_enable(struct rcar_pwm_chip *rp)
 	u32 value, cyc, ph;
 
 	/* Don't enable the PWM device if CYC0 or PH0 is 0 */
-	value = rcar_pwm_read(rp, RCAR_PWMCNT);
+	value = rcar_pwm_read(rp, RCAR_PWMCNTA);
 	cyc = FIELD_GET(RCAR_PWMCNT_CYC0_MASK, value);
 	ph = FIELD_GET(RCAR_PWMCNT_PH0_MASK, value);
+	if (rp->cycle_bits >= 16) {
+		value = rcar_pwm_read(rp, RCAR_PWMCNTB);
+		cyc |= FIELD_GET(RCAR_PWMCNT_CYC0_MASK, value) << 16;
+		ph |= FIELD_GET(RCAR_PWMCNT_PH0_MASK, value) << 16;
+	}
 
 	if ((cyc & RCAR_PWM_MAX_CYCLE(rp)) == 0 ||
 	    (ph & RCAR_PWM_MAX_CYCLE(rp)) == 0)
@@ -262,8 +274,13 @@ static const struct rcar_pwm_info rcar_pwm_info = {
 	.cycle_bits = 10,
 };
 
+static const struct rcar_pwm_info rcar_gen5_pwm_info = {
+	.cycle_bits = 24,
+};
+
 static const struct of_device_id rcar_pwm_of_table[] = {
 	{ .compatible = "renesas,pwm-rcar", .data = &rcar_pwm_info },
+	{ .compatible = "renesas,rcar-gen5-pwm", .data = &rcar_gen5_pwm_info },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
-- 
2.43.0

[PATCH 07/11] dt-bindings: clock: renesas,r8a78000-cpg: Add PWM clocks

[Geert Uytterhoeven]

Add definitions for the clocks used by the PWM modules on R-Car X5H:
 - R8A78000_CPG_SGASYNCD16_PERW_MAIN,
 - R8A78000_CPG_S0ASYNCD8_PERW_MAIN.
Include R8A78000_CPG_SGASYNCD8_PERW_MAIN for ordering consistency.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
This depends on "[PATCH 2/7] dt-bindings: clock: renesas,r8a78000-cpg:
Add GPIO clocks"
https://lore.kernel.org/624a9fb09e4ec74b1995797e5121b86e7206f5f2.1792776697.git.geert+renesas@glider.be
---
 include/dt-bindings/clock/renesas,r8a78000-cpg.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/dt-bindings/clock/renesas,r8a78000-cpg.h b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
index cd7192ccecd4e22c..8c30476d41448cf5 100644
--- a/include/dt-bindings/clock/renesas,r8a78000-cpg.h
+++ b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
@@ -28,5 +28,8 @@
 #define R8A78000_CPG_SGD8_PERW_BUS		18
 #define R8A78000_CPG_SGD32_PERW_BUS		19
 #define R8A78000_CPG_S0D24_HSCN_OTHER		20
+#define R8A78000_CPG_SGASYNCD8_PERW_MAIN	21
+#define R8A78000_CPG_SGASYNCD16_PERW_MAIN	22
+#define R8A78000_CPG_S0ASYNCD8_PERW_MAIN	23
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ */
-- 
2.43.0

[PATCH 08/11] arm64: dts: renesas: r8a78000: Add PWM nodes

[Geert Uytterhoeven]

Add device nodes for the Pulse Width Modulation (PWM) modules and the
16-Bit Timer Pulse Unit (TPU) on the Renesas R-Car X5H (R8A78000) SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm64/boot/dts/renesas/r8a78000.dtsi | 121 ++++++++++++++++++++++
 1 file changed, 121 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
index 946dce6ab38b619d..c5e48eac4c3712d8 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -1243,6 +1243,127 @@ hscif3: serial@c071c000 {
 			status = "disabled";
 		};
 
+		tpu: pwm@c0720000 {
+			compatible = "renesas,tpu-r8a78000", "renesas,tpu";
+			reg = <0 0xc0720000 0 0x200>;
+			interrupts = <GIC_ESPI 23 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGASYNCD16_PERW_MAIN>;
+			power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x76>;
+			resets = <&mdlc_perw 0x76>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
+		pwm0: pwm@c0740000 {
+			compatible = "renesas,pwm-r8a78000",
+				     "renesas,rcar-gen5-pwm";
+			reg = <0 0xc0740000 0 0x10>;
+			#pwm-cells = <2>;
+			clocks = <&cpg R8A78000_CPG_SGASYNCD16_PERW_MAIN>;
+			power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x70>;
+			resets = <&mdlc_perw 0x70>;
+			status = "disabled";
+		};
+
+		pwm1: pwm@c0741000 {
+			compatible = "renesas,pwm-r8a78000",
+				     "renesas,rcar-gen5-pwm";
+			reg = <0 0xc0741000 0 0x10>;
+			#pwm-cells = <2>;
+			clocks = <&cpg R8A78000_CPG_SGASYNCD16_PERW_MAIN>;
+			power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x70>;
+			resets = <&mdlc_perw 0x70>;
+			status = "disabled";
+		};
+
+		pwm2: pwm@c0742000 {
+			compatible = "renesas,pwm-r8a78000",
+				     "renesas,rcar-gen5-pwm";
+			reg = <0 0xc0742000 0 0x10>;
+			#pwm-cells = <2>;
+			clocks = <&cpg R8A78000_CPG_SGASYNCD16_PERW_MAIN>;
+			power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x70>;
+			resets = <&mdlc_perw 0x70>;
+			status = "disabled";
+		};
+
+		pwm3: pwm@c0743000 {
+			compatible = "renesas,pwm-r8a78000",
+				     "renesas,rcar-gen5-pwm";
+			reg = <0 0xc0743000 0 0x10>;
+			#pwm-cells = <2>;
+			clocks = <&cpg R8A78000_CPG_SGASYNCD16_PERW_MAIN>;
+			power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x70>;
+			resets = <&mdlc_perw 0x70>;
+			status = "disabled";
+		};
+
+		pwm4: pwm@c0780000 {
+			compatible = "renesas,pwm-r8a78000",
+				     "renesas,rcar-gen5-pwm";
+			reg = <0 0xc0780000 0 0x10>;
+			#pwm-cells = <2>;
+			clocks = <&cpg R8A78000_CPG_S0ASYNCD8_PERW_MAIN>;
+			power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x70>;
+			resets = <&mdlc_perw 0x70>;
+			status = "disabled";
+		};
+
+		pwm5: pwm@c0781000 {
+			compatible = "renesas,pwm-r8a78000",
+				     "renesas,rcar-gen5-pwm";
+			reg = <0 0xc0781000 0 0x10>;
+			#pwm-cells = <2>;
+			clocks = <&cpg R8A78000_CPG_S0ASYNCD8_PERW_MAIN>;
+			power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x70>;
+			resets = <&mdlc_perw 0x70>;
+			status = "disabled";
+		};
+
+		pwm6: pwm@c0782000 {
+			compatible = "renesas,pwm-r8a78000",
+				     "renesas,rcar-gen5-pwm";
+			reg = <0 0xc0782000 0 0x10>;
+			#pwm-cells = <2>;
+			clocks = <&cpg R8A78000_CPG_S0ASYNCD8_PERW_MAIN>;
+			power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x70>;
+			resets = <&mdlc_perw 0x70>;
+			status = "disabled";
+		};
+
+		pwm7: pwm@c0783000 {
+			compatible = "renesas,pwm-r8a78000",
+				     "renesas,rcar-gen5-pwm";
+			reg = <0 0xc0783000 0 0x10>;
+			#pwm-cells = <2>;
+			clocks = <&cpg R8A78000_CPG_S0ASYNCD8_PERW_MAIN>;
+			power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x70>;
+			resets = <&mdlc_perw 0x70>;
+			status = "disabled";
+		};
+
+		pwm8: pwm@c0784000 {
+			compatible = "renesas,pwm-r8a78000",
+				     "renesas,rcar-gen5-pwm";
+			reg = <0 0xc0784000 0 0x10>;
+			#pwm-cells = <2>;
+			clocks = <&cpg R8A78000_CPG_S0ASYNCD8_PERW_MAIN>;
+			power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x70>;
+			resets = <&mdlc_perw 0x70>;
+			status = "disabled";
+		};
+
+		pwm9: pwm@c0785000 {
+			compatible = "renesas,pwm-r8a78000",
+				     "renesas,rcar-gen5-pwm";
+			reg = <0 0xc0785000 0 0x10>;
+			#pwm-cells = <2>;
+			clocks = <&cpg R8A78000_CPG_S0ASYNCD8_PERW_MAIN>;
+			power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x70>;
+			resets = <&mdlc_perw 0x70>;
+			status = "disabled";
+		};
+
 		stcm_transport: sram@c1060000 {
 			compatible = "mmio-sram";
 			reg = <0x0 0xc1060000 0x0 0x1c00>;
-- 
2.43.0

[PATCH/DNI 09/11] clk: renesas: r8a78000: Add PWM clocks

[Geert Uytterhoeven]

Add support for the clocks used by the PWM modules on R-Car X5H.
This includes SCMI remapping tables and fixed-clock fallbacks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
This depends on "[PATCH/DNI 4/7] clk: renesas: r8a78000: Add GPIO
clocks"
https://lore.kernel.org/34f97dab00c6d98b7afe8d8df38eeb83abf5c19f.1792776697.git.geert+renesas@glider.be
---
 drivers/clk/renesas/r8a78000-cpg.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/renesas/r8a78000-cpg.c b/drivers/clk/renesas/r8a78000-cpg.c
index 1d66082f6f44b5ba..9b1ff5a8ff1bdc31 100644
--- a/drivers/clk/renesas/r8a78000-cpg.c
+++ b/drivers/clk/renesas/r8a78000-cpg.c
@@ -38,6 +38,7 @@ enum fixed_clk {
 	FIXED_CLK_33M,
 	FIXED_CLK_37M5,
 	FIXED_CLK_66M,
+	FIXED_CLK_100M,
 	FIXED_CLK_133M,
 	FIXED_CLK_266M,
 };
@@ -46,6 +47,7 @@ static const unsigned long fixed_clk_rates[] = {
 	[FIXED_CLK_33M] = 33333000,
 	[FIXED_CLK_37M5] = 37500000,
 	[FIXED_CLK_66M] = 66666000,
+	[FIXED_CLK_100M] = 100000000,
 	[FIXED_CLK_133M] = 133330000,
 	[FIXED_CLK_266M] = 266660000,
 };
@@ -299,6 +301,8 @@ static const struct clk_map_in r8a78000_cpg_default[] = {
 	{ R8A78000_CPG_S0D24_PERE_MAIN,		FIXED_CLK(33M) },
 	{ R8A78000_CPG_SGD32_PERW_BUS,		FIXED_CLK(33M) },
 	{ R8A78000_CPG_S0D24_HSCN_OTHER,	FIXED_CLK(33M) },
+	{ R8A78000_CPG_SGASYNCD16_PERW_MAIN,	FIXED_CLK(66M) },
+	{ R8A78000_CPG_S0ASYNCD8_PERW_MAIN,	FIXED_CLK(100M) },
 	{ -1 }
 };
 
@@ -312,6 +316,8 @@ static const struct clk_map_in r8a78000_cpg_fw[] = {
 	{ R8A78000_CPG_S0D24_PERE_MAIN,		1690 },
 	{ R8A78000_CPG_SGD32_PERW_BUS,		1660 },
 	{ R8A78000_CPG_S0D24_HSCN_OTHER,	1499 },
+	{ R8A78000_CPG_SGASYNCD16_PERW_MAIN,	1651 },
+	{ R8A78000_CPG_S0ASYNCD8_PERW_MAIN,	1653 },
 	{ -1 }
 };
 
-- 
2.43.0

[PATCH/DNI 10/11] pmdomain: renesas: r8a78000: Add PWM support

[Geert Uytterhoeven]

Add support for the Pulse Width Modulation (PWM) modules and the 16-Bit
Timer Pulse Unit (TPU) on R-Car X5H.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
This depends on "[PATCH v4 7/8] pmdomain: renesas: r8a78000: Add SCMI
remapping support"
https://lore.kernel.org/2895c8f3cbe718dc597ad25e16c2461f0d681ab6.1792163045.git.geert+renesas@glider.be/
---
 drivers/pmdomain/renesas/r8a78000-mdlc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pmdomain/renesas/r8a78000-mdlc.c b/drivers/pmdomain/renesas/r8a78000-mdlc.c
index 838566ed821e29e0..62156bfb8080e6e4 100644
--- a/drivers/pmdomain/renesas/r8a78000-mdlc.c
+++ b/drivers/pmdomain/renesas/r8a78000-mdlc.c
@@ -681,6 +681,8 @@ static const struct mod_map_in r8a78000_mdlc_perw_mod_fw[] = {
 	{ 0x55, 225, -1 },	/* HSCIF1 */
 	{ 0x56, 226, -1 },	/* HSCIF2 */
 	{ 0x57, 227, -1 },	/* HSCIF3 */
+	{ 0x70, 244, -1 },	/* PWM0 */
+	{ 0x76, 249, -1 },	/* TPU0 */
 	{ -1 }
 };
 
-- 
2.43.0

[PATCH/DNI 11/11] arm64: dts: renesas: ironhide: Enable PWM

[Geert Uytterhoeven]

Pulse Width Modulation (PWM) instances 0 to 5 and 16-Bit Timer Pulse
Unit (TPU) channels 0 and 1 are wired to PWM CN (CN48).

Note that TPU channels 0 and 1 are mutually-exclusive with PWM instances
4 and 5.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
This depends on out-of-tree pin control support.
---
 .../boot/dts/renesas/r8a78000-ironhide.dts    | 84 +++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
index 5d919953efe4970e..c2d814da9fd97802 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
+++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
@@ -242,10 +242,87 @@ msiof6_pins: msiof6 {
 
 	};
 
+	pwm0_pins: pwm0 {
+		groups = "pwm0_a";
+		function = "pwm0";
+	};
+
+	pwm1_pins: pwm1 {
+		groups = "pwm1";
+		function = "pwm1";
+	};
+
+	pwm2_pins: pwm2 {
+		groups = "pwm2";
+		function = "pwm2";
+	};
+
+	pwm3_pins: pwm3 {
+		groups = "pwm3";
+		function = "pwm3";
+	};
+
+	pwm4_pins: pwm4 {
+		groups = "pwm4";
+		function = "pwm4";
+	};
+
+	pwm5_pins: pwm5 {
+		groups = "pwm5";
+		function = "pwm5";
+	};
+
 	scif_clk_pins: scif-clk {
 		groups = "scif_clk";
 		function = "scif_clk";
 	};
+
+	tpu_pins: tpu {
+		groups = "tpu_to0", "tpu_to1";
+		function = "tpu";
+	};
+};
+
+&pwm0 {
+	pinctrl-0 = <&pwm0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pwm1 {
+	pinctrl-0 = <&pwm1_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pwm2 {
+	pinctrl-0 = <&pwm2_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pwm3 {
+	pinctrl-0 = <&pwm3_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pwm4 {
+	pinctrl-0 = <&pwm4_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pwm5 {
+	pinctrl-0 = <&pwm5_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
 };
 
 &scif_clk {
@@ -263,3 +340,10 @@ scmi_rx_shmem: sram@1300 {
 		reg = <0x1300 0x100>;
 	};
 };
+
+&tpu {
+	pinctrl-0 = <&tpu_pins>;
+	pinctrl-names = "default";
+
+	//status = "okay";	// Mutually-exclusive with pwm4 and pwm5
+};
-- 
2.43.0

Re: [PATCH 01/11] dt-bindings: pwm: renesas,tpu-pwm: Add support for R-Car X5H

[Krzysztof Kozlowski]

On Mon, Oct 26, 2026 at 03:55:17PM +0100, Geert Uytterhoeven wrote:
> From: Khanh Le <khanh.le.xr@renesas.com>
> 
> Document support for the 16-Bit Timer Pulse Unit (TPU) in the Renesas
> R-Car X5H (R8A78000) SoC.
> 
> Signed-off-by: Khanh Le <khanh.le.xr@renesas.com>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH 02/11] dt-bindings: pwm: renesas,pwm-rcar: Add support for R-Car X5H

[Krzysztof Kozlowski]

On Mon, Oct 26, 2026 at 03:55:18PM +0100, Geert Uytterhoeven wrote:
> Document support for the Pulse Width Modulation (PWM) module in the
> Renesas R-Car X5H (R8A78000) SoC.
> 
> R-Car Gen5 enlarged the PWM output cycle and high-level period fields
> from 10 to 24 bits.  While the added register bits have initial states
> of all-zeroes, and thus look compatible with previous generations, the
> register bits may have been modified before Linux boots.  Hence no
> fallback to renesas,pwm-rcar is included.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  .../bindings/pwm/renesas,pwm-rcar.yaml        | 61 ++++++++++---------
>  1 file changed, 33 insertions(+), 28 deletions(-)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH 07/11] dt-bindings: clock: renesas,r8a78000-cpg: Add PWM clocks

[Krzysztof Kozlowski]

On Mon, Oct 26, 2026 at 03:55:23PM +0100, Geert Uytterhoeven wrote:
> Add definitions for the clocks used by the PWM modules on R-Car X5H:
>  - R8A78000_CPG_SGASYNCD16_PERW_MAIN,
>  - R8A78000_CPG_S0ASYNCD8_PERW_MAIN.
> Include R8A78000_CPG_SGASYNCD8_PERW_MAIN for ordering consistency.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> This depends on "[PATCH 2/7] dt-bindings: clock: renesas,r8a78000-cpg:
> Add GPIO clocks"
> https://lore.kernel.org/624a9fb09e4ec74b1995797e5121b86e7206f5f2.1792776697.git.geert+renesas@glider.be
> ---
>  include/dt-bindings/clock/renesas,r8a78000-cpg.h | 3 +++
>  1 file changed, 3 insertions(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH 07/11] dt-bindings: clock: renesas,r8a78000-cpg: Add PWM clocks

[Laurent Pinchart]

Hi Geert,

Thank you for the patch.

On Mon, Oct 26, 2026 at 03:55:23PM +0100, Geert Uytterhoeven wrote:
> Add definitions for the clocks used by the PWM modules on R-Car X5H:
>  - R8A78000_CPG_SGASYNCD16_PERW_MAIN,
>  - R8A78000_CPG_S0ASYNCD8_PERW_MAIN.
> Include R8A78000_CPG_SGASYNCD8_PERW_MAIN for ordering consistency.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> This depends on "[PATCH 2/7] dt-bindings: clock: renesas,r8a78000-cpg:
> Add GPIO clocks"
> https://lore.kernel.org/624a9fb09e4ec74b1995797e5121b86e7206f5f2.1792776697.git.geert+renesas@glider.be
> ---
>  include/dt-bindings/clock/renesas,r8a78000-cpg.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/renesas,r8a78000-cpg.h b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
> index cd7192ccecd4e22c..8c30476d41448cf5 100644
> --- a/include/dt-bindings/clock/renesas,r8a78000-cpg.h
> +++ b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
> @@ -28,5 +28,8 @@
>  #define R8A78000_CPG_SGD8_PERW_BUS		18
>  #define R8A78000_CPG_SGD32_PERW_BUS		19
>  #define R8A78000_CPG_S0D24_HSCN_OTHER		20
> +#define R8A78000_CPG_SGASYNCD8_PERW_MAIN	21
> +#define R8A78000_CPG_SGASYNCD16_PERW_MAIN	22

Could you also add R8A78000_CPG_SGASYNCD4_PERW_MAIN and
R8A78000_CPG_SGASYNCD32_PERW_MAIN for ordering consistency ? The
dependency patch should then also include R8A78000_CPG_SGD4_PERW_BUS and
R8A78000_CPG_SGD16_PERW_BUS, as well as
R8A78000_CPG_S0D{1,2,4,8,12,16}_HSCN_OTHER.

> +#define R8A78000_CPG_S0ASYNCD8_PERW_MAIN	23
>  
>  #endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ */

-- 
Regards,

Laurent Pinchart

Re: [PATCH 07/11] dt-bindings: clock: renesas,r8a78000-cpg: Add PWM clocks

[Geert Uytterhoeven]

Hi Laurent,

On Wed, 28 Oct 2026 at 14:29, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Mon, Oct 26, 2026 at 03:55:23PM +0100, Geert Uytterhoeven wrote:
> > Add definitions for the clocks used by the PWM modules on R-Car X5H:
> >  - R8A78000_CPG_SGASYNCD16_PERW_MAIN,
> >  - R8A78000_CPG_S0ASYNCD8_PERW_MAIN.
> > Include R8A78000_CPG_SGASYNCD8_PERW_MAIN for ordering consistency.
> >
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

> > --- a/include/dt-bindings/clock/renesas,r8a78000-cpg.h
> > +++ b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
> > @@ -28,5 +28,8 @@
> >  #define R8A78000_CPG_SGD8_PERW_BUS           18
> >  #define R8A78000_CPG_SGD32_PERW_BUS          19
> >  #define R8A78000_CPG_S0D24_HSCN_OTHER                20
> > +#define R8A78000_CPG_SGASYNCD8_PERW_MAIN     21
> > +#define R8A78000_CPG_SGASYNCD16_PERW_MAIN    22
>
> Could you also add R8A78000_CPG_SGASYNCD4_PERW_MAIN and
> R8A78000_CPG_SGASYNCD32_PERW_MAIN for ordering consistency ? The
> dependency patch should then also include R8A78000_CPG_SGD4_PERW_BUS and
> R8A78000_CPG_SGD16_PERW_BUS, as well as
> R8A78000_CPG_S0D{1,2,4,8,12,16}_HSCN_OTHER.

I could add them, but do you have any need to refer to them from DT?
So far I only added clocks that are listed as clock supplies of on-SoC
modules, e.g. R8A78000_CPG_SGASYNCD8_PERW_MAIN is supplied to the
Timer Unit (TMU)).

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 07/11] dt-bindings: clock: renesas,r8a78000-cpg: Add PWM clocks

[Laurent Pinchart]

On Wed, Oct 28, 2026 at 03:43:42PM +0100, Geert Uytterhoeven wrote:
> On Wed, 28 Oct 2026 at 14:29, Laurent Pinchart wrote:
> > On Mon, Oct 26, 2026 at 03:55:23PM +0100, Geert Uytterhoeven wrote:
> > > Add definitions for the clocks used by the PWM modules on R-Car X5H:
> > >  - R8A78000_CPG_SGASYNCD16_PERW_MAIN,
> > >  - R8A78000_CPG_S0ASYNCD8_PERW_MAIN.
> > > Include R8A78000_CPG_SGASYNCD8_PERW_MAIN for ordering consistency.
> > >
> > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> > > --- a/include/dt-bindings/clock/renesas,r8a78000-cpg.h
> > > +++ b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
> > > @@ -28,5 +28,8 @@
> > >  #define R8A78000_CPG_SGD8_PERW_BUS           18
> > >  #define R8A78000_CPG_SGD32_PERW_BUS          19
> > >  #define R8A78000_CPG_S0D24_HSCN_OTHER                20
> > > +#define R8A78000_CPG_SGASYNCD8_PERW_MAIN     21
> > > +#define R8A78000_CPG_SGASYNCD16_PERW_MAIN    22
> >
> > Could you also add R8A78000_CPG_SGASYNCD4_PERW_MAIN and
> > R8A78000_CPG_SGASYNCD32_PERW_MAIN for ordering consistency ? The
> > dependency patch should then also include R8A78000_CPG_SGD4_PERW_BUS and
> > R8A78000_CPG_SGD16_PERW_BUS, as well as
> > R8A78000_CPG_S0D{1,2,4,8,12,16}_HSCN_OTHER.
> 
> I could add them, but do you have any need to refer to them from DT?
> So far I only added clocks that are listed as clock supplies of on-SoC
> modules, e.g. R8A78000_CPG_SGASYNCD8_PERW_MAIN is supplied to the
> Timer Unit (TMU)).

So we have two conflicting goals here. One of them is to only add clocks
that we have validated to exist (and ideally work as documented). The
other is to keep renesas,r8a78000-cpg.h readable. We won't be able to
satisfy them both fully.

I think we previously discussed adding whole groups of dividers in one
go, as some sort of middle-ground approach. Those are clocks that are
not directly controllable. There's a risk of adding clocks that don't
exist, or clocks that we won't need to reference from DT (because
they're only used as parents of the MDLC-controlled module clock). Do
you think that's an issue, could it cause ABI problems in the future ?

-- 
Regards,

Laurent Pinchart