* [PATCH v2 1/5] dt-bindings: remoteproc: qcom,sm8350-pas: Add SC8280XP
2025-05-17 17:27 [PATCH v2 0/5] SC8280XP SLPI Konrad Dybcio
@ 2025-05-17 17:27 ` Konrad Dybcio
2025-05-17 17:27 ` [PATCH v2 2/5] arm64: dts: qcom: sc8280xp: Fix node order Konrad Dybcio
` (5 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Konrad Dybcio @ 2025-05-17 17:27 UTC (permalink / raw)
To: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Konrad Dybcio
Cc: Marijn Suijten, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
From the software POV, it matches the SM8350's implementation.
Describe it as such, with a fallback.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
.../bindings/remoteproc/qcom,sm8350-pas.yaml | 54 ++++++++++++----------
1 file changed, 30 insertions(+), 24 deletions(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml
index fd3423e6051bc8bb0e783479360a7b38e5fa1358..6d09823153fc8331f04d4657d9acba718533cce6 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml
@@ -15,16 +15,20 @@ description:
properties:
compatible:
- enum:
- - qcom,sar2130p-adsp-pas
- - qcom,sm8350-adsp-pas
- - qcom,sm8350-cdsp-pas
- - qcom,sm8350-slpi-pas
- - qcom,sm8350-mpss-pas
- - qcom,sm8450-adsp-pas
- - qcom,sm8450-cdsp-pas
- - qcom,sm8450-mpss-pas
- - qcom,sm8450-slpi-pas
+ oneOf:
+ - enum:
+ - qcom,sar2130p-adsp-pas
+ - qcom,sm8350-adsp-pas
+ - qcom,sm8350-cdsp-pas
+ - qcom,sm8350-slpi-pas
+ - qcom,sm8350-mpss-pas
+ - qcom,sm8450-adsp-pas
+ - qcom,sm8450-cdsp-pas
+ - qcom,sm8450-mpss-pas
+ - qcom,sm8450-slpi-pas
+ - items:
+ - const: qcom,sc8280xp-slpi-pas
+ - const: qcom,sm8350-slpi-pas
reg:
maxItems: 1
@@ -61,14 +65,15 @@ allOf:
- if:
properties:
compatible:
- enum:
- - qcom,sar2130p-adsp-pas
- - qcom,sm8350-adsp-pas
- - qcom,sm8350-cdsp-pas
- - qcom,sm8350-slpi-pas
- - qcom,sm8450-adsp-pas
- - qcom,sm8450-cdsp-pas
- - qcom,sm8450-slpi-pas
+ contains:
+ enum:
+ - qcom,sar2130p-adsp-pas
+ - qcom,sm8350-adsp-pas
+ - qcom,sm8350-cdsp-pas
+ - qcom,sm8350-slpi-pas
+ - qcom,sm8450-adsp-pas
+ - qcom,sm8450-cdsp-pas
+ - qcom,sm8450-slpi-pas
then:
properties:
interrupts:
@@ -102,12 +107,13 @@ allOf:
- if:
properties:
compatible:
- enum:
- - qcom,sar2130p-adsp-pas
- - qcom,sm8350-adsp-pas
- - qcom,sm8350-slpi-pas
- - qcom,sm8450-adsp-pas
- - qcom,sm8450-slpi-pas
+ contains:
+ enum:
+ - qcom,sar2130p-adsp-pas
+ - qcom,sm8350-adsp-pas
+ - qcom,sm8350-slpi-pas
+ - qcom,sm8450-adsp-pas
+ - qcom,sm8450-slpi-pas
then:
properties:
power-domains:
--
2.49.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 2/5] arm64: dts: qcom: sc8280xp: Fix node order
2025-05-17 17:27 [PATCH v2 0/5] SC8280XP SLPI Konrad Dybcio
2025-05-17 17:27 ` [PATCH v2 1/5] dt-bindings: remoteproc: qcom,sm8350-pas: Add SC8280XP Konrad Dybcio
@ 2025-05-17 17:27 ` Konrad Dybcio
2025-05-18 10:58 ` Dmitry Baryshkov
2025-05-17 17:27 ` [PATCH v2 3/5] arm64: dts: qcom: sc8280xp: Add SLPI Konrad Dybcio
` (4 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Konrad Dybcio @ 2025-05-17 17:27 UTC (permalink / raw)
To: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Konrad Dybcio
Cc: Marijn Suijten, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Certain /soc@0 subnodes are very out of order. Reshuffle them.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 574 ++++++++++++++++-----------------
1 file changed, 287 insertions(+), 287 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 27d21e1a2d50c6fc12f324ab2b4dfa4b99791b81..94dcbccca62e992030bcdd6eb3bc3fcd879c1e8a 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -2454,293 +2454,6 @@ tcsr: syscon@1fc0000 {
reg = <0x0 0x01fc0000 0x0 0x30000>;
};
- gpu: gpu@3d00000 {
- compatible = "qcom,adreno-690.0", "qcom,adreno";
-
- reg = <0 0x03d00000 0 0x40000>,
- <0 0x03d9e000 0 0x1000>,
- <0 0x03d61000 0 0x800>;
- reg-names = "kgsl_3d0_reg_memory",
- "cx_mem",
- "cx_dbgc";
- interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
- iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
- operating-points-v2 = <&gpu_opp_table>;
-
- qcom,gmu = <&gmu>;
- interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
- interconnect-names = "gfx-mem";
- #cooling-cells = <2>;
-
- status = "disabled";
-
- gpu_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-270000000 {
- opp-hz = /bits/ 64 <270000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
- opp-peak-kBps = <451000>;
- };
-
- opp-410000000 {
- opp-hz = /bits/ 64 <410000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
- opp-peak-kBps = <1555000>;
- };
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
- opp-peak-kBps = <1555000>;
- };
-
- opp-547000000 {
- opp-hz = /bits/ 64 <547000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
- opp-peak-kBps = <1555000>;
- };
-
- opp-606000000 {
- opp-hz = /bits/ 64 <606000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
- opp-peak-kBps = <2736000>;
- };
-
- opp-640000000 {
- opp-hz = /bits/ 64 <640000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
- opp-peak-kBps = <2736000>;
- };
-
- opp-655000000 {
- opp-hz = /bits/ 64 <655000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
- opp-peak-kBps = <2736000>;
- };
-
- opp-690000000 {
- opp-hz = /bits/ 64 <690000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
- opp-peak-kBps = <2736000>;
- };
- };
- };
-
- gmu: gmu@3d6a000 {
- compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
- reg = <0 0x03d6a000 0 0x34000>,
- <0 0x03de0000 0 0x10000>,
- <0 0x0b290000 0 0x10000>;
- reg-names = "gmu", "rscc", "gmu_pdc";
- interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hfi", "gmu";
- clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
- <&gpucc GPU_CC_CXO_CLK>,
- <&gcc GCC_DDRSS_GPU_AXI_CLK>,
- <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
- <&gpucc GPU_CC_AHB_CLK>,
- <&gpucc GPU_CC_HUB_CX_INT_CLK>,
- <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
- clock-names = "gmu",
- "cxo",
- "axi",
- "memnoc",
- "ahb",
- "hub",
- "smmu_vote";
- power-domains = <&gpucc GPU_CC_CX_GDSC>,
- <&gpucc GPU_CC_GX_GDSC>;
- power-domain-names = "cx",
- "gx";
- iommus = <&gpu_smmu 5 0xc00>;
- operating-points-v2 = <&gmu_opp_table>;
-
- gmu_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
- };
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
- };
- };
- };
-
- gpucc: clock-controller@3d90000 {
- compatible = "qcom,sc8280xp-gpucc";
- reg = <0 0x03d90000 0 0x9000>;
- clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_GPU_GPLL0_CLK_SRC>,
- <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
- clock-names = "bi_tcxo",
- "gcc_gpu_gpll0_clk_src",
- "gcc_gpu_gpll0_div_clk_src";
-
- power-domains = <&rpmhpd SC8280XP_GFX>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
-
- gpu_smmu: iommu@3da0000 {
- compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
- "qcom,smmu-500", "arm,mmu-500";
- reg = <0 0x03da0000 0 0x20000>;
- #iommu-cells = <2>;
- #global-interrupts = <2>;
- interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
-
- clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
- <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
- <&gpucc GPU_CC_AHB_CLK>,
- <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
- <&gpucc GPU_CC_CX_GMU_CLK>,
- <&gpucc GPU_CC_HUB_CX_INT_CLK>,
- <&gpucc GPU_CC_HUB_AON_CLK>;
- clock-names = "gcc_gpu_memnoc_gfx_clk",
- "gcc_gpu_snoc_dvm_gfx_clk",
- "gpu_cc_ahb_clk",
- "gpu_cc_hlos1_vote_gpu_smmu_clk",
- "gpu_cc_cx_gmu_clk",
- "gpu_cc_hub_cx_int_clk",
- "gpu_cc_hub_aon_clk";
-
- power-domains = <&gpucc GPU_CC_CX_GDSC>;
- dma-coherent;
- };
-
- usb_0_hsphy: phy@88e5000 {
- compatible = "qcom,sc8280xp-usb-hs-phy",
- "qcom,usb-snps-hs-5nm-phy";
- reg = <0 0x088e5000 0 0x400>;
- clocks = <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "ref";
- resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- usb_2_hsphy0: phy@88e7000 {
- compatible = "qcom,sc8280xp-usb-hs-phy",
- "qcom,usb-snps-hs-5nm-phy";
- reg = <0 0x088e7000 0 0x400>;
- clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
- clock-names = "ref";
- resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- usb_2_hsphy1: phy@88e8000 {
- compatible = "qcom,sc8280xp-usb-hs-phy",
- "qcom,usb-snps-hs-5nm-phy";
- reg = <0 0x088e8000 0 0x400>;
- clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
- clock-names = "ref";
- resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- usb_2_hsphy2: phy@88e9000 {
- compatible = "qcom,sc8280xp-usb-hs-phy",
- "qcom,usb-snps-hs-5nm-phy";
- reg = <0 0x088e9000 0 0x400>;
- clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
- clock-names = "ref";
- resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- usb_2_hsphy3: phy@88ea000 {
- compatible = "qcom,sc8280xp-usb-hs-phy",
- "qcom,usb-snps-hs-5nm-phy";
- reg = <0 0x088ea000 0 0x400>;
- clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
- clock-names = "ref";
- resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- usb_2_qmpphy0: phy@88ef000 {
- compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
- reg = <0 0x088ef000 0 0x2000>;
-
- clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
- <&gcc GCC_USB3_MP0_CLKREF_CLK>,
- <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
- <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
- clock-names = "aux", "ref", "com_aux", "pipe";
-
- resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
- <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
- reset-names = "phy", "phy_phy";
-
- power-domains = <&gcc USB30_MP_GDSC>;
-
- #clock-cells = <0>;
- clock-output-names = "usb2_phy0_pipe_clk";
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
- usb_2_qmpphy1: phy@88f1000 {
- compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
- reg = <0 0x088f1000 0 0x2000>;
-
- clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
- <&gcc GCC_USB3_MP1_CLKREF_CLK>,
- <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
- <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
- clock-names = "aux", "ref", "com_aux", "pipe";
-
- resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
- <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
- reset-names = "phy", "phy_phy";
-
- power-domains = <&gcc USB30_MP_GDSC>;
-
- #clock-cells = <0>;
- clock-output-names = "usb2_phy1_pipe_clk";
-
- #phy-cells = <0>;
-
- status = "disabled";
- };
-
remoteproc_adsp: remoteproc@3000000 {
compatible = "qcom,sc8280xp-adsp-pas";
reg = <0 0x03000000 0 0x10000>;
@@ -3166,6 +2879,180 @@ lpasscc: clock-controller@33e0000 {
#reset-cells = <1>;
};
+ gpu: gpu@3d00000 {
+ compatible = "qcom,adreno-690.0", "qcom,adreno";
+
+ reg = <0 0x03d00000 0 0x40000>,
+ <0 0x03d9e000 0 0x1000>,
+ <0 0x03d61000 0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
+ operating-points-v2 = <&gpu_opp_table>;
+
+ qcom,gmu = <&gmu>;
+ interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "gfx-mem";
+ #cooling-cells = <2>;
+
+ status = "disabled";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-peak-kBps = <451000>;
+ };
+
+ opp-410000000 {
+ opp-hz = /bits/ 64 <410000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-peak-kBps = <1555000>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <1555000>;
+ };
+
+ opp-547000000 {
+ opp-hz = /bits/ 64 <547000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ opp-peak-kBps = <1555000>;
+ };
+
+ opp-606000000 {
+ opp-hz = /bits/ 64 <606000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-peak-kBps = <2736000>;
+ };
+
+ opp-640000000 {
+ opp-hz = /bits/ 64 <640000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ opp-peak-kBps = <2736000>;
+ };
+
+ opp-655000000 {
+ opp-hz = /bits/ 64 <655000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ opp-peak-kBps = <2736000>;
+ };
+
+ opp-690000000 {
+ opp-hz = /bits/ 64 <690000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ opp-peak-kBps = <2736000>;
+ };
+ };
+ };
+
+ gmu: gmu@3d6a000 {
+ compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
+ reg = <0 0x03d6a000 0 0x34000>,
+ <0 0x03de0000 0 0x10000>,
+ <0 0x0b290000 0 0x10000>;
+ reg-names = "gmu", "rscc", "gmu_pdc";
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+ clock-names = "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "ahb",
+ "hub",
+ "smmu_vote";
+ power-domains = <&gpucc GPU_CC_CX_GDSC>,
+ <&gpucc GPU_CC_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+ iommus = <&gpu_smmu 5 0xc00>;
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+ };
+ };
+
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,sc8280xp-gpucc";
+ reg = <0 0x03d90000 0 0x9000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ clock-names = "bi_tcxo",
+ "gcc_gpu_gpll0_clk_src",
+ "gcc_gpu_gpll0_div_clk_src";
+
+ power-domains = <&rpmhpd SC8280XP_GFX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ gpu_smmu: iommu@3da0000 {
+ compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
+ "qcom,smmu-500", "arm,mmu-500";
+ reg = <0 0x03da0000 0 0x20000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HUB_AON_CLK>;
+ clock-names = "gcc_gpu_memnoc_gfx_clk",
+ "gcc_gpu_snoc_dvm_gfx_clk",
+ "gpu_cc_ahb_clk",
+ "gpu_cc_hlos1_vote_gpu_smmu_clk",
+ "gpu_cc_cx_gmu_clk",
+ "gpu_cc_hub_cx_int_clk",
+ "gpu_cc_hub_aon_clk";
+
+ power-domains = <&gpucc GPU_CC_CX_GDSC>;
+ dma-coherent;
+ };
+
sdc2: mmc@8804000 {
compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
@@ -3209,6 +3096,71 @@ opp-202000000 {
};
};
+ usb_0_hsphy: phy@88e5000 {
+ compatible = "qcom,sc8280xp-usb-hs-phy",
+ "qcom,usb-snps-hs-5nm-phy";
+ reg = <0 0x088e5000 0 0x400>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_2_hsphy0: phy@88e7000 {
+ compatible = "qcom,sc8280xp-usb-hs-phy",
+ "qcom,usb-snps-hs-5nm-phy";
+ reg = <0 0x088e7000 0 0x400>;
+ clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
+ clock-names = "ref";
+ resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_2_hsphy1: phy@88e8000 {
+ compatible = "qcom,sc8280xp-usb-hs-phy",
+ "qcom,usb-snps-hs-5nm-phy";
+ reg = <0 0x088e8000 0 0x400>;
+ clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
+ clock-names = "ref";
+ resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_2_hsphy2: phy@88e9000 {
+ compatible = "qcom,sc8280xp-usb-hs-phy",
+ "qcom,usb-snps-hs-5nm-phy";
+ reg = <0 0x088e9000 0 0x400>;
+ clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
+ clock-names = "ref";
+ resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_2_hsphy3: phy@88ea000 {
+ compatible = "qcom,sc8280xp-usb-hs-phy",
+ "qcom,usb-snps-hs-5nm-phy";
+ reg = <0 0x088ea000 0 0x400>;
+ clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
+ clock-names = "ref";
+ resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
usb_0_qmpphy: phy@88eb000 {
compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
reg = <0 0x088eb000 0 0x4000>;
@@ -3256,6 +3208,54 @@ port@2 {
};
};
+ usb_2_qmpphy0: phy@88ef000 {
+ compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
+ reg = <0 0x088ef000 0 0x2000>;
+
+ clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
+ <&gcc GCC_USB3_MP0_CLKREF_CLK>,
+ <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
+ clock-names = "aux", "ref", "com_aux", "pipe";
+
+ resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
+ <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
+ reset-names = "phy", "phy_phy";
+
+ power-domains = <&gcc USB30_MP_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "usb2_phy0_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_2_qmpphy1: phy@88f1000 {
+ compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
+ reg = <0 0x088f1000 0 0x2000>;
+
+ clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
+ <&gcc GCC_USB3_MP1_CLKREF_CLK>,
+ <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
+ clock-names = "aux", "ref", "com_aux", "pipe";
+
+ resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
+ <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
+ reset-names = "phy", "phy_phy";
+
+ power-domains = <&gcc USB30_MP_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "usb2_phy1_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
usb_1_hsphy: phy@8902000 {
compatible = "qcom,sc8280xp-usb-hs-phy",
"qcom,usb-snps-hs-5nm-phy";
--
2.49.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2 3/5] arm64: dts: qcom: sc8280xp: Add SLPI
2025-05-17 17:27 [PATCH v2 0/5] SC8280XP SLPI Konrad Dybcio
2025-05-17 17:27 ` [PATCH v2 1/5] dt-bindings: remoteproc: qcom,sm8350-pas: Add SC8280XP Konrad Dybcio
2025-05-17 17:27 ` [PATCH v2 2/5] arm64: dts: qcom: sc8280xp: Fix node order Konrad Dybcio
@ 2025-05-17 17:27 ` Konrad Dybcio
2025-05-18 10:58 ` Dmitry Baryshkov
2025-05-17 17:27 ` [PATCH v2 4/5] arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13s: enable sensors DSP Konrad Dybcio
` (3 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Konrad Dybcio @ 2025-05-17 17:27 UTC (permalink / raw)
To: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Konrad Dybcio
Cc: Marijn Suijten, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
SC8280XP features a SLPI (Sensor Low Power Island) core. Describe it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 99 ++++++++++++++++++++++++++++++++++
1 file changed, 99 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 94dcbccca62e992030bcdd6eb3bc3fcd879c1e8a..87555a119d947dca75415675807f7965b2f203ac 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -695,6 +695,11 @@ pil_adsp_mem: adsp-region@86c00000 {
no-map;
};
+ pil_slpi_mem: slpi-region@88c00000 {
+ reg = <0 0x88c00000 0 0x1500000>;
+ no-map;
+ };
+
pil_nsp0_mem: cdsp0-region@8a100000 {
reg = <0 0x8a100000 0 0x1e00000>;
no-map;
@@ -783,6 +788,30 @@ smp2p_nsp1_in: slave-kernel {
};
};
+ smp2p-slpi {
+ compatible = "qcom,smp2p";
+ qcom,smem = <481>, <430>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_SLPI
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <3>;
+
+ smp2p_slpi_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_slpi_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
@@ -2454,6 +2483,76 @@ tcsr: syscon@1fc0000 {
reg = <0x0 0x01fc0000 0x0 0x30000>;
};
+ remoteproc_slpi: remoteproc@2400000 {
+ compatible = "qcom,sc8280xp-slpi-pas", "qcom,sm8350-slpi-pas";
+ reg = <0 0x02400000 0 0x10000>;
+
+ interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SC8280XP_LCX>,
+ <&rpmhpd SC8280XP_LMX>;
+ power-domain-names = "lcx", "lmx";
+
+ memory-region = <&pil_slpi_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_slpi_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_SLPI
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "slpi";
+ qcom,remote-pid = <3>;
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "sdsp";
+ qcom,non-secure-domain;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+ iommus = <&apps_smmu 0x0521 0x0>;
+ };
+
+ compute-cb@2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+ iommus = <&apps_smmu 0x0522 0x0>;
+ };
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x0523 0x0>;
+ };
+ };
+ };
+ };
+
remoteproc_adsp: remoteproc@3000000 {
compatible = "qcom,sc8280xp-adsp-pas";
reg = <0 0x03000000 0 0x10000>;
--
2.49.0
^ permalink raw reply related [flat|nested] 14+ messages in thread