Linux Renesas SOC kernel development
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From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: linus.walleij@linaro.org, linux-renesas-soc@vger.kernel.org,
	laurent.pinchart@ideasonboard.com, linux-gpio@vger.kernel.org,
	geert+renesas@glider.be
Subject: [PATCH] pinctrl: sh-pfc: r8a7792: add DU pin groups
Date: Sat, 03 Sep 2016 00:49:14 +0300	[thread overview]
Message-ID: <1497777.FvT8ieIrQm@wasted.cogentembedded.com> (raw)
In-Reply-To: <1501145.5ro9yfox2Z@wasted.cogentembedded.com>

Add QSPI pin groups to the R8A7792 PFC driver.

Based  on the original (and large) patch by Vladimir Barinov
<vladimir.barinov@cogentembedded.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
The patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git'
repo...

 drivers/pinctrl/sh-pfc/pfc-r8a7792.c |   33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

Index: linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
===================================================================
--- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
+++ linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
@@ -1034,6 +1034,29 @@ static const unsigned int lbsc_ex_cs5_pi
 static const unsigned int lbsc_ex_cs5_mux[] = {
 	EX_CS5_N_MARK,
 };
+/* - QSPI ------------------------------------------------------------------- */
+static const unsigned int qspi_ctrl_pins[] = {
+	/* SPCLK, SSL */
+	RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
+};
+static const unsigned int qspi_ctrl_mux[] = {
+	SPCLK_MARK, SSL_MARK,
+};
+static const unsigned int qspi_data2_pins[] = {
+	/* MOSI_IO0, MISO_IO1 */
+	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+};
+static const unsigned int qspi_data2_mux[] = {
+	MOSI_IO0_MARK, MISO_IO1_MARK,
+};
+static const unsigned int qspi_data4_pins[] = {
+	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
+	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
+	RCAR_GP_PIN(3, 24),
+};
+static const unsigned int qspi_data4_mux[] = {
+	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK,	IO3_MARK,
+};
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
 	/* RX, TX */
@@ -1585,6 +1608,9 @@ static const struct sh_pfc_pin_group pin
 	SH_PFC_PIN_GROUP(lbsc_ex_cs3),
 	SH_PFC_PIN_GROUP(lbsc_ex_cs4),
 	SH_PFC_PIN_GROUP(lbsc_ex_cs5),
+	SH_PFC_PIN_GROUP(qspi_ctrl),
+	SH_PFC_PIN_GROUP(qspi_data2),
+	SH_PFC_PIN_GROUP(qspi_data4),
 	SH_PFC_PIN_GROUP(scif0_data),
 	SH_PFC_PIN_GROUP(scif0_clk),
 	SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -1708,6 +1734,12 @@ static const char * const lbsc_groups[]
 	"lbsc_ex_cs5",
 };
 
+static const char * const qspi_groups[] = {
+	"qspi_ctrl",
+	"qspi_data2",
+	"qspi_data4",
+};
+
 static const char * const scif0_groups[] = {
 	"scif0_data",
 	"scif0_clk",
@@ -1808,6 +1840,7 @@ static const struct sh_pfc_function pinm
 	SH_PFC_FUNCTION(du1),
 	SH_PFC_FUNCTION(intc),
 	SH_PFC_FUNCTION(lbsc),
+	SH_PFC_FUNCTION(qspi),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif3),
 	SH_PFC_FUNCTION(sdhi0),

  parent reply	other threads:[~2016-09-02 21:49 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1501145.5ro9yfox2Z@wasted.cogentembedded.com>
2016-07-04 19:52 ` [PATCH] pinctrl: sh-pfc: r8a7792: add EtherAVB pin groups Sergei Shtylyov
2016-07-05  6:57   ` Geert Uytterhoeven
2016-07-05 11:00     ` Sergei Shtylyov
2016-07-05 14:54     ` Linus Walleij
2016-07-05 15:46       ` Geert Uytterhoeven
2016-07-05 21:14         ` Linus Walleij
2016-07-06 17:18           ` Sergei Shtylyov
2016-07-05 21:53 ` [PATCH] gpio: rcar: document R8A7792 support Sergei Shtylyov
2016-07-07 11:10   ` Sergei Shtylyov
2016-07-07 14:11 ` [PATCH] gpio: rcar: add " Sergei Shtylyov
2016-07-11  7:49   ` Linus Walleij
2016-07-12 21:38 ` [PATCH v2] pinctrl: sh-pfc: r8a7792: add EtherAVB pin groups Sergei Shtylyov
2016-07-13  6:13   ` Geert Uytterhoeven
2016-07-14 12:09     ` Sergei Shtylyov
2016-07-12 21:40 ` [PATCH] pinctrl: sh-pfc: r8a7792: add SDHI " Sergei Shtylyov
2016-07-13  6:17   ` Geert Uytterhoeven
2016-08-04  7:44   ` Linus Walleij
2016-07-14 19:51 ` [PATCH] pinctrl: sh-pfc: r8a7792: add CAN " Sergei Shtylyov
2016-07-18  9:25   ` Geert Uytterhoeven
2016-07-22 13:51 ` [PATCH] pinctrl: sh-pfc: r8a7792: add missing pinmux data Sergei Shtylyov
2016-08-04  8:04   ` Linus Walleij
2016-08-04 13:39     ` Sergei Shtylyov
2016-08-08 10:32       ` Geert Uytterhoeven
2016-07-22 22:24 ` [PATCH] pinctrl: sh-pfc: r8a7792: add VIN pin groups Sergei Shtylyov
2016-08-03 19:51   ` Sergei Shtylyov
2016-08-05 20:52 ` [PATCH v2] " Sergei Shtylyov
2016-08-08 11:46   ` Geert Uytterhoeven
2016-08-05 20:54 ` [PATCH] pinctrl: sh-pfc: r8a7792: add DU " Sergei Shtylyov
2016-08-08 12:06   ` Geert Uytterhoeven
2016-09-02 21:49 ` Sergei Shtylyov [this message]
2016-09-02 21:50 ` [PATCH resend] pinctrl: sh-pfc: r8a7792: add QSPI " Sergei Shtylyov
2016-09-05  9:00   ` Geert Uytterhoeven
2016-09-07 21:49   ` Linus Walleij
2016-09-05 20:17 ` [PATCH] pinctrl: sh-pfc: r8a7792: add MSIOF " Sergei Shtylyov
2016-09-06  7:02   ` Geert Uytterhoeven

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