[PATCH v2] RISC-V: KVM: Fix csr_write -> csr_set for HVIEN PMU overflow bit

[PATCH v2] RISC-V: KVM: Fix csr_write -> csr_set for HVIEN PMU overflow bit

[Michael Neuling]

This doesn't cause a problem currently as HVIEN isn't used elsewhere
yet. Found by inspection.

Signed-off-by: Michael Neuling <michaelneuling@tenstorrent.com>
Fixes: 16b0bde9a37c ("RISC-V: KVM: Add perf sampling support for guests")
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
v2:
  Added Fixes tag
  Added Reviews
  No code change
---
 arch/riscv/kvm/aia.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/kvm/aia.c b/arch/riscv/kvm/aia.c
index 2967d305c4..9f3b527596 100644
--- a/arch/riscv/kvm/aia.c
+++ b/arch/riscv/kvm/aia.c
@@ -552,7 +552,7 @@ void kvm_riscv_aia_enable(void)
 	csr_set(CSR_HIE, BIT(IRQ_S_GEXT));
 	/* Enable IRQ filtering for overflow interrupt only if sscofpmf is present */
 	if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSCOFPMF))
-		csr_write(CSR_HVIEN, BIT(IRQ_PMU_OVF));
+		csr_set(CSR_HVIEN, BIT(IRQ_PMU_OVF));
 }
 
 void kvm_riscv_aia_disable(void)
-- 
2.34.1


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Re: [PATCH v2] RISC-V: KVM: Fix csr_write -> csr_set for HVIEN PMU overflow bit

[Anup Patel]

On Wed, Nov 27, 2024 at 9:49 AM Michael Neuling
<michaelneuling@tenstorrent.com> wrote:
>
> This doesn't cause a problem currently as HVIEN isn't used elsewhere
> yet. Found by inspection.
>
> Signed-off-by: Michael Neuling <michaelneuling@tenstorrent.com>
> Fixes: 16b0bde9a37c ("RISC-V: KVM: Add perf sampling support for guests")
> Reviewed-by: Atish Patra <atishp@rivosinc.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>

Queued for 6.13-rcX fixes

Regards,
Anup

> ---
> v2:
>   Added Fixes tag
>   Added Reviews
>   No code change
> ---
>  arch/riscv/kvm/aia.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kvm/aia.c b/arch/riscv/kvm/aia.c
> index 2967d305c4..9f3b527596 100644
> --- a/arch/riscv/kvm/aia.c
> +++ b/arch/riscv/kvm/aia.c
> @@ -552,7 +552,7 @@ void kvm_riscv_aia_enable(void)
>         csr_set(CSR_HIE, BIT(IRQ_S_GEXT));
>         /* Enable IRQ filtering for overflow interrupt only if sscofpmf is present */
>         if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSCOFPMF))
> -               csr_write(CSR_HVIEN, BIT(IRQ_PMU_OVF));
> +               csr_set(CSR_HVIEN, BIT(IRQ_PMU_OVF));
>  }
>
>  void kvm_riscv_aia_disable(void)
> --
> 2.34.1
>

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Re: [PATCH v2] RISC-V: KVM: Fix csr_write -> csr_set for HVIEN PMU overflow bit

[patchwork-bot+linux-riscv]

Hello:

This patch was applied to riscv/linux.git (fixes)
by Anup Patel <anup@brainfault.org>:

On Wed, 27 Nov 2024 04:18:40 +0000 you wrote:
> This doesn't cause a problem currently as HVIEN isn't used elsewhere
> yet. Found by inspection.
> 
> Signed-off-by: Michael Neuling <michaelneuling@tenstorrent.com>
> Fixes: 16b0bde9a37c ("RISC-V: KVM: Add perf sampling support for guests")
> Reviewed-by: Atish Patra <atishp@rivosinc.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> 
> [...]

Here is the summary with links:
  - [v2] RISC-V: KVM: Fix csr_write -> csr_set for HVIEN PMU overflow bit
    https://git.kernel.org/riscv/c/ea6398a5af81

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html



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