* [PATCH v1] dt-bindings: cache: sifive,ccache0: add a pic64gx compatible
@ 2025-11-17 14:24 Conor Dooley
2025-11-17 22:49 ` Rob Herring (Arm)
0 siblings, 1 reply; 2+ messages in thread
From: Conor Dooley @ 2025-11-17 14:24 UTC (permalink / raw)
To: linux-kernel
Cc: conor, Pierre-Henry Moussay, Conor Dooley, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Samuel Holland, devicetree,
linux-riscv
From: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
The pic64gx use the same IP than mpfs, therefore add compatibility with
mpfs as fallback.
Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
CC: Conor Dooley <conor@kernel.org>
CC: Rob Herring <robh@kernel.org>
CC: Krzysztof Kozlowski <krzk+dt@kernel.org>
CC: Paul Walmsley <pjw@kernel.org>
CC: Samuel Holland <samuel.holland@sifive.com>
CC: devicetree@vger.kernel.org
CC: linux-riscv@lists.infradead.org
CC: linux-kernel@vger.kernel.org
Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
index 579bacb66f34..c0e5ebb1fa4c 100644
--- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
@@ -48,6 +48,11 @@ properties:
- const: microchip,mpfs-ccache
- const: sifive,fu540-c000-ccache
- const: cache
+ - items:
+ - const: microchip,pic64gx-ccache
+ - const: microchip,mpfs-ccache
+ - const: sifive,fu540-c000-ccache
+ - const: cache
cache-block-size:
const: 64
--
2.51.0
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v1] dt-bindings: cache: sifive,ccache0: add a pic64gx compatible
2025-11-17 14:24 [PATCH v1] dt-bindings: cache: sifive,ccache0: add a pic64gx compatible Conor Dooley
@ 2025-11-17 22:49 ` Rob Herring (Arm)
0 siblings, 0 replies; 2+ messages in thread
From: Rob Herring (Arm) @ 2025-11-17 22:49 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-riscv, Krzysztof Kozlowski, Samuel Holland, Conor Dooley,
linux-kernel, devicetree, Pierre-Henry Moussay, Paul Walmsley
On Mon, 17 Nov 2025 14:24:37 +0000, Conor Dooley wrote:
> From: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
>
> The pic64gx use the same IP than mpfs, therefore add compatibility with
> mpfs as fallback.
>
> Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> CC: Conor Dooley <conor@kernel.org>
> CC: Rob Herring <robh@kernel.org>
> CC: Krzysztof Kozlowski <krzk+dt@kernel.org>
> CC: Paul Walmsley <pjw@kernel.org>
> CC: Samuel Holland <samuel.holland@sifive.com>
> CC: devicetree@vger.kernel.org
> CC: linux-riscv@lists.infradead.org
> CC: linux-kernel@vger.kernel.org
> Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
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