[PATCH] RISC-V: Fix up some vector state related build failures

[PATCH] RISC-V: Fix up some vector state related build failures

[Palmer Dabbelt]

I get a few build failures along the lines of

./arch/riscv/include/uapi/asm/sigcontext.h:19:36: error: field ‘v_state’ has incomplete type
   19 |         struct __riscv_v_ext_state v_state;
      |                                    ^~~~~~~
./arch/riscv/include/uapi/asm/sigcontext.h:32:49: error: field ‘sc_extdesc’ has incomplete type
   32 |                 struct __riscv_extra_ext_header sc_extdesc;

The V structures in question are defined for !assembly, so let's just do
so for the others.

Fixes: 8ee0b41898fa ("riscv: signal: Add sigcontext save/restore for vector")
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 arch/riscv/include/uapi/asm/sigcontext.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/include/uapi/asm/sigcontext.h b/arch/riscv/include/uapi/asm/sigcontext.h
index 8b8a8541673a..8c8712aa9551 100644
--- a/arch/riscv/include/uapi/asm/sigcontext.h
+++ b/arch/riscv/include/uapi/asm/sigcontext.h
@@ -15,6 +15,8 @@
 /* The size of END signal context header. */
 #define END_HDR_SIZE	0x0
 
+#ifndef __ASSEMBLY__
+
 struct __sc_riscv_v_state {
 	struct __riscv_v_ext_state v_state;
 } __attribute__((aligned(16)));
@@ -33,4 +35,6 @@ struct sigcontext {
 	};
 };
 
+#endif /*!__ASSEMBLY__*/
+
 #endif /* _UAPI_ASM_RISCV_SIGCONTEXT_H */
-- 
2.40.1


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Re: [PATCH] RISC-V: Fix up some vector state related build failures

[Conor Dooley]

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On Mon, Jun 19, 2023 at 10:21:01AM -0700, Palmer Dabbelt wrote:
> I get a few build failures along the lines of
> 
> ./arch/riscv/include/uapi/asm/sigcontext.h:19:36: error: field ‘v_state’ has incomplete type
>    19 |         struct __riscv_v_ext_state v_state;
>       |                                    ^~~~~~~
> ./arch/riscv/include/uapi/asm/sigcontext.h:32:49: error: field ‘sc_extdesc’ has incomplete type
>    32 |                 struct __riscv_extra_ext_header sc_extdesc;
> 
> The V structures in question are defined for !assembly, so let's just do
> so for the others.
> 
> Fixes: 8ee0b41898fa ("riscv: signal: Add sigcontext save/restore for vector")
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

Not the first time you've caught this sort of problem in headers, is
there a particular build that catches these?

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

> ---
>  arch/riscv/include/uapi/asm/sigcontext.h | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/riscv/include/uapi/asm/sigcontext.h b/arch/riscv/include/uapi/asm/sigcontext.h
> index 8b8a8541673a..8c8712aa9551 100644
> --- a/arch/riscv/include/uapi/asm/sigcontext.h
> +++ b/arch/riscv/include/uapi/asm/sigcontext.h
> @@ -15,6 +15,8 @@
>  /* The size of END signal context header. */
>  #define END_HDR_SIZE	0x0
>  
> +#ifndef __ASSEMBLY__
> +
>  struct __sc_riscv_v_state {
>  	struct __riscv_v_ext_state v_state;
>  } __attribute__((aligned(16)));
> @@ -33,4 +35,6 @@ struct sigcontext {
>  	};
>  };
>  
> +#endif /*!__ASSEMBLY__*/
> +
>  #endif /* _UAPI_ASM_RISCV_SIGCONTEXT_H */
> -- 
> 2.40.1
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

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Re: [PATCH] RISC-V: Fix up some vector state related build failures

[Palmer Dabbelt]

On Tue, 20 Jun 2023 00:33:57 PDT (-0700), Conor Dooley wrote:
> On Mon, Jun 19, 2023 at 10:21:01AM -0700, Palmer Dabbelt wrote:
>> I get a few build failures along the lines of
>>
>> ./arch/riscv/include/uapi/asm/sigcontext.h:19:36: error: field ‘v_state’ has incomplete type
>>    19 |         struct __riscv_v_ext_state v_state;
>>       |                                    ^~~~~~~
>> ./arch/riscv/include/uapi/asm/sigcontext.h:32:49: error: field ‘sc_extdesc’ has incomplete type
>>    32 |                 struct __riscv_extra_ext_header sc_extdesc;
>>
>> The V structures in question are defined for !assembly, so let's just do
>> so for the others.
>>
>> Fixes: 8ee0b41898fa ("riscv: signal: Add sigcontext save/restore for vector")
>> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
>
> Not the first time you've caught this sort of problem in headers, is
> there a particular build that catches these?

I think we're missing some sort of dependency somewhere, these 
assembly-related issues tend to only show up once when I'm doing dirty 
builds.  I'd guess it's because I'm bouncing between trees and such, not 
100% sure though.

>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> Cheers,
> Conor.
>
>> ---
>>  arch/riscv/include/uapi/asm/sigcontext.h | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/riscv/include/uapi/asm/sigcontext.h b/arch/riscv/include/uapi/asm/sigcontext.h
>> index 8b8a8541673a..8c8712aa9551 100644
>> --- a/arch/riscv/include/uapi/asm/sigcontext.h
>> +++ b/arch/riscv/include/uapi/asm/sigcontext.h
>> @@ -15,6 +15,8 @@
>>  /* The size of END signal context header. */
>>  #define END_HDR_SIZE	0x0
>>
>> +#ifndef __ASSEMBLY__
>> +
>>  struct __sc_riscv_v_state {
>>  	struct __riscv_v_ext_state v_state;
>>  } __attribute__((aligned(16)));
>> @@ -33,4 +35,6 @@ struct sigcontext {
>>  	};
>>  };
>>
>> +#endif /*!__ASSEMBLY__*/
>> +
>>  #endif /* _UAPI_ASM_RISCV_SIGCONTEXT_H */
>> --
>> 2.40.1
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

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Re: [PATCH] RISC-V: Fix up some vector state related build failures

[patchwork-bot+linux-riscv]

Hello:

This patch was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Mon, 19 Jun 2023 10:21:01 -0700 you wrote:
> I get a few build failures along the lines of
> 
> ./arch/riscv/include/uapi/asm/sigcontext.h:19:36: error: field ‘v_state’ has incomplete type
>    19 |         struct __riscv_v_ext_state v_state;
>       |                                    ^~~~~~~
> ./arch/riscv/include/uapi/asm/sigcontext.h:32:49: error: field ‘sc_extdesc’ has incomplete type
>    32 |                 struct __riscv_extra_ext_header sc_extdesc;
> 
> [...]

Here is the summary with links:
  - RISC-V: Fix up some vector state related build failures
    https://git.kernel.org/riscv/c/e50db34efdc8

You are awesome, thank you!
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