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From: Conor Dooley <conor.dooley@microchip.com>
To: Andy Chiu <andy.chiu@sifive.com>
Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
	vineetg@rivosinc.com, bjorn@kernel.org, greentime.hu@sifive.com,
	paul.walmsley@sifive.com, guoren@linux.alibaba.com,
	anup@brainfault.org, atishp@atishpatra.org,
	heiko.stuebner@vrull.eu, "Albert Ou" <aou@eecs.berkeley.edu>,
	"Oleg Nesterov" <oleg@redhat.com>, "Guo Ren" <guoren@kernel.org>,
	"Yipeng Zou" <zouyipeng@huawei.com>,
	"Huacai Chen" <chenhuacai@kernel.org>,
	"Vincent Chen" <vincent.chen@sifive.com>,
	"Björn Töpel" <bjorn@rivosinc.com>,
	"Mathis Salmen" <mathis.salmen@matsal.de>,
	"Andrew Bresticker" <abrestic@rivosinc.com>
Subject: Re: [v1, 4/6] riscv: vector: do not pass task_struct into riscv_v_vstate_{save,restore}()
Date: Mon, 17 Jul 2023 11:32:29 +0100	[thread overview]
Message-ID: <20230717-igloo-poncho-ede3baa98110@wendy> (raw)
In-Reply-To: <20230715150032.6917-5-andy.chiu@sifive.com>


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On Sat, Jul 15, 2023 at 03:00:30PM +0000, Andy Chiu wrote:
> riscv_v_vstate_{save,restore}() can operate only on the knowlege of
> struct __riscv_v_ext_state, and struct pt_regs. Let the caller decides
> which should be passed into the function. Meanwhile, the kernel-mode
> Vector is going to introduce another vstate, so this also makes functions
> potentially able to be reused.
> 
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>

Breaks the build chief:
../arch/riscv/include/asm/vector.h:199:41: error: incompatible type for argument 1 of 'riscv_v_vstate_save'
../arch/riscv/include/asm/vector.h:199:41: error: incompatible type for argument 1 of 'riscv_v_vstate_save'
../arch/riscv/include/asm/vector.h:199:41: error: incompatible type for argument 1 of 'riscv_v_vstate_save'
../arch/riscv/include/asm/vector.h:199:41: error: incompatible type for argument 1 of 'riscv_v_vstate_save'
../arch/riscv/include/asm/vector.h:199:41: error: incompatible type for argument 1 of 'riscv_v_vstate_save'
../arch/riscv/include/asm/vector.h:199:41: error: incompatible type for argument 1 of 'riscv_v_vstate_save'
../arch/riscv/include/asm/vector.h:199:41: error: incompatible type for argument 1 of 'riscv_v_vstate_save'
../arch/riscv/include/asm/vector.h:199:41: error: incompatible type for argument 1 of 'riscv_v_vstate_save'
../arch/riscv/include/asm/vector.h:199:41: error: incompatible type for argument 1 of 'riscv_v_vstate_save'
../arch/riscv/include/asm/vector.h:199:41: error: incompatible type for argument 1 of 'riscv_v_vstate_save'
../arch/riscv/include/asm/vector.h:199:41: error: incompatible type for argument 1 of 'riscv_v_vstate_save'
../arch/riscv/include/asm/vector.h:199:41: error: incompatible type for argument 1 of 'riscv_v_vstate_save'
../arch/riscv/include/asm/vector.h:199:41: error: incompatible type for argument 1 of 'riscv_v_vstate_save'
../arch/riscv/include/asm/vector.h:199:41: error: incompatible type for argument 1 of 'riscv_v_vstate_save'
../arch/riscv/include/asm/vector.h:199:41: error: incompatible type for argument 1 of 'riscv_v_vstate_save'
../arch/riscv/include/asm/vector.h:199:41: error: incompatible type for argument 1 of 'riscv_v_vstate_save'
../arch/riscv/include/asm/vector.h:199:41: error: incompatible type for argument 1 of 'riscv_v_vstate_save'
../arch/riscv/include/asm/vector.h:199:41: error: incompatible type for argument 1 of 'riscv_v_vstate_save'

rv64 allmodconfig w/ gcc.

Thanks,
Conor.

> ---
>  arch/riscv/include/asm/entry-common.h  |  2 +-
>  arch/riscv/include/asm/vector.h        | 14 +++++---------
>  arch/riscv/kernel/kernel_mode_vector.c |  2 +-
>  arch/riscv/kernel/ptrace.c             |  2 +-
>  arch/riscv/kernel/signal.c             |  2 +-
>  5 files changed, 9 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h
> index 52926f4d8d7c..aa1b9e50d6c8 100644
> --- a/arch/riscv/include/asm/entry-common.h
> +++ b/arch/riscv/include/asm/entry-common.h
> @@ -12,7 +12,7 @@ static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs,
>  {
>  	if (ti_work & _TIF_RISCV_V_DEFER_RESTORE) {
>  		clear_thread_flag(TIF_RISCV_V_DEFER_RESTORE);
> -		riscv_v_vstate_restore(current, regs);
> +		riscv_v_vstate_restore(&current->thread.vstate, regs);
>  	}
>  }
>  
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> index 9831b19153ae..50c556afd95a 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -163,23 +163,19 @@ static inline void riscv_v_vstate_discard(struct pt_regs *regs)
>  	__riscv_v_vstate_dirty(regs);
>  }
>  
> -static inline void riscv_v_vstate_save(struct task_struct *task,
> +static inline void riscv_v_vstate_save(struct __riscv_v_ext_state *vstate,
>  				       struct pt_regs *regs)
>  {
>  	if ((regs->status & SR_VS) == SR_VS_DIRTY) {
> -		struct __riscv_v_ext_state *vstate = &task->thread.vstate;
> -
>  		__riscv_v_vstate_save(vstate, vstate->datap);
>  		__riscv_v_vstate_clean(regs);
>  	}
>  }
>  
> -static inline void riscv_v_vstate_restore(struct task_struct *task,
> +static inline void riscv_v_vstate_restore(struct __riscv_v_ext_state *vstate,
>  					  struct pt_regs *regs)
>  {
>  	if ((regs->status & SR_VS) != SR_VS_OFF) {
> -		struct __riscv_v_ext_state *vstate = &task->thread.vstate;
> -
>  		__riscv_v_vstate_restore(vstate, vstate->datap);
>  		__riscv_v_vstate_clean(regs);
>  	}
> @@ -200,7 +196,7 @@ static inline void __switch_to_vector(struct task_struct *prev,
>  	struct pt_regs *regs;
>  
>  	regs = task_pt_regs(prev);
> -	riscv_v_vstate_save(prev, regs);
> +	riscv_v_vstate_save(prev->thread.vstate, regs);
>  	riscv_v_vstate_set_restore(next, task_pt_regs(next));
>  }
>  
> @@ -218,8 +214,8 @@ static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; }
>  static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; }
>  #define riscv_v_vsize (0)
>  #define riscv_v_vstate_discard(regs)		do {} while (0)
> -#define riscv_v_vstate_save(task, regs)		do {} while (0)
> -#define riscv_v_vstate_restore(task, regs)	do {} while (0)
> +#define riscv_v_vstate_save(vstate, regs)	do {} while (0)
> +#define riscv_v_vstate_restore(vstate, regs)	do {} while (0)
>  #define __switch_to_vector(__prev, __next)	do {} while (0)
>  #define riscv_v_vstate_off(regs)		do {} while (0)
>  #define riscv_v_vstate_on(regs)			do {} while (0)
> diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/kernel_mode_vector.c
> index c0c152c501a5..30f1b861cac0 100644
> --- a/arch/riscv/kernel/kernel_mode_vector.c
> +++ b/arch/riscv/kernel/kernel_mode_vector.c
> @@ -91,7 +91,7 @@ int kernel_rvv_begin(void)
>  		return -EPERM;
>  
>  	/* Save vector state, if any */
> -	riscv_v_vstate_save(current, task_pt_regs(current));
> +	riscv_v_vstate_save(&current->thread.vstate, task_pt_regs(current));
>  
>  	/* Acquire kernel mode vector */
>  	get_cpu_vector_context();
> diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
> index 1d572cf3140f..85e7167245cc 100644
> --- a/arch/riscv/kernel/ptrace.c
> +++ b/arch/riscv/kernel/ptrace.c
> @@ -99,7 +99,7 @@ static int riscv_vr_get(struct task_struct *target,
>  	 * copying them to membuf.
>  	 */
>  	if (target == current)
> -		riscv_v_vstate_save(current, task_pt_regs(current));
> +		riscv_v_vstate_save(&current->thread.vstate, task_pt_regs(current));
>  
>  	/* Copy vector header from vstate. */
>  	membuf_write(&to, vstate, offsetof(struct __riscv_v_ext_state, datap));
> diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c
> index 0fca2c128b5f..75fd8cc05e10 100644
> --- a/arch/riscv/kernel/signal.c
> +++ b/arch/riscv/kernel/signal.c
> @@ -86,7 +86,7 @@ static long save_v_state(struct pt_regs *regs, void __user **sc_vec)
>  	/* datap is designed to be 16 byte aligned for better performance */
>  	WARN_ON(unlikely(!IS_ALIGNED((unsigned long)datap, 16)));
>  
> -	riscv_v_vstate_save(current, regs);
> +	riscv_v_vstate_save(&current->thread.vstate, regs);
>  	/* Copy everything of vstate but datap. */
>  	err = __copy_to_user(&state->v_state, &current->thread.vstate,
>  			     offsetof(struct __riscv_v_ext_state, datap));
> -- 
> 2.17.1
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

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  reply	other threads:[~2023-07-17 10:33 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-15 15:00 [v1, 0/6] riscv: support kernel-mode Vector Andy Chiu
2023-07-15 15:00 ` [v1, 1/6] riscv: sched: defer restoring Vector context for user Andy Chiu
2023-07-17  9:46   ` Conor Dooley
2023-07-17 16:03     ` Andy Chiu
2023-07-15 15:00 ` [v1, 2/6] riscv: Add support for kernel mode vector Andy Chiu
2023-07-17 10:22   ` Conor Dooley
2023-07-20 14:54     ` Andy Chiu
2023-07-15 15:00 ` [v1, 3/6] riscv: Add vector extension XOR implementation Andy Chiu
2023-07-17 10:25   ` Conor Dooley
2023-07-20 14:56     ` Andy Chiu
2023-07-15 15:00 ` [v1, 4/6] riscv: vector: do not pass task_struct into riscv_v_vstate_{save,restore}() Andy Chiu
2023-07-17 10:32   ` Conor Dooley [this message]
2023-07-20 14:59     ` Andy Chiu
2023-07-15 15:00 ` [v1, 5/6] riscv: vector: allow kernel-mode Vector with preemption Andy Chiu
2023-07-17 11:05   ` Conor Dooley
2023-07-20 15:13     ` Andy Chiu
2023-07-15 15:00 ` [v1, 6/6] riscv: vector: enable preemptive kernel-mode Vector to be built Andy Chiu
2023-07-17 11:11   ` Conor Dooley
2023-07-16  9:26 ` [v1, 0/6] riscv: support kernel-mode Vector Heiko Stuebner

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