From: Conor Dooley <conor.dooley@microchip.com>
To: Andy Chiu <andy.chiu@sifive.com>
Cc: <linux-riscv@lists.infradead.org>, <palmer@dabbelt.com>,
<vineetg@rivosinc.com>, <bjorn@kernel.org>,
<greentime.hu@sifive.com>, <paul.walmsley@sifive.com>,
<guoren@linux.alibaba.com>, <anup@brainfault.org>,
<atishp@atishpatra.org>, <heiko.stuebner@vrull.eu>,
Han-Kuan Chen <hankuan.chen@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Andrew Jones <ajones@ventanamicro.com>
Subject: Re: [v1, 3/6] riscv: Add vector extension XOR implementation
Date: Mon, 17 Jul 2023 11:25:34 +0100 [thread overview]
Message-ID: <20230717-sedan-tiara-b7013d409ab8@wendy> (raw)
In-Reply-To: <20230715150032.6917-4-andy.chiu@sifive.com>
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On Sat, Jul 15, 2023 at 03:00:29PM +0000, Andy Chiu wrote:
> From: Greentime Hu <greentime.hu@sifive.com>
>
> This patch adds support for vector optimized XOR and it is tested in
> qemu.
Since this patch was originally written, has it been tested in hardware?
> Co-developed-by: Han-Kuan Chen <hankuan.chen@sifive.com>
> Signed-off-by: Han-Kuan Chen <hankuan.chen@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> ---
> arch/riscv/include/asm/xor.h | 82 ++++++++++++++++++++++++++++++++++++
> arch/riscv/lib/Makefile | 1 +
> arch/riscv/lib/xor.S | 81 +++++++++++++++++++++++++++++++++++
> 3 files changed, 164 insertions(+)
> create mode 100644 arch/riscv/include/asm/xor.h
> create mode 100644 arch/riscv/lib/xor.S
>
> diff --git a/arch/riscv/include/asm/xor.h b/arch/riscv/include/asm/xor.h
> new file mode 100644
> index 000000000000..81b8837fa161
> --- /dev/null
> +++ b/arch/riscv/include/asm/xor.h
> +static void xor_rvv_2(unsigned long bytes, unsigned long *__restrict p1,
> + const unsigned long *__restrict p2)
> +static void xor_rvv_3(unsigned long bytes, unsigned long *__restrict p1,
> + const unsigned long *__restrict p2,
> + const unsigned long *__restrict p3)
> +static void xor_rvv_4(unsigned long bytes, unsigned long *__restrict p1,
> + const unsigned long *__restrict p2,
> + const unsigned long *__restrict p3,
> + const unsigned long *__restrict p4)
> +
> +static void xor_rvv_5(unsigned long bytes, unsigned long *__restrict p1,
> + const unsigned long *__restrict p2,
> + const unsigned long *__restrict p3,
> + const unsigned long *__restrict p4,
> + const unsigned long *__restrict p5)
> +
> +static struct xor_block_template xor_block_rvv = {
> + .name = "rvv",
> + .do_2 = xor_rvv_2,
> + .do_3 = xor_rvv_3,
> + .do_4 = xor_rvv_4,
> + .do_5 = xor_rvv_5
> +};
Same naming scheme comments as the main vector patchset and 2/6 apply
here too.
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next prev parent reply other threads:[~2023-07-17 10:26 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-15 15:00 [v1, 0/6] riscv: support kernel-mode Vector Andy Chiu
2023-07-15 15:00 ` [v1, 1/6] riscv: sched: defer restoring Vector context for user Andy Chiu
2023-07-17 9:46 ` Conor Dooley
2023-07-17 16:03 ` Andy Chiu
2023-07-15 15:00 ` [v1, 2/6] riscv: Add support for kernel mode vector Andy Chiu
2023-07-17 10:22 ` Conor Dooley
2023-07-20 14:54 ` Andy Chiu
2023-07-15 15:00 ` [v1, 3/6] riscv: Add vector extension XOR implementation Andy Chiu
2023-07-17 10:25 ` Conor Dooley [this message]
2023-07-20 14:56 ` Andy Chiu
2023-07-15 15:00 ` [v1, 4/6] riscv: vector: do not pass task_struct into riscv_v_vstate_{save,restore}() Andy Chiu
2023-07-17 10:32 ` Conor Dooley
2023-07-20 14:59 ` Andy Chiu
2023-07-15 15:00 ` [v1, 5/6] riscv: vector: allow kernel-mode Vector with preemption Andy Chiu
2023-07-17 11:05 ` Conor Dooley
2023-07-20 15:13 ` Andy Chiu
2023-07-15 15:00 ` [v1, 6/6] riscv: vector: enable preemptive kernel-mode Vector to be built Andy Chiu
2023-07-17 11:11 ` Conor Dooley
2023-07-16 9:26 ` [v1, 0/6] riscv: support kernel-mode Vector Heiko Stuebner
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