Re: [v1, 2/6] riscv: smp: fail booting up smp if inconsistent vlen is detected

From: Conor Dooley <conor@kernel.org>
To: Andy Chiu <andy.chiu@sifive.com>
Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
	"Anup Patel" <apatel@ventanamicro.com>,
	"Clément Léger" <cleger@rivosinc.com>,
	guoren@linux.alibaba.com, "Heiko Stuebner" <heiko@sntech.de>,
	"Yang Li" <yang.lee@linux.alibaba.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Nam Cao" <namcaov@gmail.com>,
	"Samuel Holland" <samuel.holland@sifive.com>,
	"Vincent Chen" <vincent.chen@sifive.com>,
	bjorn@kernel.org, "Albert Ou" <aou@eecs.berkeley.edu>,
	"Guo Ren" <guoren@kernel.org>, "Evan Green" <evan@rivosinc.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Frederik Haxel" <haxel@fzi.de>,
	greentime.hu@sifive.com,
	"Sami Tolvanen" <samitolvanen@google.com>,
	"Andrew Jones" <ajones@ventanamicro.com>
Subject: Re: [v1, 2/6] riscv: smp: fail booting up smp if inconsistent vlen is detected
Date: Tue, 12 Mar 2024 12:59:01 +0000	[thread overview]
Message-ID: <20240312-hardened-filled-01e6cafc9c5b@spud> (raw)
In-Reply-To: <20240312123627.9285-3-andy.chiu@sifive.com>

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On Tue, Mar 12, 2024 at 08:36:23PM +0800, Andy Chiu wrote:
> Currently we only support Vector for SMP platforms, that is, all SMP
> cores have the same vlenb. If we happen to detect a mismatching vlen, it
> is better to just fail bootting it up to prevent further race/scheduling
> issues.
> 
> Fixes: 7017858eb2d7 ("riscv: Introduce riscv_v_vsize to record size of Vector context")
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>

Reported-by: Conor Dooley <conor.dooley@microchip.com>
Closes: https://lore.kernel.org/linux-riscv/20240228-vicinity-cornstalk-4b8eb5fe5730@spud/
cc: stable@vger.kernel.org

I actually thought I had sent a patch for this, but I don't seem to
have. I did write one, so I guess I just did not send it.

> ---
>  arch/riscv/kernel/head.S    | 14 +++++++-------
>  arch/riscv/kernel/smpboot.c | 14 +++++++++-----
>  2 files changed, 16 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index 4236a69c35cb..a158fa9f2656 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -165,9 +165,15 @@ secondary_start_sbi:
>  #endif
>  	call .Lsetup_trap_vector
>  	scs_load_current
> -	tail smp_callin
> +	call smp_callin
>  #endif /* CONFIG_SMP */
>  
> +.align 2
> +.Lsecondary_park:
> +	/* We lack SMP support or have too many harts, so park this hart */
> +	wfi
> +	j .Lsecondary_park
> +
>  .align 2
>  .Lsetup_trap_vector:
>  	/* Set trap vector to exception handler */
> @@ -181,12 +187,6 @@ secondary_start_sbi:
>  	csrw CSR_SCRATCH, zero
>  	ret
>  
> -.align 2
> -.Lsecondary_park:
> -	/* We lack SMP support or have too many harts, so park this hart */
> -	wfi
> -	j .Lsecondary_park
> -
>  SYM_CODE_END(_start)
>  
>  SYM_CODE_START(_start_kernel)

Why does this change? There's no mention of why in the commit message.

Thanks,
Conor.

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