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From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com
Cc: greentime.hu@sifive.com, guoren@linux.alibaba.com,
	bjorn@kernel.org, "Andy Chiu" <andy.chiu@sifive.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Evan Green" <evan@rivosinc.com>,
	"Clément Léger" <cleger@rivosinc.com>,
	"Charlie Jenkins" <charlie@rivosinc.com>,
	"Yangyu Chen" <cyy@cyyself.name>
Subject: [v1, 3/6] riscv: cpufeature: call match_isa_ext() for single-letter extensions
Date: Tue, 12 Mar 2024 20:36:24 +0800	[thread overview]
Message-ID: <20240312123627.9285-4-andy.chiu@sifive.com> (raw)
In-Reply-To: <20240312123627.9285-1-andy.chiu@sifive.com>

Single-letter extensions may also imply multiple subextensions. For
example, Vector extension implies zve64d, and zve64d implies zve64f.

Extension parsing for "riscv,isa-extensions" has the ability to resolve
the dependency by calling match_isa_ext(). This patch makes deprecated
parser call the same function for single letter extensions.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
---
 arch/riscv/kernel/cpufeature.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 1b21f1e568e1..8986ceb58188 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -470,6 +470,10 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc
 
 		if (unlikely(ext_err))
 			continue;
+
+		for (int i = 0; i < riscv_isa_ext_count; i++)
+			match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo);
+
 		if (!ext_long) {
 			int nr = tolower(*ext) - 'a';
 
@@ -477,9 +481,6 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc
 				*this_hwcap |= isa2hwcap[nr];
 				set_bit(nr, isainfo->isa);
 			}
-		} else {
-			for (int i = 0; i < riscv_isa_ext_count; i++)
-				match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo);
 		}
 	}
 }
-- 
2.17.1


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  parent reply	other threads:[~2024-03-12 12:37 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-12 12:36 [v1, 0/6] Support Zve32[xf] and Zve64[xfd] Vector subextensions Andy Chiu
2024-03-12 12:36 ` [v1, 1/6] riscv: vector: add a comment when calling riscv_setup_vsize() Andy Chiu
2024-03-12 13:01   ` Conor Dooley
2024-03-12 12:36 ` [v1, 2/6] riscv: smp: fail booting up smp if inconsistent vlen is detected Andy Chiu
2024-03-12 12:59   ` Conor Dooley
2024-03-13  1:40     ` Andy Chiu
2024-03-12 12:36 ` Andy Chiu [this message]
2024-03-12 12:36 ` [v1, 4/6] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection Andy Chiu
2024-03-12 12:51   ` Clément Léger
2024-03-13  3:34     ` Andy Chiu
2024-03-12 13:05   ` Conor Dooley
2024-03-13  7:04     ` Andy Chiu
2024-03-13  4:01   ` Samuel Holland
2024-03-13  7:03     ` Andy Chiu
2024-03-12 12:36 ` [v1, 5/6] riscv: hwprobe: add zve Vector subextesnions into hwprobe interface Andy Chiu
2024-03-12 12:42   ` Clément Léger
2024-03-12 12:56     ` Clément Léger
2024-03-13  1:47     ` Andy Chiu
2024-03-12 12:36 ` [v1, 6/6] riscv: vector: adjust minimum Vector requirement to ZVE32X Andy Chiu
2024-03-13  9:53   ` Joel Granados
2024-03-12 13:16 ` [v1, 0/6] Support Zve32[xf] and Zve64[xfd] Vector subextensions Stefan O'Rear
2024-03-13  9:15   ` Andy Chiu
2024-03-14 22:13     ` Stefan O'Rear

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