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From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com
Cc: greentime.hu@sifive.com, guoren@linux.alibaba.com,
	bjorn@kernel.org, "Andy Chiu" <andy.chiu@sifive.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Evan Green" <evan@rivosinc.com>,
	"Clément Léger" <cleger@rivosinc.com>,
	"Charlie Jenkins" <charlie@rivosinc.com>,
	"Yangyu Chen" <cyy@cyyself.name>
Subject: [v1, 1/6] riscv: vector: add a comment when calling riscv_setup_vsize()
Date: Tue, 12 Mar 2024 20:36:22 +0800	[thread overview]
Message-ID: <20240312123627.9285-2-andy.chiu@sifive.com> (raw)
In-Reply-To: <20240312123627.9285-1-andy.chiu@sifive.com>

The function would fail when it detects the calling hart's vlen doesn't
match the first one's. The boot hart is the first hart calling this
function during riscv_fill_hwcap, so it is impossible to fail here. Add
a comment about this behavior.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
---
 arch/riscv/kernel/cpufeature.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 89920f84d0a3..1b21f1e568e1 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -671,6 +671,10 @@ void __init riscv_fill_hwcap(void)
 	}
 
 	if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
+		/*
+		 * This callsite can't fail here. This is the first time we
+		 * call during boot, so riscv_v_vsize must be zero.
+		 */
 		riscv_v_setup_vsize();
 		/*
 		 * ISA string in device tree might have 'v' flag, but
-- 
2.17.1


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  reply	other threads:[~2024-03-12 12:36 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-12 12:36 [v1, 0/6] Support Zve32[xf] and Zve64[xfd] Vector subextensions Andy Chiu
2024-03-12 12:36 ` Andy Chiu [this message]
2024-03-12 13:01   ` [v1, 1/6] riscv: vector: add a comment when calling riscv_setup_vsize() Conor Dooley
2024-03-12 12:36 ` [v1, 2/6] riscv: smp: fail booting up smp if inconsistent vlen is detected Andy Chiu
2024-03-12 12:59   ` Conor Dooley
2024-03-13  1:40     ` Andy Chiu
2024-03-12 12:36 ` [v1, 3/6] riscv: cpufeature: call match_isa_ext() for single-letter extensions Andy Chiu
2024-03-12 12:36 ` [v1, 4/6] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection Andy Chiu
2024-03-12 12:51   ` Clément Léger
2024-03-13  3:34     ` Andy Chiu
2024-03-12 13:05   ` Conor Dooley
2024-03-13  7:04     ` Andy Chiu
2024-03-13  4:01   ` Samuel Holland
2024-03-13  7:03     ` Andy Chiu
2024-03-12 12:36 ` [v1, 5/6] riscv: hwprobe: add zve Vector subextesnions into hwprobe interface Andy Chiu
2024-03-12 12:42   ` Clément Léger
2024-03-12 12:56     ` Clément Léger
2024-03-13  1:47     ` Andy Chiu
2024-03-12 12:36 ` [v1, 6/6] riscv: vector: adjust minimum Vector requirement to ZVE32X Andy Chiu
2024-03-13  9:53   ` Joel Granados
2024-03-12 13:16 ` [v1, 0/6] Support Zve32[xf] and Zve64[xfd] Vector subextensions Stefan O'Rear
2024-03-13  9:15   ` Andy Chiu
2024-03-14 22:13     ` Stefan O'Rear

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