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From: Xu Lu <luxu.kernel@bytedance.com>
To: daniel.lezcano@linaro.org, tglx@linutronix.de,
	anup@brainfault.org, paul.walmsley@sifive.com,
	palmer@dabbelt.com
Cc: lihangjing@bytedance.com, xieyongji@bytedance.com,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Xu Lu <luxu.kernel@bytedance.com>
Subject: [PATCH 2/5] irqchip/riscv-imsic: Add a threshold to ext irq handling times
Date: Mon, 13 Jan 2025 23:09:30 +0800	[thread overview]
Message-ID: <20250113150933.65121-3-luxu.kernel@bytedance.com> (raw)
In-Reply-To: <20250113150933.65121-1-luxu.kernel@bytedance.com>

RISC-V's external irq has higher priority than software irq, timer irq
and pmu overflow irq. In existing implementation of IMSIC driver, If
external irqs keep arriving within a certain period of time, no other
interrupt will get a chance to be handled.

This commit solves this problem by introducing a threshold to the number
of times imsic interrupts can be processed in each round.

Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
 drivers/irqchip/irq-riscv-imsic-early.c | 31 ++++++++++++++-----------
 1 file changed, 18 insertions(+), 13 deletions(-)

diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c
index c5c2e6929a2f..63097f2bbadf 100644
--- a/drivers/irqchip/irq-riscv-imsic-early.c
+++ b/drivers/irqchip/irq-riscv-imsic-early.c
@@ -20,6 +20,8 @@
 
 #include "irq-riscv-imsic-state.h"
 
+#define IMSIC_HANDLE_THRESHOLD		20
+
 static int imsic_parent_irq;
 
 #ifdef CONFIG_SMP
@@ -76,6 +78,7 @@ static void imsic_handle_irq(struct irq_desc *desc)
 	int err, cpu = smp_processor_id();
 	struct imsic_vector *vec;
 	unsigned long local_id;
+	unsigned int handled = 0;
 
 	chained_irq_enter(chip, desc);
 
@@ -85,21 +88,23 @@ static void imsic_handle_irq(struct irq_desc *desc)
 		if (local_id == IMSIC_IPI_ID) {
 			if (IS_ENABLED(CONFIG_SMP))
 				ipi_mux_process();
-			continue;
-		}
-
-		if (unlikely(!imsic->base_domain))
-			continue;
-
-		vec = imsic_vector_from_local_id(cpu, local_id);
-		if (!vec) {
-			pr_warn_ratelimited("vector not found for local ID 0x%lx\n", local_id);
-			continue;
+		} else if (likely(imsic->base_domain)) {
+			vec = imsic_vector_from_local_id(cpu, local_id);
+
+			if (unlikely(!vec))
+				pr_warn_ratelimited("vector not found for local ID 0x%lx\n",
+						    local_id);
+			else {
+				err = generic_handle_domain_irq(imsic->base_domain, vec->hwirq);
+
+				if (unlikely(err))
+					pr_warn_ratelimited("hwirq 0x%x mapping not found\n",
+							    vec->hwirq);
+			}
 		}
 
-		err = generic_handle_domain_irq(imsic->base_domain, vec->hwirq);
-		if (unlikely(err))
-			pr_warn_ratelimited("hwirq 0x%x mapping not found\n", vec->hwirq);
+		if (handled++ >= IMSIC_HANDLE_THRESHOLD)
+			break;
 	}
 
 	chained_irq_exit(chip, desc);
-- 
2.20.1


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  parent reply	other threads:[~2025-01-13 15:52 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-13 15:09 [PATCH 0/5] riscv: irqchip: Optimization of interrupt handling Xu Lu
2025-01-13 15:09 ` [PATCH 1/5] irqchip/riscv-intc: Balance priority and fairness during irq handling Xu Lu
2025-01-15 11:39   ` Anup Patel
2025-01-15 12:37     ` [External] " Xu Lu
2025-01-15 17:01       ` Anup Patel
2025-01-16  2:26         ` Xu Lu
2025-01-13 15:09 ` Xu Lu [this message]
2025-01-13 15:09 ` [PATCH 3/5] irqchip/riscv-imsic: Use wmb() to order normal writes and IPI writes Xu Lu
2025-01-14  4:34   ` Anup Patel
2025-01-14  6:39     ` [External] " Xu Lu
2025-01-14  8:58       ` Anup Patel
2025-01-14  9:07         ` Xu Lu
2025-01-13 15:09 ` [PATCH 4/5] irqchip/timer-clint: " Xu Lu
2025-01-14  4:34   ` Anup Patel
2025-01-13 15:09 ` [PATCH 5/5] irqchip/aclint-sswi: " Xu Lu
2025-01-14  4:34   ` Anup Patel

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