[PATCH 3/5] irqchip/riscv-imsic: Use wmb() to order normal writes and IPI writes

From: Xu Lu <luxu.kernel@bytedance.com>
To: daniel.lezcano@linaro.org, tglx@linutronix.de,
	anup@brainfault.org, paul.walmsley@sifive.com,
	palmer@dabbelt.com
Cc: lihangjing@bytedance.com, xieyongji@bytedance.com,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Xu Lu <luxu.kernel@bytedance.com>
Subject: [PATCH 3/5] irqchip/riscv-imsic: Use wmb() to order normal writes and IPI writes
Date: Mon, 13 Jan 2025 23:09:31 +0800	[thread overview]
Message-ID: <20250113150933.65121-4-luxu.kernel@bytedance.com> (raw)
In-Reply-To: <20250113150933.65121-1-luxu.kernel@bytedance.com>

During an IPI procedure, we need to ensure all previous write operations
are visible to other CPUs before sending a real IPI. We use wmb() barrier
to ensure this as IMSIC issues IPI via mmio writes.

Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
 drivers/irqchip/irq-riscv-imsic-early.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c
index 63097f2bbadf..c6317cb557fb 100644
--- a/drivers/irqchip/irq-riscv-imsic-early.c
+++ b/drivers/irqchip/irq-riscv-imsic-early.c
@@ -29,6 +29,12 @@ static void imsic_ipi_send(unsigned int cpu)
 {
 	struct imsic_local_config *local = per_cpu_ptr(imsic->global.local, cpu);
 
+	/*
+	 * Ensure that stores to normal memory are visible to the other CPUs
+	 * before issuing IPI.
+	 */
+	wmb();
+
 	writel_relaxed(IMSIC_IPI_ID, local->msi_va);
 }
 
-- 
2.20.1


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