From: "Clément Léger" <cleger@rivosinc.com>
To: linux-doc@vger.kernel.org (open list:DOCUMENTATION),
linux-kernel@vger.kernel.org (open list),
linux-riscv@lists.infradead.org (open list:RISC-V ARCHITECTURE),
linux-kselftest@vger.kernel.org (open list:KERNEL SELFTEST
FRAMEWORK)
Cc: "Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Shuah Khan" <shuah@kernel.org>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Samuel Holland" <samuel.holland@sifive.com>
Subject: [PATCH v2 0/5] riscv: misaligned: fix interruptible context and add tests
Date: Tue, 22 Apr 2025 18:23:07 +0200 [thread overview]
Message-ID: <20250422162324.956065-1-cleger@rivosinc.com> (raw)
This series fixes misaligned access handling when in non interruptible
context by reenabling interrupts when possible. A previous commit
changed raw_copy_from_user() with copy_from_user() which enables page
faulting and thus can sleep. While correct, a warning is now triggered
due to being called in an invalid context (sleeping in
non-interruptible). This series fixes that problem by factorizing
misaligned load/store entry in a single function than reenables
interrupt if the interrupted context had interrupts enabled.
In order for misaligned handling problems to be caught sooner, add a
kselftest for all the currently supported instructions .
Note: these commits were actually part of another larger series for
misaligned request delegation but was split since it isn't directly
required.
V2:
- Use an array of struct to simplify misaligned load/store selection
- Revert use of irqentry_enter()/exit() to irqentry_nmi_enter() for
kernel space.
Clément Léger (5):
riscv: misaligned: factorize trap handling
riscv: misaligned: enable IRQs while handling misaligned accesses
riscv: misaligned: use get_user() instead of __get_user()
Documentation/sysctl: add riscv to unaligned-trap supported archs
selftests: riscv: add misaligned access testing
Documentation/admin-guide/sysctl/kernel.rst | 4 +-
arch/riscv/kernel/traps.c | 64 +++--
arch/riscv/kernel/traps_misaligned.c | 2 +-
.../selftests/riscv/misaligned/.gitignore | 1 +
.../selftests/riscv/misaligned/Makefile | 12 +
.../selftests/riscv/misaligned/common.S | 33 +++
.../testing/selftests/riscv/misaligned/fpu.S | 180 +++++++++++++
tools/testing/selftests/riscv/misaligned/gp.S | 103 +++++++
.../selftests/riscv/misaligned/misaligned.c | 254 ++++++++++++++++++
9 files changed, 623 insertions(+), 30 deletions(-)
create mode 100644 tools/testing/selftests/riscv/misaligned/.gitignore
create mode 100644 tools/testing/selftests/riscv/misaligned/Makefile
create mode 100644 tools/testing/selftests/riscv/misaligned/common.S
create mode 100644 tools/testing/selftests/riscv/misaligned/fpu.S
create mode 100644 tools/testing/selftests/riscv/misaligned/gp.S
create mode 100644 tools/testing/selftests/riscv/misaligned/misaligned.c
--
2.49.0
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next reply other threads:[~2025-04-22 19:47 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-22 16:23 Clément Léger [this message]
2025-04-22 16:23 ` [PATCH v2 1/5] riscv: misaligned: factorize trap handling Clément Léger
2025-05-06 10:58 ` Alexandre Ghiti
2025-04-22 16:23 ` [PATCH v2 2/5] riscv: misaligned: enable IRQs while handling misaligned accesses Clément Léger
2025-05-06 11:07 ` Alexandre Ghiti
2025-04-22 16:23 ` [PATCH v2 3/5] riscv: misaligned: use get_user() instead of __get_user() Clément Léger
2025-04-22 16:23 ` [PATCH v2 4/5] Documentation/sysctl: add riscv to unaligned-trap supported archs Clément Léger
2025-04-22 16:23 ` [PATCH v2 5/5] selftests: riscv: add misaligned access testing Clément Léger
2025-05-09 8:22 ` Alexandre Ghiti
2025-05-12 7:18 ` Clément Léger
2025-05-08 16:52 ` [PATCH v2 0/5] riscv: misaligned: fix interruptible context and add tests patchwork-bot+linux-riscv
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