From: "Clément Léger" <cleger@rivosinc.com>
To: linux-doc@vger.kernel.org (open list:DOCUMENTATION),
linux-kernel@vger.kernel.org (open list),
linux-riscv@lists.infradead.org (open list:RISC-V ARCHITECTURE),
linux-kselftest@vger.kernel.org (open list:KERNEL SELFTEST
FRAMEWORK)
Cc: "Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Shuah Khan" <shuah@kernel.org>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Alexandre Ghiti" <alexghiti@rivosinc.com>
Subject: [PATCH v2 3/5] riscv: misaligned: use get_user() instead of __get_user()
Date: Tue, 22 Apr 2025 18:23:10 +0200 [thread overview]
Message-ID: <20250422162324.956065-4-cleger@rivosinc.com> (raw)
In-Reply-To: <20250422162324.956065-1-cleger@rivosinc.com>
Now that we can safely handle user memory accesses while in the
misaligned access handlers, use get_user() instead of __get_user() to
have user memory access checks.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
---
arch/riscv/kernel/traps_misaligned.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index 4354c87c0376..97c674d7d34f 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -268,7 +268,7 @@ static unsigned long get_f32_rs(unsigned long insn, u8 fp_reg_offset,
int __ret; \
\
if (user_mode(regs)) { \
- __ret = __get_user(insn, (type __user *) insn_addr); \
+ __ret = get_user(insn, (type __user *) insn_addr); \
} else { \
insn = *(type *)insn_addr; \
__ret = 0; \
--
2.49.0
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next prev parent reply other threads:[~2025-04-22 19:47 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-22 16:23 [PATCH v2 0/5] riscv: misaligned: fix interruptible context and add tests Clément Léger
2025-04-22 16:23 ` [PATCH v2 1/5] riscv: misaligned: factorize trap handling Clément Léger
2025-05-06 10:58 ` Alexandre Ghiti
2025-04-22 16:23 ` [PATCH v2 2/5] riscv: misaligned: enable IRQs while handling misaligned accesses Clément Léger
2025-05-06 11:07 ` Alexandre Ghiti
2025-04-22 16:23 ` Clément Léger [this message]
2025-04-22 16:23 ` [PATCH v2 4/5] Documentation/sysctl: add riscv to unaligned-trap supported archs Clément Léger
2025-04-22 16:23 ` [PATCH v2 5/5] selftests: riscv: add misaligned access testing Clément Léger
2025-05-09 8:22 ` Alexandre Ghiti
2025-05-12 7:18 ` Clément Léger
2025-05-08 16:52 ` [PATCH v2 0/5] riscv: misaligned: fix interruptible context and add tests patchwork-bot+linux-riscv
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