From: "Clément Léger" <cleger@rivosinc.com>
To: linux-doc@vger.kernel.org (open list:DOCUMENTATION),
linux-kernel@vger.kernel.org (open list),
linux-riscv@lists.infradead.org (open list:RISC-V ARCHITECTURE),
linux-kselftest@vger.kernel.org (open list:KERNEL SELFTEST
FRAMEWORK)
Cc: "Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Shuah Khan" <shuah@kernel.org>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Samuel Holland" <samuel.holland@sifive.com>
Subject: [PATCH v2 1/5] riscv: misaligned: factorize trap handling
Date: Tue, 22 Apr 2025 18:23:08 +0200 [thread overview]
Message-ID: <20250422162324.956065-2-cleger@rivosinc.com> (raw)
In-Reply-To: <20250422162324.956065-1-cleger@rivosinc.com>
Since both load/store and user/kernel should use almost the same path and
that we are going to add some code around that, factorize it.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
arch/riscv/kernel/traps.c | 66 +++++++++++++++++++++------------------
1 file changed, 36 insertions(+), 30 deletions(-)
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index 8ff8e8b36524..b1d991c78a23 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -198,47 +198,53 @@ asmlinkage __visible __trap_section void do_trap_insn_illegal(struct pt_regs *re
DO_ERROR_INFO(do_trap_load_fault,
SIGSEGV, SEGV_ACCERR, "load access fault");
-asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt_regs *regs)
+enum misaligned_access_type {
+ MISALIGNED_STORE,
+ MISALIGNED_LOAD,
+};
+static const struct {
+ const char *type_str;
+ int (*handler)(struct pt_regs *regs);
+} misaligned_handler[] = {
+ [MISALIGNED_STORE] = {
+ .type_str = "Oops - store (or AMO) address misaligned",
+ .handler = handle_misaligned_store,
+ },
+ [MISALIGNED_LOAD] = {
+ .type_str = "Oops - load address misaligned",
+ .handler = handle_misaligned_load,
+ },
+};
+
+static void do_trap_misaligned(struct pt_regs *regs, enum misaligned_access_type type)
{
- if (user_mode(regs)) {
+ irqentry_state_t state;
+
+ if (user_mode(regs))
irqentry_enter_from_user_mode(regs);
+ else
+ state = irqentry_nmi_enter(regs);
- if (handle_misaligned_load(regs))
- do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc,
- "Oops - load address misaligned");
+ if (misaligned_handler[type].handler(regs))
+ do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc,
+ misaligned_handler[type].type_str);
+ if (user_mode(regs))
irqentry_exit_to_user_mode(regs);
- } else {
- irqentry_state_t state = irqentry_nmi_enter(regs);
-
- if (handle_misaligned_load(regs))
- do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc,
- "Oops - load address misaligned");
-
+ else
irqentry_nmi_exit(regs, state);
- }
}
-asmlinkage __visible __trap_section void do_trap_store_misaligned(struct pt_regs *regs)
+asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt_regs *regs)
{
- if (user_mode(regs)) {
- irqentry_enter_from_user_mode(regs);
-
- if (handle_misaligned_store(regs))
- do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc,
- "Oops - store (or AMO) address misaligned");
-
- irqentry_exit_to_user_mode(regs);
- } else {
- irqentry_state_t state = irqentry_nmi_enter(regs);
-
- if (handle_misaligned_store(regs))
- do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc,
- "Oops - store (or AMO) address misaligned");
+ do_trap_misaligned(regs, MISALIGNED_LOAD);
+}
- irqentry_nmi_exit(regs, state);
- }
+asmlinkage __visible __trap_section void do_trap_store_misaligned(struct pt_regs *regs)
+{
+ do_trap_misaligned(regs, MISALIGNED_STORE);
}
+
DO_ERROR_INFO(do_trap_store_fault,
SIGSEGV, SEGV_ACCERR, "store (or AMO) access fault");
DO_ERROR_INFO(do_trap_ecall_s,
--
2.49.0
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next prev parent reply other threads:[~2025-04-22 19:47 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-22 16:23 [PATCH v2 0/5] riscv: misaligned: fix interruptible context and add tests Clément Léger
2025-04-22 16:23 ` Clément Léger [this message]
2025-05-06 10:58 ` [PATCH v2 1/5] riscv: misaligned: factorize trap handling Alexandre Ghiti
2025-04-22 16:23 ` [PATCH v2 2/5] riscv: misaligned: enable IRQs while handling misaligned accesses Clément Léger
2025-05-06 11:07 ` Alexandre Ghiti
2025-04-22 16:23 ` [PATCH v2 3/5] riscv: misaligned: use get_user() instead of __get_user() Clément Léger
2025-04-22 16:23 ` [PATCH v2 4/5] Documentation/sysctl: add riscv to unaligned-trap supported archs Clément Léger
2025-04-22 16:23 ` [PATCH v2 5/5] selftests: riscv: add misaligned access testing Clément Léger
2025-05-09 8:22 ` Alexandre Ghiti
2025-05-12 7:18 ` Clément Léger
2025-05-08 16:52 ` [PATCH v2 0/5] riscv: misaligned: fix interruptible context and add tests patchwork-bot+linux-riscv
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