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From: cp0613@linux.alibaba.com
To: paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, alex@ghiti.fr, guoren@kernel.org
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Chen Pei <cp0613@linux.alibaba.com>
Subject: [RFC PATCH 4/4] riscv: trace: Support sink using dma buffer
Date: Thu, 11 Sep 2025 20:44:48 +0800	[thread overview]
Message-ID: <20250911124448.1771-5-cp0613@linux.alibaba.com> (raw)
In-Reply-To: <20250911124448.1771-1-cp0613@linux.alibaba.com>

From: Chen Pei <cp0613@linux.alibaba.com>

In common SoC systems, the trace data by the sink is usually
written to the memory, and the memory needs to be a large block.

We have two methods to achieve this. One is based on reserved
memory. This method requires pre-isolation of memory and is not
flexible enough. Therefore, we chose the second method, which is
based on IOMMU to map non-contiguous memory to continuous. When
implementing the driver, only the DMA alloc related APIs are needed.

Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
---
 arch/riscv/events/riscv_trace.c | 49 ++++++++++++++++++++++++++++++++-
 arch/riscv/events/riscv_trace.h |  4 ++-
 2 files changed, 51 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/events/riscv_trace.c b/arch/riscv/events/riscv_trace.c
index 3ac4a3be5d3e..e8deaefa0180 100644
--- a/arch/riscv/events/riscv_trace.c
+++ b/arch/riscv/events/riscv_trace.c
@@ -9,6 +9,7 @@
 #include <linux/device.h>
 #include <linux/perf_event.h>
 #include <linux/vmalloc.h>
+#include <linux/dma-mapping.h>
 
 #include "riscv_trace.h"
 
@@ -55,6 +56,44 @@ static void riscv_trace_init_filter_attrs(struct perf_event *event)
 		riscv_trace_pmu.filter_attr.priv_mode);
 }
 
+static int riscv_trace_sink_dma_alloc(unsigned long size)
+{
+	struct riscv_trace_component *component;
+	dma_addr_t dma_addr;
+
+	list_for_each_entry(component, &riscv_trace_controllers, list) {
+		if (component->type == RISCV_TRACE_SINK) {
+			component->sink.vaddr =
+			    dma_alloc_coherent(riscv_trace_pmu.pmu.dev, size,
+					       &dma_addr, GFP_KERNEL);
+			if (component->sink.vaddr) {
+				component->sink.start_addr = dma_addr;
+				component->sink.limit_addr = dma_addr + size;
+				continue;
+			} else {
+				pr_err("dma_alloc_coherent failed\n");
+				return -ENOMEM;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static void riscv_trace_sink_dma_free(void)
+{
+	struct riscv_trace_component *component;
+
+	list_for_each_entry(component, &riscv_trace_controllers, list) {
+		if (component->type == RISCV_TRACE_SINK) {
+			if (component->sink.vaddr)
+				dma_free_coherent(riscv_trace_pmu.pmu.dev,
+					component->sink.limit_addr - component->sink.start_addr,
+					component->sink.vaddr, component->sink.start_addr);
+		}
+	}
+}
+
 static int riscv_trace_event_init(struct perf_event *event)
 {
 	if (event->attr.type != riscv_trace_pmu.pmu.type)
@@ -105,7 +144,7 @@ static void *riscv_trace_buffer_setup_aux(struct perf_event *event, void **pages
 {
 	struct riscv_trace_aux_buf *buf;
 	struct page **pagelist;
-	int i;
+	int i, ret;
 
 	if (overwrite) {
 		pr_warn("Overwrite mode is not supported\n");
@@ -135,6 +174,12 @@ static void *riscv_trace_buffer_setup_aux(struct perf_event *event, void **pages
 
 	pr_info("nr_pages=%d length=%d\n", buf->nr_pages, buf->length);
 
+	ret = riscv_trace_sink_dma_alloc(buf->length);
+	if (ret) {
+		kfree(pagelist);
+		goto err;
+	}
+
 	kfree(pagelist);
 	return buf;
 err:
@@ -148,6 +193,8 @@ static void riscv_trace_buffer_free_aux(void *aux)
 
 	vunmap(buf->base);
 	kfree(buf);
+
+	riscv_trace_sink_dma_free();
 }
 
 static int __init riscv_trace_init(void)
diff --git a/arch/riscv/events/riscv_trace.h b/arch/riscv/events/riscv_trace.h
index c28216227006..7819fbeace1f 100644
--- a/arch/riscv/events/riscv_trace.h
+++ b/arch/riscv/events/riscv_trace.h
@@ -49,7 +49,9 @@ struct riscv_trace_funnel {
 };
 
 struct riscv_trace_sink {
-	;
+	u64 start_addr;
+	u64 limit_addr;
+	void __iomem *vaddr;
 };
 
 struct riscv_trace_component {
-- 
2.49.0


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  parent reply	other threads:[~2025-09-11 12:45 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-11 12:44 [RFC PATCH 0/4] riscv: tarce: Implement riscv trace pmu driver and perf support cp0613
2025-09-11 12:44 ` [RFC PATCH 1/4] dt-bindings: riscv: Add trace components description cp0613
2025-09-11 17:24   ` Krzysztof Kozlowski
2025-09-15  2:39     ` cp0613
2025-09-11 12:44 ` [RFC PATCH 2/4] riscv: event: Initial riscv trace driver support cp0613
2025-09-11 12:44 ` [RFC PATCH 3/4] tools: perf: Support perf record with aux buffer for riscv trace cp0613
2025-09-11 12:44 ` cp0613 [this message]
2025-09-17  7:27 ` [RFC PATCH 0/4] riscv: tarce: Implement riscv trace pmu driver and perf support Bo Gan
2025-09-18  6:19   ` cp0613
2025-10-13  4:22 ` Anup Patel
2025-10-14  2:54   ` Guo Ren

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