* [PATCH 0/3] riscv: dts: thead: add more th1520 isa extension support
@ 2025-09-11 18:45 Han Gao
2025-09-11 18:45 ` [PATCH 1/3] riscv: dts: thead: add xtheadvector to the th1520 devicetree Han Gao
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Han Gao @ 2025-09-11 18:45 UTC (permalink / raw)
To: devicetree, Drew Fustini, Guo Ren, Fu Wei, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Han Gao
Cc: linux-riscv, linux-kernel
Add xtheadvector & ziccrse & zfh for th1520
Thanks,
Han
Han Gao (3):
riscv: dts: thead: add xtheadvector to the th1520 devicetree
riscv: dts: thead: add ziccrse for th1520
riscv: dts: thead: add zfh for th1520
arch/riscv/boot/dts/thead/th1520.dtsi | 28 +++++++++++++++++++--------
1 file changed, 20 insertions(+), 8 deletions(-)
--
2.47.3
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/3] riscv: dts: thead: add xtheadvector to the th1520 devicetree
2025-09-11 18:45 [PATCH 0/3] riscv: dts: thead: add more th1520 isa extension support Han Gao
@ 2025-09-11 18:45 ` Han Gao
2025-09-11 18:45 ` [PATCH 2/3] riscv: dts: thead: add ziccrse for th1520 Han Gao
2025-09-11 18:45 ` [PATCH 3/3] riscv: dts: thead: add zfh " Han Gao
2 siblings, 0 replies; 8+ messages in thread
From: Han Gao @ 2025-09-11 18:45 UTC (permalink / raw)
To: devicetree, Drew Fustini, Guo Ren, Fu Wei, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Han Gao
Cc: linux-riscv, linux-kernel, Han Gao
The th1520 support xtheadvector [1] so it can be included in the
devicetree. Also include vlenb for the cpu. And set vlenb=16 [2].
This can be tested by passing the "mitigations=off" kernel parameter.
Link: https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-4-236c22791ef9@rivosinc.com/ [1]
Link: https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/ [2]
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 42724bf7e90e..59d1927764a6 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -25,7 +25,8 @@ c910_0: cpu@0 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
- "zifencei", "zihpm";
+ "zifencei", "zihpm", "xtheadvector";
+ thead,vlenb = <16>;
reg = <0>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -49,7 +50,8 @@ c910_1: cpu@1 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
- "zifencei", "zihpm";
+ "zifencei", "zihpm", "xtheadvector";
+ thead,vlenb = <16>;
reg = <1>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -73,7 +75,8 @@ c910_2: cpu@2 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
- "zifencei", "zihpm";
+ "zifencei", "zihpm", "xtheadvector";
+ thead,vlenb = <16>;
reg = <2>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -97,7 +100,8 @@ c910_3: cpu@3 {
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
- "zifencei", "zihpm";
+ "zifencei", "zihpm", "xtheadvector";
+ thead,vlenb = <16>;
reg = <3>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
--
2.47.3
_______________________________________________
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linux-riscv@lists.infradead.org
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/3] riscv: dts: thead: add ziccrse for th1520
2025-09-11 18:45 [PATCH 0/3] riscv: dts: thead: add more th1520 isa extension support Han Gao
2025-09-11 18:45 ` [PATCH 1/3] riscv: dts: thead: add xtheadvector to the th1520 devicetree Han Gao
@ 2025-09-11 18:45 ` Han Gao
2025-09-12 17:57 ` Conor Dooley
2025-09-11 18:45 ` [PATCH 3/3] riscv: dts: thead: add zfh " Han Gao
2 siblings, 1 reply; 8+ messages in thread
From: Han Gao @ 2025-09-11 18:45 UTC (permalink / raw)
To: devicetree, Drew Fustini, Guo Ren, Fu Wei, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Han Gao
Cc: linux-riscv, linux-kernel, Han Gao
th1520 support Ziccrse ISA extension [1].
Link: https://lore.kernel.org/all/20241103145153.105097-12-alexghiti@rivosinc.com/ [1]
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 24 ++++++++++++++++--------
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 59d1927764a6..7f07688aa964 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -24,8 +24,10 @@ c910_0: cpu@0 {
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
- "zifencei", "zihpm", "xtheadvector";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "ziccrse", "zicntr", "zicsr",
+ "zifencei", "zihpm",
+ "xtheadvector";
thead,vlenb = <16>;
reg = <0>;
i-cache-block-size = <64>;
@@ -49,8 +51,10 @@ c910_1: cpu@1 {
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
- "zifencei", "zihpm", "xtheadvector";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "ziccrse", "zicntr", "zicsr",
+ "zifencei", "zihpm",
+ "xtheadvector";
thead,vlenb = <16>;
reg = <1>;
i-cache-block-size = <64>;
@@ -74,8 +78,10 @@ c910_2: cpu@2 {
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
- "zifencei", "zihpm", "xtheadvector";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "ziccrse", "zicntr", "zicsr",
+ "zifencei", "zihpm",
+ "xtheadvector";
thead,vlenb = <16>;
reg = <2>;
i-cache-block-size = <64>;
@@ -99,8 +105,10 @@ c910_3: cpu@3 {
device_type = "cpu";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
- "zifencei", "zihpm", "xtheadvector";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "ziccrse", "zicntr", "zicsr",
+ "zifencei", "zihpm",
+ "xtheadvector";
thead,vlenb = <16>;
reg = <3>;
i-cache-block-size = <64>;
--
2.47.3
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/3] riscv: dts: thead: add zfh for th1520
2025-09-11 18:45 [PATCH 0/3] riscv: dts: thead: add more th1520 isa extension support Han Gao
2025-09-11 18:45 ` [PATCH 1/3] riscv: dts: thead: add xtheadvector to the th1520 devicetree Han Gao
2025-09-11 18:45 ` [PATCH 2/3] riscv: dts: thead: add ziccrse for th1520 Han Gao
@ 2025-09-11 18:45 ` Han Gao
2025-09-12 17:59 ` Conor Dooley
2025-09-13 5:04 ` Guo Ren
2 siblings, 2 replies; 8+ messages in thread
From: Han Gao @ 2025-09-11 18:45 UTC (permalink / raw)
To: devicetree, Drew Fustini, Guo Ren, Fu Wei, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Han Gao
Cc: linux-riscv, linux-kernel, Han Gao
th1520 support Zfh ISA extension [1].
Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 7f07688aa964..2075bb969c2f 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -26,7 +26,7 @@ c910_0: cpu@0 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <0>;
@@ -53,7 +53,7 @@ c910_1: cpu@1 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <1>;
@@ -80,7 +80,7 @@ c910_2: cpu@2 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <2>;
@@ -107,7 +107,7 @@ c910_3: cpu@3 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <3>;
--
2.47.3
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] riscv: dts: thead: add ziccrse for th1520
2025-09-11 18:45 ` [PATCH 2/3] riscv: dts: thead: add ziccrse for th1520 Han Gao
@ 2025-09-12 17:57 ` Conor Dooley
2025-09-13 9:29 ` Han Gao
0 siblings, 1 reply; 8+ messages in thread
From: Conor Dooley @ 2025-09-12 17:57 UTC (permalink / raw)
To: Han Gao
Cc: devicetree, Drew Fustini, Guo Ren, Fu Wei, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, linux-riscv, linux-kernel, Han Gao
[-- Attachment #1.1: Type: text/plain, Size: 3031 bytes --]
On Fri, Sep 12, 2025 at 02:45:27AM +0800, Han Gao wrote:
> th1520 support Ziccrse ISA extension [1].
>
> Link: https://lore.kernel.org/all/20241103145153.105097-12-alexghiti@rivosinc.com/ [1]
I don't see what this link has to do with th1520 supporting the
extension. The kernel supporting it has nothing to do with whether it
should be in the dts or not. A useful link would substantiate your
claim.
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
You only need to sign this off once.
Cheers,
Conor.
> ---
> arch/riscv/boot/dts/thead/th1520.dtsi | 24 ++++++++++++++++--------
> 1 file changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index 59d1927764a6..7f07688aa964 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -24,8 +24,10 @@ c910_0: cpu@0 {
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> riscv,isa-base = "rv64i";
> - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> - "zifencei", "zihpm", "xtheadvector";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> + "ziccrse", "zicntr", "zicsr",
> + "zifencei", "zihpm",
> + "xtheadvector";
> thead,vlenb = <16>;
> reg = <0>;
> i-cache-block-size = <64>;
> @@ -49,8 +51,10 @@ c910_1: cpu@1 {
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> riscv,isa-base = "rv64i";
> - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> - "zifencei", "zihpm", "xtheadvector";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> + "ziccrse", "zicntr", "zicsr",
> + "zifencei", "zihpm",
> + "xtheadvector";
> thead,vlenb = <16>;
> reg = <1>;
> i-cache-block-size = <64>;
> @@ -74,8 +78,10 @@ c910_2: cpu@2 {
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> riscv,isa-base = "rv64i";
> - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> - "zifencei", "zihpm", "xtheadvector";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> + "ziccrse", "zicntr", "zicsr",
> + "zifencei", "zihpm",
> + "xtheadvector";
> thead,vlenb = <16>;
> reg = <2>;
> i-cache-block-size = <64>;
> @@ -99,8 +105,10 @@ c910_3: cpu@3 {
> device_type = "cpu";
> riscv,isa = "rv64imafdc";
> riscv,isa-base = "rv64i";
> - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> - "zifencei", "zihpm", "xtheadvector";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> + "ziccrse", "zicntr", "zicsr",
> + "zifencei", "zihpm",
> + "xtheadvector";
> thead,vlenb = <16>;
> reg = <3>;
> i-cache-block-size = <64>;
> --
> 2.47.3
>
[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] riscv: dts: thead: add zfh for th1520
2025-09-11 18:45 ` [PATCH 3/3] riscv: dts: thead: add zfh " Han Gao
@ 2025-09-12 17:59 ` Conor Dooley
2025-09-13 5:04 ` Guo Ren
1 sibling, 0 replies; 8+ messages in thread
From: Conor Dooley @ 2025-09-12 17:59 UTC (permalink / raw)
To: Han Gao
Cc: devicetree, Drew Fustini, Guo Ren, Fu Wei, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, linux-riscv, linux-kernel, Han Gao
[-- Attachment #1.1: Type: text/plain, Size: 2339 bytes --]
On Fri, Sep 12, 2025 at 02:45:28AM +0800, Han Gao wrote:
> th1520 support Zfh ISA extension [1].
>
> Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]
Could you please cite the section that this is detailed in?
>
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
> ---
> arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index 7f07688aa964..2075bb969c2f 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -26,7 +26,7 @@ c910_0: cpu@0 {
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <0>;
> @@ -53,7 +53,7 @@ c910_1: cpu@1 {
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <1>;
> @@ -80,7 +80,7 @@ c910_2: cpu@2 {
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <2>;
> @@ -107,7 +107,7 @@ c910_3: cpu@3 {
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <3>;
> --
> 2.47.3
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] riscv: dts: thead: add zfh for th1520
2025-09-11 18:45 ` [PATCH 3/3] riscv: dts: thead: add zfh " Han Gao
2025-09-12 17:59 ` Conor Dooley
@ 2025-09-13 5:04 ` Guo Ren
1 sibling, 0 replies; 8+ messages in thread
From: Guo Ren @ 2025-09-13 5:04 UTC (permalink / raw)
To: Han Gao
Cc: devicetree, Drew Fustini, Fu Wei, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, linux-riscv, linux-kernel, Han Gao
On Fri, Sep 12, 2025 at 2:46 AM Han Gao <rabenda.cn@gmail.com> wrote:
>
> th1520 support Zfh ISA extension [1].
>
> Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]
Agree with Conor's advice.
Linus just had some comment about the Link tag usage:
https://www.phoronix.com/news/Linus-Torvalds-No-Link-Tags
We should be careful :-P
>
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
> ---
> arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index 7f07688aa964..2075bb969c2f 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -26,7 +26,7 @@ c910_0: cpu@0 {
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <0>;
> @@ -53,7 +53,7 @@ c910_1: cpu@1 {
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <1>;
> @@ -80,7 +80,7 @@ c910_2: cpu@2 {
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <2>;
> @@ -107,7 +107,7 @@ c910_3: cpu@3 {
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <3>;
> --
> 2.47.3
>
--
Best Regards
Guo Ren
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] riscv: dts: thead: add ziccrse for th1520
2025-09-12 17:57 ` Conor Dooley
@ 2025-09-13 9:29 ` Han Gao
0 siblings, 0 replies; 8+ messages in thread
From: Han Gao @ 2025-09-13 9:29 UTC (permalink / raw)
To: Conor Dooley
Cc: devicetree, Drew Fustini, Guo Ren, Fu Wei, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, linux-riscv, linux-kernel, Han Gao
On Sat, Sep 13, 2025 at 1:57 AM Conor Dooley <conor@kernel.org> wrote:
>
> On Fri, Sep 12, 2025 at 02:45:27AM +0800, Han Gao wrote:
> > th1520 support Ziccrse ISA extension [1].
> >
> > Link: https://lore.kernel.org/all/20241103145153.105097-12-alexghiti@rivosinc.com/ [1]
>
> I don't see what this link has to do with th1520 supporting the
> extension. The kernel supporting it has nothing to do with whether it
> should be in the dts or not. A useful link would substantiate your
> claim.
Existing rv64 hardware conforms to the rva20 profile.
Ziccrse is an additional extension required by the rva20 profile, so
th1520 has this extension.
Link: https://github.com/riscv/riscv-profiles/blob/main/src/profiles.adoc#511-rva20u64-mandatory-base
[1]
>
> > Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> > Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
>
> You only need to sign this off once.
>
> Cheers,
> Conor.
>
> > ---
> > arch/riscv/boot/dts/thead/th1520.dtsi | 24 ++++++++++++++++--------
> > 1 file changed, 16 insertions(+), 8 deletions(-)
> >
> > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> > index 59d1927764a6..7f07688aa964 100644
> > --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> > @@ -24,8 +24,10 @@ c910_0: cpu@0 {
> > device_type = "cpu";
> > riscv,isa = "rv64imafdc";
> > riscv,isa-base = "rv64i";
> > - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > - "zifencei", "zihpm", "xtheadvector";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > + "ziccrse", "zicntr", "zicsr",
> > + "zifencei", "zihpm",
> > + "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <0>;
> > i-cache-block-size = <64>;
> > @@ -49,8 +51,10 @@ c910_1: cpu@1 {
> > device_type = "cpu";
> > riscv,isa = "rv64imafdc";
> > riscv,isa-base = "rv64i";
> > - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > - "zifencei", "zihpm", "xtheadvector";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > + "ziccrse", "zicntr", "zicsr",
> > + "zifencei", "zihpm",
> > + "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <1>;
> > i-cache-block-size = <64>;
> > @@ -74,8 +78,10 @@ c910_2: cpu@2 {
> > device_type = "cpu";
> > riscv,isa = "rv64imafdc";
> > riscv,isa-base = "rv64i";
> > - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > - "zifencei", "zihpm", "xtheadvector";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > + "ziccrse", "zicntr", "zicsr",
> > + "zifencei", "zihpm",
> > + "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <2>;
> > i-cache-block-size = <64>;
> > @@ -99,8 +105,10 @@ c910_3: cpu@3 {
> > device_type = "cpu";
> > riscv,isa = "rv64imafdc";
> > riscv,isa-base = "rv64i";
> > - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > - "zifencei", "zihpm", "xtheadvector";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > + "ziccrse", "zicntr", "zicsr",
> > + "zifencei", "zihpm",
> > + "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <3>;
> > i-cache-block-size = <64>;
> > --
> > 2.47.3
> >
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linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2025-09-13 9:29 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-09-11 18:45 [PATCH 0/3] riscv: dts: thead: add more th1520 isa extension support Han Gao
2025-09-11 18:45 ` [PATCH 1/3] riscv: dts: thead: add xtheadvector to the th1520 devicetree Han Gao
2025-09-11 18:45 ` [PATCH 2/3] riscv: dts: thead: add ziccrse for th1520 Han Gao
2025-09-12 17:57 ` Conor Dooley
2025-09-13 9:29 ` Han Gao
2025-09-11 18:45 ` [PATCH 3/3] riscv: dts: thead: add zfh " Han Gao
2025-09-12 17:59 ` Conor Dooley
2025-09-13 5:04 ` Guo Ren
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