Re: [PATCH] riscv: Update MIPS vendor id to 0x127.

From: Conor Dooley <conor.dooley@microchip.com>
To: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
Cc: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>,
	"alex@ghiti.fr" <alex@ghiti.fr>,
	"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
	"cfu@wavecomp.com" <cfu@wavecomp.com>,
	"conor@kernel.org" <conor@kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"palmer@dabbelt.com" <palmer@dabbelt.com>,
	"pjw@kernel.org" <pjw@kernel.org>
Subject: Re: [PATCH] riscv: Update MIPS vendor id to 0x127.
Date: Tue, 4 Nov 2025 14:09:08 +0000	[thread overview]
Message-ID: <20251104-reclining-eskimo-9ab425c708d3@wendy> (raw)
In-Reply-To: <bb3a2237-6dde-4231-a016-faf190f9a877@htecgroup.com>

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On Tue, Nov 04, 2025 at 02:06:31PM +0000, Aleksa Paunovic wrote:
> On 11/4/25 14:18, Conor Dooley wrote:
> 
> > On Tue, Nov 04, 2025 at 11:53:49AM +0000, Aleksa Paunovic wrote:
> >> On 11/3/25 23:07, Conor Dooley wrote:
> >>> On Mon, Nov 03, 2025 at 04:05:48PM +0100, Aleksa Paunovic wrote:
> >>>> From: Chao-ying Fu <cfu@wavecomp.com>

While I am here, you have a From: header with Chao-ying it it, but the
patch has not been signed off by them.

> >>>>
> >>>> [1] defines MIPS vendor id as 0x127.
> >>>>
> >>>> [1] https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
> >>>>
> >>>> Fixes: a8fed1bc03ace27902338e4f0d318335883ac847 ("riscv: Add xmipsexectl as a vendor extension")
> >>> Incorrect format for fixes tags!
> >> Will fix that in v2.
> >>
> >>>> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> >>>> ---
> >>>>  arch/riscv/include/asm/vendorid_list.h | 2 +-
> >>>>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>>>
> >>>> diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
> >>>> index 3b09874d7a6dfb8f8aa45b0be41c20711d539e78..55205f7938055ba2b744dba5118bba935bcac008 100644
> >>>> --- a/arch/riscv/include/asm/vendorid_list.h
> >>>> +++ b/arch/riscv/include/asm/vendorid_list.h
> >>>> @@ -9,6 +9,6 @@
> >>>>  #define MICROCHIP_VENDOR_ID	0x029
> >>>>  #define SIFIVE_VENDOR_ID	0x489
> >>>>  #define THEAD_VENDOR_ID		0x5b7
> >>>> -#define MIPS_VENDOR_ID		0x722
> >>>> +#define MIPS_VENDOR_ID		0x127
> >>> How was this ever wrong? Do devices exist with this old ID? Do we need
> >>> to support both as vendor IDs for MIPS?
> >> I'm not sure how it first started, but since we worked on qemu as well, we never noticed any issues while testing. 
> >> It shouldn't cause any problems in the future though.
> > So all the hardware uses the 0x127 id? Where did 0x722 come from?
> > I recall qemu defaults to 0x0, so were none of the mips code paths
> > tested, or were they tested with a qemu modified to use 0x722?
> 
> 
> That is correct, all hardware uses the 0x127 id. 
> 
> I'm not sure where we got 0x722 from - perhaps I or someone else misread the value 
> 
> (0x27 and 0x2 are both mentioned in the Programmer's Guide mvendorid bit descriptions).
> 
> 
> Everything was tested with qemu modified to use 0x722. Please see [1], for example.
> 
> 
> [1] https://patchew.org/QEMU/20250717093833.402237-1-djordje.todorovic@htecgroup.com/20250717093833.402237-4-djordje.todorovic@htecgroup.com/

Okay, cool. Can you put this information into the commit message? It
should really explain what went wrong and what is impacted by the
change.

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