* [PATCH 1/2] riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi
@ 2026-01-13 2:38 Inochi Amaoto
2026-01-13 2:38 ` [PATCH 2/2] riscv: dts: sophgo: fix the node order of SG2042 peripheral Inochi Amaoto
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Inochi Amaoto @ 2026-01-13 2:38 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Han Gao, Nutty Liu, Thomas Gleixner, Zixian Zeng
Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan,
Longbin Li
As we have a separate CPU dtsi file, move the PLIC and CLINT
node to the CPU dtsi file. This will make the sg2042.dtsi force
peripheral devices, and make the CPU dtsi force CPU related
devices.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 305 ++++++++++++++++++++
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 303 -------------------
2 files changed, 305 insertions(+), 303 deletions(-)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
index 94a4b71acad3..509488eee432 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
@@ -2189,4 +2189,309 @@ l2_cache15: cache-controller-15 {
cache-unified;
};
};
+
+ soc {
+ intc: interrupt-controller@7090000000 {
+ compatible = "sophgo,sg2042-plic", "thead,c900-plic";
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
+ interrupt-controller;
+ interrupts-extended =
+ <&cpu0_intc 11>, <&cpu0_intc 9>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>,
+ <&cpu4_intc 11>, <&cpu4_intc 9>,
+ <&cpu5_intc 11>, <&cpu5_intc 9>,
+ <&cpu6_intc 11>, <&cpu6_intc 9>,
+ <&cpu7_intc 11>, <&cpu7_intc 9>,
+ <&cpu8_intc 11>, <&cpu8_intc 9>,
+ <&cpu9_intc 11>, <&cpu9_intc 9>,
+ <&cpu10_intc 11>, <&cpu10_intc 9>,
+ <&cpu11_intc 11>, <&cpu11_intc 9>,
+ <&cpu12_intc 11>, <&cpu12_intc 9>,
+ <&cpu13_intc 11>, <&cpu13_intc 9>,
+ <&cpu14_intc 11>, <&cpu14_intc 9>,
+ <&cpu15_intc 11>, <&cpu15_intc 9>,
+ <&cpu16_intc 11>, <&cpu16_intc 9>,
+ <&cpu17_intc 11>, <&cpu17_intc 9>,
+ <&cpu18_intc 11>, <&cpu18_intc 9>,
+ <&cpu19_intc 11>, <&cpu19_intc 9>,
+ <&cpu20_intc 11>, <&cpu20_intc 9>,
+ <&cpu21_intc 11>, <&cpu21_intc 9>,
+ <&cpu22_intc 11>, <&cpu22_intc 9>,
+ <&cpu23_intc 11>, <&cpu23_intc 9>,
+ <&cpu24_intc 11>, <&cpu24_intc 9>,
+ <&cpu25_intc 11>, <&cpu25_intc 9>,
+ <&cpu26_intc 11>, <&cpu26_intc 9>,
+ <&cpu27_intc 11>, <&cpu27_intc 9>,
+ <&cpu28_intc 11>, <&cpu28_intc 9>,
+ <&cpu29_intc 11>, <&cpu29_intc 9>,
+ <&cpu30_intc 11>, <&cpu30_intc 9>,
+ <&cpu31_intc 11>, <&cpu31_intc 9>,
+ <&cpu32_intc 11>, <&cpu32_intc 9>,
+ <&cpu33_intc 11>, <&cpu33_intc 9>,
+ <&cpu34_intc 11>, <&cpu34_intc 9>,
+ <&cpu35_intc 11>, <&cpu35_intc 9>,
+ <&cpu36_intc 11>, <&cpu36_intc 9>,
+ <&cpu37_intc 11>, <&cpu37_intc 9>,
+ <&cpu38_intc 11>, <&cpu38_intc 9>,
+ <&cpu39_intc 11>, <&cpu39_intc 9>,
+ <&cpu40_intc 11>, <&cpu40_intc 9>,
+ <&cpu41_intc 11>, <&cpu41_intc 9>,
+ <&cpu42_intc 11>, <&cpu42_intc 9>,
+ <&cpu43_intc 11>, <&cpu43_intc 9>,
+ <&cpu44_intc 11>, <&cpu44_intc 9>,
+ <&cpu45_intc 11>, <&cpu45_intc 9>,
+ <&cpu46_intc 11>, <&cpu46_intc 9>,
+ <&cpu47_intc 11>, <&cpu47_intc 9>,
+ <&cpu48_intc 11>, <&cpu48_intc 9>,
+ <&cpu49_intc 11>, <&cpu49_intc 9>,
+ <&cpu50_intc 11>, <&cpu50_intc 9>,
+ <&cpu51_intc 11>, <&cpu51_intc 9>,
+ <&cpu52_intc 11>, <&cpu52_intc 9>,
+ <&cpu53_intc 11>, <&cpu53_intc 9>,
+ <&cpu54_intc 11>, <&cpu54_intc 9>,
+ <&cpu55_intc 11>, <&cpu55_intc 9>,
+ <&cpu56_intc 11>, <&cpu56_intc 9>,
+ <&cpu57_intc 11>, <&cpu57_intc 9>,
+ <&cpu58_intc 11>, <&cpu58_intc 9>,
+ <&cpu59_intc 11>, <&cpu59_intc 9>,
+ <&cpu60_intc 11>, <&cpu60_intc 9>,
+ <&cpu61_intc 11>, <&cpu61_intc 9>,
+ <&cpu62_intc 11>, <&cpu62_intc 9>,
+ <&cpu63_intc 11>, <&cpu63_intc 9>;
+ riscv,ndev = <224>;
+ };
+
+ clint_mswi: interrupt-controller@7094000000 {
+ compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
+ reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
+ interrupts-extended = <&cpu0_intc 3>,
+ <&cpu1_intc 3>,
+ <&cpu2_intc 3>,
+ <&cpu3_intc 3>,
+ <&cpu4_intc 3>,
+ <&cpu5_intc 3>,
+ <&cpu6_intc 3>,
+ <&cpu7_intc 3>,
+ <&cpu8_intc 3>,
+ <&cpu9_intc 3>,
+ <&cpu10_intc 3>,
+ <&cpu11_intc 3>,
+ <&cpu12_intc 3>,
+ <&cpu13_intc 3>,
+ <&cpu14_intc 3>,
+ <&cpu15_intc 3>,
+ <&cpu16_intc 3>,
+ <&cpu17_intc 3>,
+ <&cpu18_intc 3>,
+ <&cpu19_intc 3>,
+ <&cpu20_intc 3>,
+ <&cpu21_intc 3>,
+ <&cpu22_intc 3>,
+ <&cpu23_intc 3>,
+ <&cpu24_intc 3>,
+ <&cpu25_intc 3>,
+ <&cpu26_intc 3>,
+ <&cpu27_intc 3>,
+ <&cpu28_intc 3>,
+ <&cpu29_intc 3>,
+ <&cpu30_intc 3>,
+ <&cpu31_intc 3>,
+ <&cpu32_intc 3>,
+ <&cpu33_intc 3>,
+ <&cpu34_intc 3>,
+ <&cpu35_intc 3>,
+ <&cpu36_intc 3>,
+ <&cpu37_intc 3>,
+ <&cpu38_intc 3>,
+ <&cpu39_intc 3>,
+ <&cpu40_intc 3>,
+ <&cpu41_intc 3>,
+ <&cpu42_intc 3>,
+ <&cpu43_intc 3>,
+ <&cpu44_intc 3>,
+ <&cpu45_intc 3>,
+ <&cpu46_intc 3>,
+ <&cpu47_intc 3>,
+ <&cpu48_intc 3>,
+ <&cpu49_intc 3>,
+ <&cpu50_intc 3>,
+ <&cpu51_intc 3>,
+ <&cpu52_intc 3>,
+ <&cpu53_intc 3>,
+ <&cpu54_intc 3>,
+ <&cpu55_intc 3>,
+ <&cpu56_intc 3>,
+ <&cpu57_intc 3>,
+ <&cpu58_intc 3>,
+ <&cpu59_intc 3>,
+ <&cpu60_intc 3>,
+ <&cpu61_intc 3>,
+ <&cpu62_intc 3>,
+ <&cpu63_intc 3>;
+ };
+
+ clint_mtimer0: timer@70ac004000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu0_intc 7>,
+ <&cpu1_intc 7>,
+ <&cpu2_intc 7>,
+ <&cpu3_intc 7>;
+ };
+
+ clint_mtimer1: timer@70ac014000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu4_intc 7>,
+ <&cpu5_intc 7>,
+ <&cpu6_intc 7>,
+ <&cpu7_intc 7>;
+ };
+
+ clint_mtimer2: timer@70ac024000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu8_intc 7>,
+ <&cpu9_intc 7>,
+ <&cpu10_intc 7>,
+ <&cpu11_intc 7>;
+ };
+
+ clint_mtimer3: timer@70ac034000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu12_intc 7>,
+ <&cpu13_intc 7>,
+ <&cpu14_intc 7>,
+ <&cpu15_intc 7>;
+ };
+
+ clint_mtimer4: timer@70ac044000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu16_intc 7>,
+ <&cpu17_intc 7>,
+ <&cpu18_intc 7>,
+ <&cpu19_intc 7>;
+ };
+
+ clint_mtimer5: timer@70ac054000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu20_intc 7>,
+ <&cpu21_intc 7>,
+ <&cpu22_intc 7>,
+ <&cpu23_intc 7>;
+ };
+
+ clint_mtimer6: timer@70ac064000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu24_intc 7>,
+ <&cpu25_intc 7>,
+ <&cpu26_intc 7>,
+ <&cpu27_intc 7>;
+ };
+
+ clint_mtimer7: timer@70ac074000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu28_intc 7>,
+ <&cpu29_intc 7>,
+ <&cpu30_intc 7>,
+ <&cpu31_intc 7>;
+ };
+
+ clint_mtimer8: timer@70ac084000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu32_intc 7>,
+ <&cpu33_intc 7>,
+ <&cpu34_intc 7>,
+ <&cpu35_intc 7>;
+ };
+
+ clint_mtimer9: timer@70ac094000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu36_intc 7>,
+ <&cpu37_intc 7>,
+ <&cpu38_intc 7>,
+ <&cpu39_intc 7>;
+ };
+
+ clint_mtimer10: timer@70ac0a4000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu40_intc 7>,
+ <&cpu41_intc 7>,
+ <&cpu42_intc 7>,
+ <&cpu43_intc 7>;
+ };
+
+ clint_mtimer11: timer@70ac0b4000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu44_intc 7>,
+ <&cpu45_intc 7>,
+ <&cpu46_intc 7>,
+ <&cpu47_intc 7>;
+ };
+
+ clint_mtimer12: timer@70ac0c4000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu48_intc 7>,
+ <&cpu49_intc 7>,
+ <&cpu50_intc 7>,
+ <&cpu51_intc 7>;
+ };
+
+ clint_mtimer13: timer@70ac0d4000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu52_intc 7>,
+ <&cpu53_intc 7>,
+ <&cpu54_intc 7>,
+ <&cpu55_intc 7>;
+ };
+
+ clint_mtimer14: timer@70ac0e4000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu56_intc 7>,
+ <&cpu57_intc 7>,
+ <&cpu58_intc 7>,
+ <&cpu59_intc 7>;
+ };
+
+ clint_mtimer15: timer@70ac0f4000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu60_intc 7>,
+ <&cpu61_intc 7>,
+ <&cpu62_intc 7>,
+ <&cpu63_intc 7>;
+ };
+ };
};
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index ec99da39150f..e6891f95d479 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -352,309 +352,6 @@ pcie_rc3: pcie@7062800000 {
status = "disabled";
};
- clint_mswi: interrupt-controller@7094000000 {
- compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
- reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
- interrupts-extended = <&cpu0_intc 3>,
- <&cpu1_intc 3>,
- <&cpu2_intc 3>,
- <&cpu3_intc 3>,
- <&cpu4_intc 3>,
- <&cpu5_intc 3>,
- <&cpu6_intc 3>,
- <&cpu7_intc 3>,
- <&cpu8_intc 3>,
- <&cpu9_intc 3>,
- <&cpu10_intc 3>,
- <&cpu11_intc 3>,
- <&cpu12_intc 3>,
- <&cpu13_intc 3>,
- <&cpu14_intc 3>,
- <&cpu15_intc 3>,
- <&cpu16_intc 3>,
- <&cpu17_intc 3>,
- <&cpu18_intc 3>,
- <&cpu19_intc 3>,
- <&cpu20_intc 3>,
- <&cpu21_intc 3>,
- <&cpu22_intc 3>,
- <&cpu23_intc 3>,
- <&cpu24_intc 3>,
- <&cpu25_intc 3>,
- <&cpu26_intc 3>,
- <&cpu27_intc 3>,
- <&cpu28_intc 3>,
- <&cpu29_intc 3>,
- <&cpu30_intc 3>,
- <&cpu31_intc 3>,
- <&cpu32_intc 3>,
- <&cpu33_intc 3>,
- <&cpu34_intc 3>,
- <&cpu35_intc 3>,
- <&cpu36_intc 3>,
- <&cpu37_intc 3>,
- <&cpu38_intc 3>,
- <&cpu39_intc 3>,
- <&cpu40_intc 3>,
- <&cpu41_intc 3>,
- <&cpu42_intc 3>,
- <&cpu43_intc 3>,
- <&cpu44_intc 3>,
- <&cpu45_intc 3>,
- <&cpu46_intc 3>,
- <&cpu47_intc 3>,
- <&cpu48_intc 3>,
- <&cpu49_intc 3>,
- <&cpu50_intc 3>,
- <&cpu51_intc 3>,
- <&cpu52_intc 3>,
- <&cpu53_intc 3>,
- <&cpu54_intc 3>,
- <&cpu55_intc 3>,
- <&cpu56_intc 3>,
- <&cpu57_intc 3>,
- <&cpu58_intc 3>,
- <&cpu59_intc 3>,
- <&cpu60_intc 3>,
- <&cpu61_intc 3>,
- <&cpu62_intc 3>,
- <&cpu63_intc 3>;
- };
-
- clint_mtimer0: timer@70ac004000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu0_intc 7>,
- <&cpu1_intc 7>,
- <&cpu2_intc 7>,
- <&cpu3_intc 7>;
- };
-
- clint_mtimer1: timer@70ac014000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu4_intc 7>,
- <&cpu5_intc 7>,
- <&cpu6_intc 7>,
- <&cpu7_intc 7>;
- };
-
- clint_mtimer2: timer@70ac024000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu8_intc 7>,
- <&cpu9_intc 7>,
- <&cpu10_intc 7>,
- <&cpu11_intc 7>;
- };
-
- clint_mtimer3: timer@70ac034000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu12_intc 7>,
- <&cpu13_intc 7>,
- <&cpu14_intc 7>,
- <&cpu15_intc 7>;
- };
-
- clint_mtimer4: timer@70ac044000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu16_intc 7>,
- <&cpu17_intc 7>,
- <&cpu18_intc 7>,
- <&cpu19_intc 7>;
- };
-
- clint_mtimer5: timer@70ac054000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu20_intc 7>,
- <&cpu21_intc 7>,
- <&cpu22_intc 7>,
- <&cpu23_intc 7>;
- };
-
- clint_mtimer6: timer@70ac064000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu24_intc 7>,
- <&cpu25_intc 7>,
- <&cpu26_intc 7>,
- <&cpu27_intc 7>;
- };
-
- clint_mtimer7: timer@70ac074000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu28_intc 7>,
- <&cpu29_intc 7>,
- <&cpu30_intc 7>,
- <&cpu31_intc 7>;
- };
-
- clint_mtimer8: timer@70ac084000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu32_intc 7>,
- <&cpu33_intc 7>,
- <&cpu34_intc 7>,
- <&cpu35_intc 7>;
- };
-
- clint_mtimer9: timer@70ac094000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu36_intc 7>,
- <&cpu37_intc 7>,
- <&cpu38_intc 7>,
- <&cpu39_intc 7>;
- };
-
- clint_mtimer10: timer@70ac0a4000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu40_intc 7>,
- <&cpu41_intc 7>,
- <&cpu42_intc 7>,
- <&cpu43_intc 7>;
- };
-
- clint_mtimer11: timer@70ac0b4000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu44_intc 7>,
- <&cpu45_intc 7>,
- <&cpu46_intc 7>,
- <&cpu47_intc 7>;
- };
-
- clint_mtimer12: timer@70ac0c4000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu48_intc 7>,
- <&cpu49_intc 7>,
- <&cpu50_intc 7>,
- <&cpu51_intc 7>;
- };
-
- clint_mtimer13: timer@70ac0d4000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu52_intc 7>,
- <&cpu53_intc 7>,
- <&cpu54_intc 7>,
- <&cpu55_intc 7>;
- };
-
- clint_mtimer14: timer@70ac0e4000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu56_intc 7>,
- <&cpu57_intc 7>,
- <&cpu58_intc 7>,
- <&cpu59_intc 7>;
- };
-
- clint_mtimer15: timer@70ac0f4000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu60_intc 7>,
- <&cpu61_intc 7>,
- <&cpu62_intc 7>,
- <&cpu63_intc 7>;
- };
-
- intc: interrupt-controller@7090000000 {
- compatible = "sophgo,sg2042-plic", "thead,c900-plic";
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
- interrupt-controller;
- interrupts-extended =
- <&cpu0_intc 11>, <&cpu0_intc 9>,
- <&cpu1_intc 11>, <&cpu1_intc 9>,
- <&cpu2_intc 11>, <&cpu2_intc 9>,
- <&cpu3_intc 11>, <&cpu3_intc 9>,
- <&cpu4_intc 11>, <&cpu4_intc 9>,
- <&cpu5_intc 11>, <&cpu5_intc 9>,
- <&cpu6_intc 11>, <&cpu6_intc 9>,
- <&cpu7_intc 11>, <&cpu7_intc 9>,
- <&cpu8_intc 11>, <&cpu8_intc 9>,
- <&cpu9_intc 11>, <&cpu9_intc 9>,
- <&cpu10_intc 11>, <&cpu10_intc 9>,
- <&cpu11_intc 11>, <&cpu11_intc 9>,
- <&cpu12_intc 11>, <&cpu12_intc 9>,
- <&cpu13_intc 11>, <&cpu13_intc 9>,
- <&cpu14_intc 11>, <&cpu14_intc 9>,
- <&cpu15_intc 11>, <&cpu15_intc 9>,
- <&cpu16_intc 11>, <&cpu16_intc 9>,
- <&cpu17_intc 11>, <&cpu17_intc 9>,
- <&cpu18_intc 11>, <&cpu18_intc 9>,
- <&cpu19_intc 11>, <&cpu19_intc 9>,
- <&cpu20_intc 11>, <&cpu20_intc 9>,
- <&cpu21_intc 11>, <&cpu21_intc 9>,
- <&cpu22_intc 11>, <&cpu22_intc 9>,
- <&cpu23_intc 11>, <&cpu23_intc 9>,
- <&cpu24_intc 11>, <&cpu24_intc 9>,
- <&cpu25_intc 11>, <&cpu25_intc 9>,
- <&cpu26_intc 11>, <&cpu26_intc 9>,
- <&cpu27_intc 11>, <&cpu27_intc 9>,
- <&cpu28_intc 11>, <&cpu28_intc 9>,
- <&cpu29_intc 11>, <&cpu29_intc 9>,
- <&cpu30_intc 11>, <&cpu30_intc 9>,
- <&cpu31_intc 11>, <&cpu31_intc 9>,
- <&cpu32_intc 11>, <&cpu32_intc 9>,
- <&cpu33_intc 11>, <&cpu33_intc 9>,
- <&cpu34_intc 11>, <&cpu34_intc 9>,
- <&cpu35_intc 11>, <&cpu35_intc 9>,
- <&cpu36_intc 11>, <&cpu36_intc 9>,
- <&cpu37_intc 11>, <&cpu37_intc 9>,
- <&cpu38_intc 11>, <&cpu38_intc 9>,
- <&cpu39_intc 11>, <&cpu39_intc 9>,
- <&cpu40_intc 11>, <&cpu40_intc 9>,
- <&cpu41_intc 11>, <&cpu41_intc 9>,
- <&cpu42_intc 11>, <&cpu42_intc 9>,
- <&cpu43_intc 11>, <&cpu43_intc 9>,
- <&cpu44_intc 11>, <&cpu44_intc 9>,
- <&cpu45_intc 11>, <&cpu45_intc 9>,
- <&cpu46_intc 11>, <&cpu46_intc 9>,
- <&cpu47_intc 11>, <&cpu47_intc 9>,
- <&cpu48_intc 11>, <&cpu48_intc 9>,
- <&cpu49_intc 11>, <&cpu49_intc 9>,
- <&cpu50_intc 11>, <&cpu50_intc 9>,
- <&cpu51_intc 11>, <&cpu51_intc 9>,
- <&cpu52_intc 11>, <&cpu52_intc 9>,
- <&cpu53_intc 11>, <&cpu53_intc 9>,
- <&cpu54_intc 11>, <&cpu54_intc 9>,
- <&cpu55_intc 11>, <&cpu55_intc 9>,
- <&cpu56_intc 11>, <&cpu56_intc 9>,
- <&cpu57_intc 11>, <&cpu57_intc 9>,
- <&cpu58_intc 11>, <&cpu58_intc 9>,
- <&cpu59_intc 11>, <&cpu59_intc 9>,
- <&cpu60_intc 11>, <&cpu60_intc 9>,
- <&cpu61_intc 11>, <&cpu61_intc 9>,
- <&cpu62_intc 11>, <&cpu62_intc 9>,
- <&cpu63_intc 11>, <&cpu63_intc 9>;
- riscv,ndev = <224>;
- };
-
rstgen: reset-controller@7030013000 {
compatible = "sophgo,sg2042-reset";
reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
--
2.52.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/2] riscv: dts: sophgo: fix the node order of SG2042 peripheral
2026-01-13 2:38 [PATCH 1/2] riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi Inochi Amaoto
@ 2026-01-13 2:38 ` Inochi Amaoto
2026-01-15 0:51 ` Chen Wang
2026-01-15 0:49 ` [PATCH 1/2] riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi Chen Wang
2026-01-20 1:16 ` Inochi Amaoto
2 siblings, 1 reply; 8+ messages in thread
From: Inochi Amaoto @ 2026-01-13 2:38 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Han Gao, Nutty Liu, Thomas Gleixner, Zixian Zeng
Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan,
Longbin Li
In sg2042.dtsi, some peripheral device node does not follow the
address order. Reorder them in ascending order by address.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 176 ++++++++++++-------------
1 file changed, 88 insertions(+), 88 deletions(-)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index e6891f95d479..9fddf3f0b3b9 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -264,94 +264,6 @@ clkgen: clock-controller@7030012000 {
#clock-cells = <1>;
};
- pcie_rc0: pcie@7060000000 {
- compatible = "sophgo,sg2042-pcie-host";
- device_type = "pci";
- reg = <0x70 0x60000000 0x0 0x00800000>,
- <0x40 0x00000000 0x0 0x00001000>;
- reg-names = "reg", "cfg";
- linux,pci-domain = <0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>,
- <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>,
- <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>,
- <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
- <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
- bus-range = <0x0 0xff>;
- vendor-id = <0x1f1c>;
- device-id = <0x2042>;
- cdns,no-bar-match-nbits = <48>;
- msi-parent = <&msi>;
- status = "disabled";
- };
-
- pcie_rc1: pcie@7060800000 {
- compatible = "sophgo,sg2042-pcie-host";
- device_type = "pci";
- reg = <0x70 0x60800000 0x0 0x00800000>,
- <0x44 0x00000000 0x0 0x00001000>;
- reg-names = "reg", "cfg";
- linux,pci-domain = <1>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>,
- <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>,
- <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>,
- <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>,
- <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>;
- bus-range = <0x0 0xff>;
- vendor-id = <0x1f1c>;
- device-id = <0x2042>;
- cdns,no-bar-match-nbits = <48>;
- msi-parent = <&msi>;
- status = "disabled";
- };
-
- pcie_rc2: pcie@7062000000 {
- compatible = "sophgo,sg2042-pcie-host";
- device_type = "pci";
- reg = <0x70 0x62000000 0x0 0x00800000>,
- <0x48 0x00000000 0x0 0x00001000>;
- reg-names = "reg", "cfg";
- linux,pci-domain = <2>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>,
- <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>,
- <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>,
- <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>,
- <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>;
- bus-range = <0x0 0xff>;
- vendor-id = <0x1f1c>;
- device-id = <0x2042>;
- cdns,no-bar-match-nbits = <48>;
- msi-parent = <&msi>;
- status = "disabled";
- };
-
- pcie_rc3: pcie@7062800000 {
- compatible = "sophgo,sg2042-pcie-host";
- device_type = "pci";
- reg = <0x70 0x62800000 0x0 0x00800000>,
- <0x4c 0x00000000 0x0 0x00001000>;
- reg-names = "reg", "cfg";
- linux,pci-domain = <3>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>,
- <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>,
- <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>,
- <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>,
- <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>;
- bus-range = <0x0 0xff>;
- vendor-id = <0x1f1c>;
- device-id = <0x2042>;
- cdns,no-bar-match-nbits = <48>;
- msi-parent = <&msi>;
- status = "disabled";
- };
-
rstgen: reset-controller@7030013000 {
compatible = "sophgo,sg2042-reset";
reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
@@ -486,5 +398,93 @@ sd: mmc@704002b000 {
"timer";
status = "disabled";
};
+
+ pcie_rc0: pcie@7060000000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x60000000 0x0 0x00800000>,
+ <0x40 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>,
+ <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ pcie_rc1: pcie@7060800000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x60800000 0x0 0x00800000>,
+ <0x44 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>,
+ <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ pcie_rc2: pcie@7062000000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x62000000 0x0 0x00800000>,
+ <0x48 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>,
+ <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>,
+ <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ pcie_rc3: pcie@7062800000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x62800000 0x0 0x00800000>,
+ <0x4c 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>,
+ <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>,
+ <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>,
+ <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
};
};
--
2.52.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 2/2] riscv: dts: sophgo: fix the node order of SG2042 peripheral
2026-01-13 2:38 ` [PATCH 2/2] riscv: dts: sophgo: fix the node order of SG2042 peripheral Inochi Amaoto
@ 2026-01-15 0:51 ` Chen Wang
0 siblings, 0 replies; 8+ messages in thread
From: Chen Wang @ 2026-01-15 0:51 UTC (permalink / raw)
To: Inochi Amaoto, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Han Gao, Nutty Liu, Thomas Gleixner, Zixian Zeng
Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan,
Longbin Li
On 1/13/2026 10:38 AM, Inochi Amaoto wrote:
> In sg2042.dtsi, some peripheral device node does not follow the
> address order. Reorder them in ascending order by address.
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> ---
> arch/riscv/boot/dts/sophgo/sg2042.dtsi | 176 ++++++++++++-------------
> 1 file changed, 88 insertions(+), 88 deletions(-)
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Thanks,
Chen
[......]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi
2026-01-13 2:38 [PATCH 1/2] riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi Inochi Amaoto
2026-01-13 2:38 ` [PATCH 2/2] riscv: dts: sophgo: fix the node order of SG2042 peripheral Inochi Amaoto
@ 2026-01-15 0:49 ` Chen Wang
2026-01-17 0:37 ` Inochi Amaoto
2026-01-20 1:16 ` Inochi Amaoto
2 siblings, 1 reply; 8+ messages in thread
From: Chen Wang @ 2026-01-15 0:49 UTC (permalink / raw)
To: Inochi Amaoto, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Han Gao, Nutty Liu, Thomas Gleixner, Zixian Zeng
Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan,
Longbin Li
On 1/13/2026 10:38 AM, Inochi Amaoto wrote:
> As we have a separate CPU dtsi file, move the PLIC and CLINT
> node to the CPU dtsi file. This will make the sg2042.dtsi force
> peripheral devices, and make the CPU dtsi force CPU related
> devices.
LGTM, except for the word "force" in the commit message; it seems a bit
odd. Perhaps it would be better to write: "This will make all peripheral
devices are defined in the sg2042.dtsi
and all CPU-related are defined in the CPU dtsi."
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> ---
> arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 305 ++++++++++++++++++++
> arch/riscv/boot/dts/sophgo/sg2042.dtsi | 303 -------------------
> 2 files changed, 305 insertions(+), 303 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> index 94a4b71acad3..509488eee432 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
[......]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi
2026-01-15 0:49 ` [PATCH 1/2] riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi Chen Wang
@ 2026-01-17 0:37 ` Inochi Amaoto
2026-01-17 0:55 ` Chen Wang
0 siblings, 1 reply; 8+ messages in thread
From: Inochi Amaoto @ 2026-01-17 0:37 UTC (permalink / raw)
To: Chen Wang, Inochi Amaoto, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Han Gao, Nutty Liu, Thomas Gleixner, Zixian Zeng
Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan,
Longbin Li
On Thu, Jan 15, 2026 at 08:49:54AM +0800, Chen Wang wrote:
>
> On 1/13/2026 10:38 AM, Inochi Amaoto wrote:
> > As we have a separate CPU dtsi file, move the PLIC and CLINT
> > node to the CPU dtsi file. This will make the sg2042.dtsi force
> > peripheral devices, and make the CPU dtsi force CPU related
> > devices.
> LGTM, except for the word "force" in the commit message; it seems a bit odd.
> Perhaps it would be better to write: "This will make all peripheral devices
> are defined in the sg2042.dtsi
>
> and all CPU-related are defined in the CPU dtsi."
>
> Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
>
Thanks, it should be "focus on", I wrote a wrong word, If it is
OK, I will fix this mistake when merging.
Regards,
Inochi
> >
> > Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> > ---
> > arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 305 ++++++++++++++++++++
> > arch/riscv/boot/dts/sophgo/sg2042.dtsi | 303 -------------------
> > 2 files changed, 305 insertions(+), 303 deletions(-)
> >
> > diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > index 94a4b71acad3..509488eee432 100644
> > --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>
> [......]
>
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi
2026-01-17 0:37 ` Inochi Amaoto
@ 2026-01-17 0:55 ` Chen Wang
0 siblings, 0 replies; 8+ messages in thread
From: Chen Wang @ 2026-01-17 0:55 UTC (permalink / raw)
To: Inochi Amaoto, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Han Gao, Nutty Liu, Thomas Gleixner, Zixian Zeng
Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan,
Longbin Li
On 1/17/2026 8:37 AM, Inochi Amaoto wrote:
> On Thu, Jan 15, 2026 at 08:49:54AM +0800, Chen Wang wrote:
>> On 1/13/2026 10:38 AM, Inochi Amaoto wrote:
>>> As we have a separate CPU dtsi file, move the PLIC and CLINT
>>> node to the CPU dtsi file. This will make the sg2042.dtsi force
>>> peripheral devices, and make the CPU dtsi force CPU related
>>> devices.
>> LGTM, except for the word "force" in the commit message; it seems a bit odd.
>> Perhaps it would be better to write: "This will make all peripheral devices
>> are defined in the sg2042.dtsi
>>
>> and all CPU-related are defined in the CPU dtsi."
>>
>> Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
>>
> Thanks, it should be "focus on", I wrote a wrong word, If it is
> OK, I will fix this mistake when merging.
>
> Regards,
> Inochi
I think it's okay.
Thanks,
Chen
>>> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
>>> ---
>>> arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 305 ++++++++++++++++++++
>>> arch/riscv/boot/dts/sophgo/sg2042.dtsi | 303 -------------------
>>> 2 files changed, 305 insertions(+), 303 deletions(-)
>>>
>>> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>>> index 94a4b71acad3..509488eee432 100644
>>> --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>>> +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>> [......]
>>
>>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi
2026-01-13 2:38 [PATCH 1/2] riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi Inochi Amaoto
2026-01-13 2:38 ` [PATCH 2/2] riscv: dts: sophgo: fix the node order of SG2042 peripheral Inochi Amaoto
2026-01-15 0:49 ` [PATCH 1/2] riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi Chen Wang
@ 2026-01-20 1:16 ` Inochi Amaoto
2026-01-20 2:48 ` Inochi Amaoto
2 siblings, 1 reply; 8+ messages in thread
From: Inochi Amaoto @ 2026-01-20 1:16 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang, Han Gao,
Nutty Liu, Thomas Gleixner, Zixian Zeng, Inochi Amaoto
Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan,
Longbin Li
On Tue, 13 Jan 2026 10:38:26 +0800, Inochi Amaoto wrote:
> As we have a separate CPU dtsi file, move the PLIC and CLINT
> node to the CPU dtsi file. This will make the sg2042.dtsi force
> peripheral devices, and make the CPU dtsi force CPU related
> devices.
>
>
Applied to dt/riscv, thanks!
[1/2] riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi
https://github.com/sophgo/linux/commit/5e6836e735f9c9c5e8e1d1dce02dfed5fe566e8f
[2/2] riscv: dts: sophgo: fix the node order of SG2042 peripheral
https://github.com/sophgo/linux/commit/ebb87dd74c34a76e1e93041e9329cf9269be35ed
Thanks,
Inochi
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 1/2] riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi
2026-01-20 1:16 ` Inochi Amaoto
@ 2026-01-20 2:48 ` Inochi Amaoto
0 siblings, 0 replies; 8+ messages in thread
From: Inochi Amaoto @ 2026-01-20 2:48 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang, Han Gao,
Nutty Liu, Thomas Gleixner, Zixian Zeng, Inochi Amaoto
Cc: devicetree, linux-riscv, sophgo, linux-kernel, Yixun Lan,
Longbin Li
On Tue, 13 Jan 2026 10:38:26 +0800, Inochi Amaoto wrote:
> As we have a separate CPU dtsi file, move the PLIC and CLINT
> node to the CPU dtsi file. This will make the sg2042.dtsi force
> peripheral devices, and make the CPU dtsi force CPU related
> devices.
>
>
Applied to dt/riscv, thanks!
[1/2] riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi
https://github.com/sophgo/linux/commit/5e6836e735f9c9c5e8e1d1dce02dfed5fe566e8f
[2/2] riscv: dts: sophgo: fix the node order of SG2042 peripheral
https://github.com/sophgo/linux/commit/ebb87dd74c34a76e1e93041e9329cf9269be35ed
Thanks,
Inochi
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2026-01-20 4:54 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-01-13 2:38 [PATCH 1/2] riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi Inochi Amaoto
2026-01-13 2:38 ` [PATCH 2/2] riscv: dts: sophgo: fix the node order of SG2042 peripheral Inochi Amaoto
2026-01-15 0:51 ` Chen Wang
2026-01-15 0:49 ` [PATCH 1/2] riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi Chen Wang
2026-01-17 0:37 ` Inochi Amaoto
2026-01-17 0:55 ` Chen Wang
2026-01-20 1:16 ` Inochi Amaoto
2026-01-20 2:48 ` Inochi Amaoto
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox