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From: Andrew Jones <andrew.jones@oss.qualcomm.com>
To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	kvm-riscv@lists.infradead.org
Cc: "Paul Walmsley" <pjw@kernel.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Anup Patel" <anup@brainfault.org>,
	"Clément Léger" <cleger@rivosinc.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Guodong Xu" <guodong@riscstar.com>,
	"Charlie Jenkins" <charlie@rivosinc.com>,
	"Charlie Jenkins" <thecharlesjenkins@gmail.com>,
	"Samuel Holland" <samuel.holland@sifive.com>
Subject: [RFC PATCH v1 11/11] riscv: /proc/cpuinfo: Also output rva20 and rva22 isa bases
Date: Thu,  5 Feb 2026 18:23:49 -0600	[thread overview]
Message-ID: <20260206002349.96740-12-andrew.jones@oss.qualcomm.com> (raw)
In-Reply-To: <20260206002349.96740-1-andrew.jones@oss.qualcomm.com>

Include rva(20|22)(u|s)64 isa bases in the output when they are
detected.

Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
---
 arch/riscv/include/asm/cpufeature.h |  4 ++
 arch/riscv/kernel/cpu.c             |  4 ++
 arch/riscv/kernel/cpufeature.c      | 65 +++++++++++++++++++++++------
 3 files changed, 61 insertions(+), 12 deletions(-)

diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
index e750735c5686..41431e89bb3b 100644
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -27,6 +27,10 @@ struct riscv_cpuinfo {
 
 enum {
 	RISCV_ISA_BASE_IMA,
+	RISCV_ISA_BASE_RVA20U64,
+	RISCV_ISA_BASE_RVA20S64,
+	RISCV_ISA_BASE_RVA22U64,
+	RISCV_ISA_BASE_RVA22S64,
 	RISCV_ISA_BASE_RVA23U64,
 	RISCV_ISA_BASE_RVA23S64,
 	RISCV_NR_ISA_BASES,
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 228867d7dc00..007958744ae5 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -313,6 +313,10 @@ static const char * const riscv_isa_base_names[] = {
 #else
 	[RISCV_ISA_BASE_IMA] = "rv64ima",
 #endif
+	[RISCV_ISA_BASE_RVA20U64] = "rva20u64",
+	[RISCV_ISA_BASE_RVA20S64] = "rva20s64",
+	[RISCV_ISA_BASE_RVA22U64] = "rva22u64",
+	[RISCV_ISA_BASE_RVA22S64] = "rva22s64",
 	[RISCV_ISA_BASE_RVA23U64] = "rva23u64",
 	[RISCV_ISA_BASE_RVA23S64] = "rva23s64",
 };
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 07a42545e9e0..ac46b974e5e4 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -1281,33 +1281,74 @@ void riscv_set_isa_bases(unsigned long *bases, const unsigned long *isa_bitmap)
 
 	set_bit(RISCV_ISA_BASE_IMA, bases);
 
-	/* RVA23U64 */
-
-	/* Zic64b and Supm with PMLEN=7 */
-	if (riscv_cbom_block_size != 64 ||
-	    riscv_cbop_block_size != 64 ||
-	    riscv_cboz_block_size != 64 ||
-	    !riscv_have_user_pmlen_7)
-		return;
-
+	/* RVA20U64 */
 	set_bit(RISCV_ISA_EXT_F, ext_mask);
 	set_bit(RISCV_ISA_EXT_D, ext_mask);
 	set_bit(RISCV_ISA_EXT_C, ext_mask);
-	set_bit(RISCV_ISA_EXT_B, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZICSR, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZICNTR, ext_mask);
-	set_bit(RISCV_ISA_EXT_ZIHPM, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZICCIF, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZICCRSE, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZICCAMOA, ext_mask);
-	set_bit(RISCV_ISA_EXT_ZICCLSM, ext_mask);
+	/* Spec says Za128rs, but Za64rs is compatible and mandated by later profiles */
 	set_bit(RISCV_ISA_EXT_ZA64RS, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZICCLSM, ext_mask);
+
+	if (bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX))
+		return;
+
+	set_bit(RISCV_ISA_BASE_RVA20U64, bases);
+
+	/* RVA20S64 */
+	set_bit(RISCV_ISA_EXT_ZIFENCEI, ext_mask);
+	/* TODO: Ss1p11 */
+	/* Svbare, Sv39 -- assumed */
+	set_bit(RISCV_ISA_EXT_SVADE, ext_mask);
+	/* TODO: Ssccptr, Sstvecd, Sstvala */
+
+	if (/*TODO*/ false && !bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX))
+		set_bit(RISCV_ISA_BASE_RVA20S64, bases);
+
+	/* RVA22U64 */
+
+	/* Zic64b */
+	if (riscv_cbom_block_size != 64 ||
+	    riscv_cbop_block_size != 64 ||
+	    riscv_cboz_block_size != 64)
+		return;
+
+	set_bit(RISCV_ISA_EXT_B, ext_mask);
+	set_bit(RISCV_ISA_EXT_ZIHPM, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZIHINTPAUSE, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZICBOM, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZICBOP, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZICBOZ, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZFHMIN, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZKT, ext_mask);
+
+	if (bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX))
+		return;
+
+	set_bit(RISCV_ISA_BASE_RVA22U64, bases);
+
+	/* RVA22S64 */
+	set_bit(RISCV_ISA_EXT_ZIFENCEI, ext_mask);
+	/* TODO: Ss1p12 */
+	/* Svbare, Sv39 -- assumed */
+	set_bit(RISCV_ISA_EXT_SVADE, ext_mask);
+	/* TODO: Ssccptr, Sstvecd, Sstvala, Sscounterenw */
+	set_bit(RISCV_ISA_EXT_SVPBMT, ext_mask);
+	set_bit(RISCV_ISA_EXT_SVINVAL, ext_mask);
+
+	if (/*TODO*/ false && !bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX))
+		set_bit(RISCV_ISA_BASE_RVA22S64, bases);
+
+	/* RVA23U64 */
+
+	/* Supm with PMLEN=7 */
+	if (!riscv_have_user_pmlen_7)
+		return;
+
 	set_bit(RISCV_ISA_EXT_V, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZVFHMIN, ext_mask);
 	set_bit(RISCV_ISA_EXT_ZVBB, ext_mask);
-- 
2.43.0


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  parent reply	other threads:[~2026-02-06  0:24 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-06  0:23 [RFC PATCH v1 00/11] riscv: hwprobe: Introduce rva23u64 base behavior Andrew Jones
2026-02-06  0:23 ` [RFC PATCH v1 01/11] riscv: hwprobe: add support for RISCV_HWPROBE_KEY_IMA_EXT_1 Andrew Jones
2026-02-06  0:23 ` [RFC PATCH v1 02/11] RISC-V: Add Zicclsm to cpufeature and hwprobe Andrew Jones
2026-02-06  0:23 ` [RFC PATCH v1 03/11] riscv: Standardize extension capitilization Andrew Jones
2026-02-06  0:23 ` [RFC PATCH v1 04/11] riscv: Add B to hwcap Andrew Jones
2026-02-21 10:49   ` Guodong Xu
2026-02-24 23:04     ` Andrew Jones
2026-03-06  2:17       ` Guodong Xu
2026-03-06 18:27         ` Andrew Jones
2026-03-06 18:50           ` Conor Dooley
2026-03-06 19:04             ` Andrew Jones
2026-02-06  0:23 ` [RFC PATCH v1 05/11] riscv: hwprobe.rst: Replace tabs with spaces Andrew Jones
2026-02-06  0:23 ` [RFC PATCH v1 06/11] riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to hwprobe Andrew Jones
2026-02-21 10:50   ` Guodong Xu
2026-02-24 23:22     ` Andrew Jones
2026-02-06  0:23 ` [RFC PATCH v1 07/11] riscv: Export have_user_pmlen* booleans Andrew Jones
2026-02-21 10:50   ` Guodong Xu
2026-02-24 23:32     ` Andrew Jones
2026-02-06  0:23 ` [RFC PATCH v1 08/11] riscv: hwprobe: Introduce rva23u64 base behavior Andrew Jones
2026-02-08 16:15   ` Andrew Jones
2026-02-21 10:51   ` Guodong Xu
2026-02-25  0:03     ` Andrew Jones
2026-03-06 12:29       ` Guodong Xu
2026-03-06 18:31         ` Andrew Jones
2026-03-06 12:08   ` Guodong Xu
2026-03-06 18:33     ` Andrew Jones
2026-02-06  0:23 ` [RFC PATCH v1 09/11] riscv: selftests: hwprobe: Check rva23u64 consistency Andrew Jones
2026-02-06  0:23 ` [RFC PATCH v1 10/11] riscv: /proc/cpuinfo: Add rva23 bases to output Andrew Jones
2026-02-21 10:52   ` Guodong Xu
2026-02-25  0:08     ` Andrew Jones
2026-03-06 12:47       ` Guodong Xu
2026-03-06 18:34         ` Andrew Jones
2026-02-06  0:23 ` Andrew Jones [this message]
2026-03-05  0:58 ` [RFC PATCH v1 00/11] riscv: hwprobe: Introduce rva23u64 base behavior Charlie Jenkins

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