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From: Andrew Jones <andrew.jones@oss.qualcomm.com>
To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	kvm-riscv@lists.infradead.org
Cc: "Paul Walmsley" <pjw@kernel.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Anup Patel" <anup@brainfault.org>,
	"Clément Léger" <cleger@rivosinc.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Guodong Xu" <guodong@riscstar.com>,
	"Charlie Jenkins" <charlie@rivosinc.com>,
	"Charlie Jenkins" <thecharlesjenkins@gmail.com>,
	"Samuel Holland" <samuel.holland@sifive.com>
Subject: [RFC PATCH v1 05/11] riscv: hwprobe.rst: Replace tabs with spaces
Date: Thu,  5 Feb 2026 18:23:43 -0600	[thread overview]
Message-ID: <20260206002349.96740-6-andrew.jones@oss.qualcomm.com> (raw)
In-Reply-To: <20260206002349.96740-1-andrew.jones@oss.qualcomm.com>

Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
---
 Documentation/arch/riscv/hwprobe.rst | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 0598c9ddd73f..4484f2a7f798 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -362,7 +362,7 @@ The following keys are defined:
 
     * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendor
         extension is supported in the T-Head ISA extensions spec starting from
-	commit a18c801634 ("Add T-Head VECTOR vendor extension. ").
+        commit a18c801634 ("Add T-Head VECTOR vendor extension. ").
 
 * :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which
   represents the size of the Zicbom block in bytes.
@@ -375,19 +375,19 @@ The following keys are defined:
 
     * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD`: The Xsfqmaccdod vendor
         extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
-	Extensions Specification.
+        Extensions Specification.
 
     * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`: The Xsfqmaccqoq vendor
         extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
-	Instruction Extensions Specification.
+        Instruction Extensions Specification.
 
     * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`: The Xsfvfnrclipxfqf
         vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged
-	Clip Instructions Extensions Specification.
+        Clip Instructions Extensions Specification.
 
     * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq
         vendor extension is supported in version 1.0 of Matrix Multiply Accumulate
-	Instruction Extensions Specification.
+        Instruction Extensions Specification.
 
 * :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which
   represents the size of the Zicbop block in bytes.
-- 
2.43.0


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  parent reply	other threads:[~2026-02-06  0:24 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-06  0:23 [RFC PATCH v1 00/11] riscv: hwprobe: Introduce rva23u64 base behavior Andrew Jones
2026-02-06  0:23 ` [RFC PATCH v1 01/11] riscv: hwprobe: add support for RISCV_HWPROBE_KEY_IMA_EXT_1 Andrew Jones
2026-02-06  0:23 ` [RFC PATCH v1 02/11] RISC-V: Add Zicclsm to cpufeature and hwprobe Andrew Jones
2026-02-06  0:23 ` [RFC PATCH v1 03/11] riscv: Standardize extension capitilization Andrew Jones
2026-02-06  0:23 ` [RFC PATCH v1 04/11] riscv: Add B to hwcap Andrew Jones
2026-02-21 10:49   ` Guodong Xu
2026-02-24 23:04     ` Andrew Jones
2026-03-06  2:17       ` Guodong Xu
2026-03-06 18:27         ` Andrew Jones
2026-03-06 18:50           ` Conor Dooley
2026-03-06 19:04             ` Andrew Jones
2026-02-06  0:23 ` Andrew Jones [this message]
2026-02-06  0:23 ` [RFC PATCH v1 06/11] riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to hwprobe Andrew Jones
2026-02-21 10:50   ` Guodong Xu
2026-02-24 23:22     ` Andrew Jones
2026-02-06  0:23 ` [RFC PATCH v1 07/11] riscv: Export have_user_pmlen* booleans Andrew Jones
2026-02-21 10:50   ` Guodong Xu
2026-02-24 23:32     ` Andrew Jones
2026-02-06  0:23 ` [RFC PATCH v1 08/11] riscv: hwprobe: Introduce rva23u64 base behavior Andrew Jones
2026-02-08 16:15   ` Andrew Jones
2026-02-21 10:51   ` Guodong Xu
2026-02-25  0:03     ` Andrew Jones
2026-03-06 12:29       ` Guodong Xu
2026-03-06 18:31         ` Andrew Jones
2026-03-06 12:08   ` Guodong Xu
2026-03-06 18:33     ` Andrew Jones
2026-02-06  0:23 ` [RFC PATCH v1 09/11] riscv: selftests: hwprobe: Check rva23u64 consistency Andrew Jones
2026-02-06  0:23 ` [RFC PATCH v1 10/11] riscv: /proc/cpuinfo: Add rva23 bases to output Andrew Jones
2026-02-21 10:52   ` Guodong Xu
2026-02-25  0:08     ` Andrew Jones
2026-03-06 12:47       ` Guodong Xu
2026-03-06 18:34         ` Andrew Jones
2026-02-06  0:23 ` [RFC PATCH v1 11/11] riscv: /proc/cpuinfo: Also output rva20 and rva22 isa bases Andrew Jones
2026-03-05  0:58 ` [RFC PATCH v1 00/11] riscv: hwprobe: Introduce rva23u64 base behavior Charlie Jenkins

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