* [PATCH v8 01/22] dt-bindings: pincfg-node: Add property 'input-debounce-ns'
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 02/22] pinctrl: pinconf-generic: " Changhuang Liang
` (20 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
The StarFive JHB100 SoC hardware supports debounce time configuration
with nanosecond granularity. The existing 'input-debounce' property
uses microseconds, which is insufficient to accurately represent the
hardware's finer timing steps.
Add the property 'input-debounce-ns' to specify debounce time in
nanoseconds as an alternative to the existing 'input-debounce' which
uses microseconds. Make the new property unavailable when the existing
property 'input-debounce' is selected to prevent conflicting definitions.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
.../devicetree/bindings/pinctrl/pincfg-node.yaml | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml b/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
index 97dbce8a261f..17a6270dce31 100644
--- a/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
@@ -104,6 +104,10 @@ properties:
description: Takes the debounce time in usec as argument or 0 to disable
debouncing
+ input-debounce-ns:
+ description: Takes the debounce time in nsec as argument or 0 to disable
+ debouncing
+
power-source:
$ref: /schemas/types.yaml#/definitions/uint32
description: select between different power supplies
@@ -214,6 +218,13 @@ allOf:
input-schmitt-enable: false
input-schmitt-microvolt: false
+ - if:
+ required:
+ - input-debounce
+ then:
+ properties:
+ input-debounce-ns: false
+
- if:
required:
- drive-strength
--
2.25.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 02/22] pinctrl: pinconf-generic: Add property 'input-debounce-ns'
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 01/22] dt-bindings: pincfg-node: Add property 'input-debounce-ns' Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 03/22] dt-bindings: pinctrl: Add starfive,jhb100-sys0-pinctrl Changhuang Liang
` (19 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add 'input-debounce-ns' to the generic parameters used for parsing DT
files, along with the corresponding configuration parameter
PIN_CONFIG_INPUT_DEBOUNCE_NS. This allows debounce time to be specified
in nanoseconds as an alternative to the existing 'input-debounce'
property which uses microseconds
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/pinconf-generic.c | 2 ++
include/linux/pinctrl/pinconf-generic.h | 5 +++++
2 files changed, 7 insertions(+)
diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
index 95c803c40a7d..36845517984e 100644
--- a/drivers/pinctrl/pinconf-generic.c
+++ b/drivers/pinctrl/pinconf-generic.c
@@ -43,6 +43,7 @@ static const struct pin_config_item conf_items[] = {
PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH, "output drive strength", "mA", true),
PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH_UA, "output drive strength", "uA", true),
PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec", true),
+ PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE_NS, "input debounce", "nsec", true),
PCONFDUMP(PIN_CONFIG_INPUT_ENABLE, "input enabled", NULL, false),
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL, false),
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_UV, "input schmitt threshold", "uV", true),
@@ -185,6 +186,7 @@ static const struct pinconf_generic_params dt_params[] = {
{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
{ "drive-strength-microamp", PIN_CONFIG_DRIVE_STRENGTH_UA, 0 },
{ "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
+ { "input-debounce-ns", PIN_CONFIG_INPUT_DEBOUNCE_NS, 0 },
{ "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
{ "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
{ "input-schmitt", PIN_CONFIG_INPUT_SCHMITT, 0 },
diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h
index a5d4b2d8633a..1df63c732b99 100644
--- a/include/linux/pinctrl/pinconf-generic.h
+++ b/include/linux/pinctrl/pinconf-generic.h
@@ -71,6 +71,10 @@ struct pinctrl_map;
* which means it will wait for signals to settle when reading inputs. The
* argument gives the debounce time in usecs. Setting the
* argument to zero turns debouncing off.
+ * @PIN_CONFIG_INPUT_DEBOUNCE_NS: this will configure the pin to debounce mode,
+ * which means it will wait for signals to settle when reading inputs. The
+ * argument gives the debounce time in nsecs. Setting the
+ * argument to zero turns debouncing off.
* @PIN_CONFIG_INPUT_ENABLE: enable the pin's input. Note that this does not
* affect the pin's ability to drive output. 1 enables input, 0 disables
* input.
@@ -143,6 +147,7 @@ enum pin_config_param {
PIN_CONFIG_DRIVE_STRENGTH,
PIN_CONFIG_DRIVE_STRENGTH_UA,
PIN_CONFIG_INPUT_DEBOUNCE,
+ PIN_CONFIG_INPUT_DEBOUNCE_NS,
PIN_CONFIG_INPUT_ENABLE,
PIN_CONFIG_INPUT_SCHMITT,
PIN_CONFIG_INPUT_SCHMITT_ENABLE,
--
2.25.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 03/22] dt-bindings: pinctrl: Add starfive,jhb100-sys0-pinctrl
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 01/22] dt-bindings: pincfg-node: Add property 'input-debounce-ns' Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 02/22] pinctrl: pinconf-generic: " Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 04/22] pinctrl: starfive: Add StarFive JHB100 sys0 controller driver Changhuang Liang
` (18 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC System-0(sys0) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../pinctrl/starfive,jhb100-sys0-pinctrl.yaml | 164 ++++++++++++++++++
1 file changed, 164 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml
new file mode 100644
index 000000000000..a6f8d1b5c459
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml
@@ -0,0 +1,164 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys0-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 System-0 Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "sys0" pinctrl domain.
+
+ The "sys0" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO pad configuration.
+ - GPIO interrupt handling.
+
+ In the SYS0 Pin Controller, there are 4 multi-function GPIO_PADs. Each of
+ them can be multiplexed to different hardware blocks through function
+ selection and each iopad has a maximum of up to 2 functions - 0 and 1.
+ Function 0 is the default function which is generally the GPIO function
+ (or occasionally, it can be a peripheral signal).
+ Function 1 is the alternate function or peripheral signal that can be
+ routed to the iopad. The function selection is carried out by writing
+ the function number to the iopad function select register.
+
+ Each iopad is configurable with parameters such as input-enable, internal
+ pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
+ debounce nanoseconds.
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-sys0-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges: true
+
+ gpio-line-names: true
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate, input debounce and
+ drive-strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ additionalProperties: false
+
+ properties:
+ pins:
+ description:
+ The list of IOs that properties in the pincfg node apply to.
+
+ function:
+ description:
+ A string containing the name of the function to mux for these
+ pins.
+ enum: [ auxpwrgood, gpio, hbled, pe2rst_out ]
+
+ bias-disable: true
+
+ bias-pull-down:
+ type: boolean
+
+ bias-pull-up:
+ type: boolean
+
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 4000, 8000, 12000 ]
+
+ input-debounce-ns:
+ minimum: 0
+ maximum: 10485680
+ description:
+ Debounce time in nanoseconds. The hardware counts in 80 ns
+ stages with a 17-bit counter, so the maximum is 10485680 ns.
+
+ input-disable: true
+
+ input-enable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow
+ 1: fast
+
+required:
+ - compatible
+ - reg
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_sys0: pinctrl@13080000 {
+ compatible = "starfive,jhb100-sys0-pinctrl";
+ reg = <0x0 0x13080000 0x0 0x800>;
+ resets = <&sys0crg 2>;
+ interrupts = <56>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_sys0 0 0 4>;
+ };
+ };
--
2.25.1
_______________________________________________
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linux-riscv@lists.infradead.org
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 04/22] pinctrl: starfive: Add StarFive JHB100 sys0 controller driver
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (2 preceding siblings ...)
2026-09-10 10:03 ` [PATCH v8 03/22] dt-bindings: pinctrl: Add starfive,jhb100-sys0-pinctrl Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 05/22] dt-bindings: pinctrl: Add starfive,jhb100-sys0h-pinctrl Changhuang Liang
` (17 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC System-0(sys0) pinctrl
controller.
Simultaneously add a generic pinctrl driver framework for registering
the pinctrl of other domains (sys1, sys2, and so on) in the JHB100 SoC.
Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Alex Soo <yuklin.soo@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
MAINTAINERS | 8 +
drivers/pinctrl/starfive/Kconfig | 19 +
drivers/pinctrl/starfive/Makefile | 3 +
.../starfive/pinctrl-starfive-jhb100-sys0.c | 121 ++
.../starfive/pinctrl-starfive-jhb100.c | 1446 +++++++++++++++++
.../starfive/pinctrl-starfive-jhb100.h | 153 ++
6 files changed, 1750 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0.c
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100.c
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100.h
diff --git a/MAINTAINERS b/MAINTAINERS
index e2b317c57a49..08201752d14a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25910,6 +25910,14 @@ S: Supported
F: Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml
F: drivers/irqchip/irq-starfive-jhb100-intc.c
+STARFIVE JHB100 PINCTRL DRIVERS
+M: Changhuang Liang <changhuang.liang@starfivetech.com>
+M: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
+L: linux-gpio@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/pinctrl/starfive,jhb1*.yaml
+F: drivers/pinctrl/starfive/pinctrl-starfive-jhb1*
+
STARFIVE JHB100 RESET CONTROLLER DRIVERS
M: Changhuang Liang <changhuang.liang@starfivetech.com>
S: Maintained
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index a9a7cb101684..b3cb513c23de 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -47,3 +47,22 @@ config PINCTRL_STARFIVE_JH7110_AON
This also provides an interface to the GPIO pins not used by other
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+
+config PINCTRL_STARFIVE_JHB100
+ bool
+ depends on OF
+ select GENERIC_PINCTRL
+ select GPIOLIB
+ select GPIOLIB_IRQCHIP
+ select OF_GPIO
+
+config PINCTRL_STARFIVE_JHB100_SYS0
+ tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select PINCTRL_STARFIVE_JHB100
+ default ARCH_STARFIVE
+ help
+ Say yes here to support system-0 pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index ee0d32d085cb..c0d368f413bc 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -5,3 +5,6 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7100) += pinctrl-starfive-jh7100.o
obj-$(CONFIG_PINCTRL_STARFIVE_JH7110) += pinctrl-starfive-jh7110.o
obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_SYS) += pinctrl-starfive-jh7110-sys.o
obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o
+
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0.c
new file mode 100644
index 000000000000..ad6f889f7d1c
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC System-0 domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+/* sys0 pad numbers */
+#define PADNUM_SYS0_GPIO_A2 2
+#define PADNUM_SYS0_GPIO_A3 3
+
+static const struct jhb100_pin_layout_desc jhb100_sys0_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 3, .name = "gpio", .gpio_func_sel = 0, },
+ { .pin_start = 3, .pin_cnt = 1, .name = "bmcpcierp_pe2rst_out", .gpio_func_sel = 1, },
+ { .pin_start = 4, .pin_cnt = 1, .name = "testen", .gpio_func_sel = -1, },
+ { .pin_start = 5, .pin_cnt = 1, .name = "syspok_in", .gpio_func_sel = -1, },
+ { .pin_start = 6, .pin_cnt = 1, .name = "sysrstn_in", .gpio_func_sel = -1, },
+ { .pin_start = 7, .pin_cnt = 1, .name = "perstn0_in", .gpio_func_sel = -1, },
+ { .pin_start = 8, .pin_cnt = 1, .name = "perstn1_in", .gpio_func_sel = -1, },
+ { .pin_start = 9, .pin_cnt = 1, .name = "aprstn_out", .gpio_func_sel = -1, },
+ { .pin_start = 10, .pin_cnt = 1, .name = "pcierp_wake", .gpio_func_sel = -1, },
+ { 0xff },
+};
+
+static const struct config_reg_layout_desc jhb100_sys0_pinctrl_crl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 4,
+ .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 },
+ .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 },
+ .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 },
+ .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 },
+ .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 },
+ .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 },
+ .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 },
+ },
+ {
+ .pin_start = 4,
+ .pin_cnt = 5,
+ .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 0, .width = 1 },
+ },
+ {
+ .pin_start = 9,
+ .pin_cnt = 1,
+ .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 },
+ .fields[PAD_CFG_SLEW_RATE] = { .shift = 2, .width = 1 },
+ },
+ {
+ .pin_start = 10,
+ .pin_cnt = 1,
+ .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 },
+ .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 },
+ .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 },
+ .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 },
+ .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 },
+ .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 },
+ },
+ { 0xff },
+};
+
+static const struct starfive_pinctrl_regs jhb100_sys0_pinctrl_regs = {
+ .func_sel = { .reg = 0x44, .width_per_pin = 2 },
+ .config = 0x0c,
+ .output = 0x38,
+ .output_en = 0x3c,
+ .gpio_status = 0x40,
+ .irq_en = 0x48,
+ .irq_status = 0x4c,
+ .irq_clr = 0x50,
+ .irq_trigger = 0x54,
+ .irq_level = 0x58,
+ .irq_both_edge = 0x5c,
+ .irq_edge = 0x60,
+};
+
+static const struct jhb100_pinctrl_func_maps jhb100_func_maps_sys0[] = {
+ { .func = "auxpwrgood", .val = 1 },
+ { .func = "gpio", .val = 0,
+ .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_SYS0_GPIO_A2) },
+ { .func = "gpio", .val = 1,
+ .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_SYS0_GPIO_A3) },
+ { .func = "hbled", .val = 1 },
+ { .func = "pe2rst_out", .val = 0 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_sys0_pinctrl_info = {
+ .name = "jhb100-sys0",
+ .pl_desc = jhb100_sys0_pl_desc,
+ .crl_desc = jhb100_sys0_pinctrl_crl_desc,
+ .regs = &jhb100_sys0_pinctrl_regs,
+ .fmaps = jhb100_func_maps_sys0,
+ .num_maps = ARRAY_SIZE(jhb100_func_maps_sys0),
+};
+
+static const struct of_device_id jhb100_sys0_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-sys0-pinctrl",
+ .data = &jhb100_sys0_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_sys0_pinctrl_of_match);
+
+static struct platform_driver jhb100_sys0_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-sys0-pinctrl",
+ .of_match_table = jhb100_sys0_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_sys0_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC System-0 domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100.c
new file mode 100644
index 000000000000..462a26697b88
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100.c
@@ -0,0 +1,1446 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/minmax.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/seq_file.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinctrl-utils.h"
+#include "../pinmux.h"
+#include "pinctrl-starfive-jhb100.h"
+
+#define GPOEN_ENABLE 0
+#define GPOEN_DISABLE 1
+
+#define JHB100_DEBOUNCE_WIDTH_STAGES_MAX GENMASK(16, 0)
+#define JHB100_DEBOUNCE_WIDTH_STAGE_NS 80
+
+/* mode select */
+#define JHB100_PUSH_PULL 0
+#define JHB100_OPEN_DRAIN 1
+#define JHB100_LEGACY_FAST_MODE_PLUS 2
+#define JHB100_LEGACY_FAST_MODE 3
+
+/* i2c open-drain pull-up select */
+#define JHB100_I2C_OPEN_DRAIN_PU_600_OHMS 0
+#define JHB100_I2C_OPEN_DRAIN_PU_900_OHMS 1
+#define JHB100_I2C_OPEN_DRAIN_PU_1200_OHMS 2
+#define JHB100_I2C_OPEN_DRAIN_PU_2000_OHMS 3
+
+/*
+ * On the StarFive JHB100 SoC, every 32 GPIOs correspond to one register address. The
+ * driver abstracts every 32 GPIOs into one GPIO bank to simplify code implementation.
+ */
+#define JHB100_NR_GPIOS_PER_BANK 32
+#define JHB100_BANK_OFFSET(n) ((n) * 4)
+#define JHB100_GPIO_BANK(gpio) ((gpio) / JHB100_NR_GPIOS_PER_BANK)
+#define JHB100_GPIO_MASK(gpio) BIT((gpio) % JHB100_NR_GPIOS_PER_BANK)
+#define JHB100_GPIO_REG_OFFSET(gpio) JHB100_BANK_OFFSET(JHB100_GPIO_BANK(gpio))
+
+static int jhb100_map_get_func_val(struct jhb100_pinctrl *sfp, const char *function,
+ unsigned int pin)
+{
+ const struct jhb100_pinctrl_func_maps *fmaps = sfp->info->fmaps;
+ size_t num = sfp->info->num_maps;
+
+ for (int i = 0; i < num; i++) {
+ if (!strcmp(function, fmaps[i].func)) {
+ if (!fmaps[i].max_pin)
+ return fmaps[i].val;
+
+ if (pin < fmaps[i].max_pin)
+ return fmaps[i].val;
+
+ continue;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static const struct config_reg_layout_desc *get_crl_desc_by_pin(struct jhb100_pinctrl *sfp,
+ unsigned int pin)
+{
+ const struct config_reg_layout_desc *crl_desc = sfp->info->crl_desc;
+ unsigned int i = 0;
+
+ do {
+ if (pin >= crl_desc[i].pin_start &&
+ pin < crl_desc[i].pin_start + crl_desc[i].pin_cnt)
+ return &crl_desc[i];
+ } while (crl_desc[i++].pin_start != 0xff);
+
+ return NULL;
+}
+
+static const struct pinctrl_ops jhb100_pinctrl_ops = {
+ .get_groups_count = pinctrl_generic_get_group_count,
+ .get_group_name = pinctrl_generic_get_group_name,
+ .get_group_pins = pinctrl_generic_get_group_pins,
+ .dt_node_to_map = pinctrl_generic_pins_function_dt_node_to_map,
+ .dt_free_map = pinctrl_utils_free_map,
+};
+
+static void jhb100_set_function(struct jhb100_pinctrl *sfp,
+ unsigned int pin, u8 func)
+{
+ const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
+ unsigned int pins_per_reg, offset, shift;
+ void __iomem *func_sel_reg;
+ u32 func_sel_mask;
+ u32 func_sel_val;
+
+ if (!pinctrl_regs->func_sel.reg || !pinctrl_regs->func_sel.width_per_pin)
+ return;
+
+ pins_per_reg = 32 / pinctrl_regs->func_sel.width_per_pin;
+ offset = 4 * (pin / pins_per_reg);
+ shift = pinctrl_regs->func_sel.width_per_pin * (pin % pins_per_reg);
+
+ func_sel_reg = sfp->base + pinctrl_regs->func_sel.reg + offset;
+ func_sel_mask = GENMASK(pinctrl_regs->func_sel.width_per_pin - 1, 0) << shift;
+ func_sel_val = func << shift;
+
+ guard(raw_spinlock_irqsave)(&sfp->lock);
+
+ func_sel_val |= readl_relaxed(func_sel_reg) & ~func_sel_mask;
+ writel_relaxed(func_sel_val, func_sel_reg);
+}
+
+static int jhb100_set_one_pin_mux(struct jhb100_pinctrl *sfp,
+ unsigned int pin,
+ u8 func)
+{
+ jhb100_set_function(sfp, pin, func);
+
+ return 0;
+}
+
+static int jhb100_set_mux(struct pinctrl_dev *pctldev,
+ unsigned int fsel, unsigned int gsel)
+{
+ struct jhb100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
+ const struct group_desc *group;
+ unsigned int i;
+ const char **functions;
+
+ group = pinctrl_generic_get_group(pctldev, gsel);
+ if (!group)
+ return -EINVAL;
+
+ functions = group->data;
+
+ for (i = 0; i < group->grp.npins; i++) {
+ int function;
+
+ function = jhb100_map_get_func_val(sfp, functions[i], group->grp.pins[i]);
+ if (function < 0) {
+ dev_err(pctldev->dev, "invalid function %s\n", functions[i]);
+ return function;
+ }
+
+ jhb100_set_one_pin_mux(sfp, group->grp.pins[i], function);
+ }
+
+ return 0;
+}
+
+static int jhb100_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int pin)
+{
+ struct jhb100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
+ const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
+ const struct jhb100_pinctrl_domain_info *info = sfp->info;
+ unsigned int pins_per_reg, offset, shift;
+ u32 func_sel_mask, fs;
+ void __iomem *reg_gpio_func_sel;
+ s8 gpio_func_sel = sfp->gpio_func_sel_arr[pin];
+
+ if (!pinctrl_regs->func_sel.reg || !pinctrl_regs->func_sel.width_per_pin)
+ return -EINVAL;
+
+ pins_per_reg = 32 / pinctrl_regs->func_sel.width_per_pin;
+ offset = 4 * (pin / pins_per_reg);
+ shift = pinctrl_regs->func_sel.width_per_pin * (pin % pins_per_reg);
+
+ reg_gpio_func_sel = sfp->base + info->regs->func_sel.reg + offset;
+ func_sel_mask = GENMASK(info->regs->func_sel.width_per_pin - 1, 0) << shift;
+
+ if (gpio_func_sel < 0)
+ return -EINVAL;
+
+ guard(raw_spinlock_irqsave)(&sfp->lock);
+
+ fs = readl_relaxed(reg_gpio_func_sel);
+ fs &= ~func_sel_mask;
+ fs |= (gpio_func_sel << shift);
+ writel_relaxed(fs, reg_gpio_func_sel);
+
+ return 0;
+}
+
+static void jhb100_padcfg_rmw(struct jhb100_pinctrl *sfp,
+ unsigned int pin, u32 mask, u32 value)
+{
+ void __iomem *reg;
+ unsigned int offset;
+ int padcfg_base;
+
+ padcfg_base = sfp->info->regs->config;
+
+ offset = 4 * pin;
+
+ reg = sfp->base + padcfg_base + offset;
+
+ value &= mask;
+
+ guard(raw_spinlock_irqsave)(&sfp->lock);
+
+ value |= readl_relaxed(reg) & ~mask;
+ writel_relaxed(value, reg);
+}
+
+static int jhb100_gpio_direction_input(struct gpio_chip *gc,
+ unsigned int gpio)
+{
+ struct jhb100_pinctrl *sfp = gpiochip_get_data(gc);
+ const struct jhb100_pinctrl_domain_info *info = sfp->info;
+ const struct config_reg_layout_desc *crl_desc;
+ unsigned int offset = JHB100_GPIO_REG_OFFSET(gpio);
+ void __iomem *reg_gpio_oen;
+ u32 doen = 0;
+
+ crl_desc = get_crl_desc_by_pin(sfp, gpio);
+ if (!crl_desc) {
+ dev_err(sfp->dev, "pin %d can't not found reg layout descriptor\n",
+ gpio);
+ return -EINVAL;
+ }
+
+ jhb100_padcfg_rmw(sfp, gpio,
+ RL_DESC_GENMASK(crl_desc, PAD_CFG_INPUT_ENABLE) |
+ RL_DESC_GENMASK(crl_desc, PAD_CFG_SCHMITT_TRIGGER_SELECT),
+ RL_DESC_GENMASK(crl_desc, PAD_CFG_INPUT_ENABLE) |
+ RL_DESC_GENMASK(crl_desc, PAD_CFG_SCHMITT_TRIGGER_SELECT));
+
+ reg_gpio_oen = sfp->base + info->regs->output_en + offset;
+
+ guard(raw_spinlock_irqsave)(&sfp->lock);
+ doen = readl_relaxed(reg_gpio_oen) | JHB100_GPIO_MASK(gpio);
+ writel_relaxed(doen, reg_gpio_oen);
+
+ return 0;
+}
+
+static int jhb100_gpio_direction_output(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct jhb100_pinctrl *sfp = gpiochip_get_data(gc);
+ const struct jhb100_pinctrl_domain_info *info = sfp->info;
+ const struct config_reg_layout_desc *crl_desc;
+ unsigned int offset = JHB100_GPIO_REG_OFFSET(gpio);
+ void __iomem *reg_gpio_oen;
+ u32 doen = 0;
+
+ crl_desc = get_crl_desc_by_pin(sfp, gpio);
+ if (!crl_desc) {
+ dev_err(sfp->dev, "pin %d can't not found reg layout descriptor\n",
+ gpio);
+ return -EINVAL;
+ }
+
+ jhb100_padcfg_rmw(sfp, gpio,
+ RL_DESC_GENMASK(crl_desc, PAD_CFG_INPUT_ENABLE) |
+ RL_DESC_GENMASK(crl_desc, PAD_CFG_SCHMITT_TRIGGER_SELECT) |
+ RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN) |
+ RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP),
+ 0);
+
+ reg_gpio_oen = sfp->base + info->regs->output_en + offset;
+
+ guard(raw_spinlock_irqsave)(&sfp->lock);
+ doen = readl_relaxed(reg_gpio_oen) & ~JHB100_GPIO_MASK(gpio);
+ writel_relaxed(doen, reg_gpio_oen);
+
+ return 0;
+}
+
+static int jhb100_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int pin,
+ bool input)
+{
+ struct jhb100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
+
+ if (input)
+ return jhb100_gpio_direction_input(&sfp->gc, pin);
+
+ return jhb100_gpio_direction_output(&sfp->gc, pin);
+}
+
+static const struct pinmux_ops jhb100_pinmux_ops = {
+ .get_functions_count = pinmux_generic_get_function_count,
+ .get_function_name = pinmux_generic_get_function_name,
+ .get_function_groups = pinmux_generic_get_function_groups,
+ .set_mux = jhb100_set_mux,
+ .gpio_request_enable = jhb100_gpio_request_enable,
+ .gpio_set_direction = jhb100_gpio_set_direction,
+};
+
+static const u8 jhb100_drive_strength_ma[4] = { 2, 4, 8, 12 };
+
+static const u8 jhb100_drive_strength_ma_3bit[8] = { 2, 5, 8, 10, 14, 16, 18, 20 };
+
+static u32 jhb100_padcfg_ds_to_mA(u32 padcfg)
+{
+ return jhb100_drive_strength_ma[padcfg];
+}
+
+static u32 jhb100_padcfg_ds_to_mA_3bit(u32 padcfg)
+{
+ return jhb100_drive_strength_ma_3bit[padcfg];
+}
+
+static u32 jhb100_padcfg_ds_to_uA(u32 padcfg)
+{
+ return (jhb100_drive_strength_ma[padcfg] * 1000);
+}
+
+static u32 jhb100_padcfg_ds_to_uA_3bit(u32 padcfg)
+{
+ return (jhb100_drive_strength_ma_3bit[padcfg] * 1000);
+}
+
+static u32 jhb100_padcfg_ds_from_mA(u32 v)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(jhb100_drive_strength_ma); i++) {
+ if (v <= jhb100_drive_strength_ma[i])
+ break;
+ }
+ return i;
+}
+
+static u32 jhb100_padcfg_ds_from_mA_3bit(u32 v)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(jhb100_drive_strength_ma_3bit); i++) {
+ if (v <= jhb100_drive_strength_ma_3bit[i])
+ break;
+ }
+ return i;
+}
+
+static u32 jhb100_padcfg_ds_from_uA(u32 v)
+{
+ /* Convert from uA to mA */
+ v /= 1000;
+
+ return jhb100_padcfg_ds_from_mA(v);
+}
+
+static u32 jhb100_padcfg_ds_from_uA_3bit(u32 v)
+{
+ /* Convert from uA to mA */
+ v /= 1000;
+
+ return jhb100_padcfg_ds_from_mA_3bit(v);
+}
+
+static u32 jhb100_padcfg_vsel_to_reg(u32 val)
+{
+ switch (val) {
+ case 3300:
+ case 1800:
+ return 0;
+ case 2500:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+static int jhb100_pincfg_reg_to_vref(u32 val)
+{
+ const int vref_table[JHB100_PINVREF_NUM] = { 3300, 2500, 1800 };
+
+ return (val < JHB100_PINVREF_NUM) ? vref_table[val] : -ENOTSUPP;
+}
+
+static u32 jhb100_pincfg_vref_to_reg(u32 val)
+{
+ switch (val) {
+ case 3300:
+ return JHB100_PINVREF_3_3V;
+ case 2500:
+ return JHB100_PINVREF_2_5V;
+ case 1800:
+ return JHB100_PINVREF_1_8V;
+ default:
+ return JHB100_PINVREF_3_3V;
+ }
+}
+
+static int jhb100_pincfg_pin_vref_get(struct jhb100_pinctrl *sfp, unsigned int pin)
+{
+ const struct pinvref_reg *vref = &sfp->info->regs->vref;
+ u32 grp = 0, i;
+ int val;
+
+ while (grp < vref->num_pv) {
+ for (i = 0; i < vref->pv_desc[grp].num_pins; i++) {
+ if (pin != vref->pv_desc[grp].pin_grp[i])
+ continue;
+
+ val = readl(sfp->base + vref->reg + grp * 4);
+
+ return jhb100_pincfg_reg_to_vref(val);
+ }
+
+ grp++;
+ }
+
+ return -ENOTSUPP;
+}
+
+static void jhb100_pincfg_pin_vref_set(struct jhb100_pinctrl *sfp, unsigned int pin,
+ u32 arg)
+{
+ const struct pinvref_reg *vref = &sfp->info->regs->vref;
+ u32 grp = 0, i;
+
+ while (grp < vref->num_pv) {
+ for (i = 0; i < vref->pv_desc[grp].num_pins; i++) {
+ if (pin != vref->pv_desc[grp].pin_grp[i])
+ continue;
+
+ arg = jhb100_pincfg_vref_to_reg(arg);
+
+ if (!(vref->pv_desc[grp].range & BIT(arg)))
+ return;
+
+ guard(raw_spinlock_irqsave)(&sfp->lock);
+ writel(arg, sfp->base + vref->reg + grp * 4);
+ return;
+ }
+
+ grp++;
+ }
+}
+
+static int jhb100_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *config)
+{
+ struct jhb100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
+ int param = pinconf_to_config_param(*config);
+ const struct config_reg_layout_desc *crl_desc;
+ unsigned int padcfg_base, offset;
+ bool enabled = false;
+ u32 padcfg, arg;
+ int ret;
+
+ padcfg_base = sfp->info->regs->config;
+ offset = 4 * pin;
+
+ if (pin >= sfp->npins)
+ return -EINVAL;
+
+ padcfg = readl_relaxed(sfp->base + padcfg_base + offset);
+
+ crl_desc = get_crl_desc_by_pin(sfp, pin);
+ if (!crl_desc) {
+ dev_err(sfp->dev, "pin %d can't not found reg layout descriptor\n", pin);
+ return -EINVAL;
+ }
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ arg = 0;
+
+ if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_DOWN) ||
+ !RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_UP))
+ return -ENOTSUPP;
+
+ enabled = !(padcfg & (RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN) |
+ RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP)));
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ arg = 1;
+
+ if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_DOWN))
+ return -ENOTSUPP;
+
+ enabled = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN))
+ >> RL_DESC_SHIFT(crl_desc, PAD_CFG_PULL_DOWN);
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_UP) &&
+ !RL_DESC_SUPPORTED(crl_desc, PAD_CFG_OPEN_DRAIN_PULL_UP_SEL))
+ return -ENOTSUPP;
+
+ if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_UP)) {
+ arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP)) >>
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_PULL_UP);
+
+ enabled = arg ? true : false;
+ }
+
+ if (!enabled && RL_DESC_SUPPORTED(crl_desc, PAD_CFG_OPEN_DRAIN_PULL_UP_SEL)) {
+ enabled = true;
+
+ arg = (padcfg &
+ RL_DESC_GENMASK(crl_desc, PAD_CFG_OPEN_DRAIN_PULL_UP_SEL)) >>
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_OPEN_DRAIN_PULL_UP_SEL);
+
+ if (arg == JHB100_I2C_OPEN_DRAIN_PU_600_OHMS)
+ arg = 600;
+ else if (arg == JHB100_I2C_OPEN_DRAIN_PU_900_OHMS)
+ arg = 900;
+ else if (arg == JHB100_I2C_OPEN_DRAIN_PU_1200_OHMS)
+ arg = 1200;
+ else if (arg == JHB100_I2C_OPEN_DRAIN_PU_2000_OHMS)
+ arg = 2000;
+ else
+ return -ENOTSUPP;
+ }
+
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT)) {
+ enabled = true;
+
+ arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT)) >>
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT);
+ arg = jhb100_padcfg_ds_to_mA(arg);
+ } else if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT)) {
+ enabled = true;
+
+ arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT)) >>
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT);
+ arg = jhb100_padcfg_ds_to_mA_3bit(arg);
+ } else {
+ return -ENOTSUPP;
+ }
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH_UA:
+ if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT)) {
+ enabled = true;
+
+ arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT)) >>
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT);
+ arg = jhb100_padcfg_ds_to_uA(arg);
+ } else if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT)) {
+ enabled = true;
+
+ arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT)) >>
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT);
+ arg = jhb100_padcfg_ds_to_uA_3bit(arg);
+ } else {
+ return -ENOTSUPP;
+ }
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_INPUT_ENABLE))
+ return -ENOTSUPP;
+
+ enabled = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_INPUT_ENABLE))
+ >> RL_DESC_SHIFT(crl_desc, PAD_CFG_INPUT_ENABLE);
+ arg = enabled;
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_SCHMITT_TRIGGER_SELECT))
+ return -ENOTSUPP;
+
+ enabled = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_SCHMITT_TRIGGER_SELECT))
+ >> RL_DESC_SHIFT(crl_desc, PAD_CFG_SCHMITT_TRIGGER_SELECT);
+ arg = enabled;
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_SLEW_RATE)) {
+ enabled = true;
+
+ arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_SLEW_RATE)) >>
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_SLEW_RATE);
+ } else if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_MODE_SELECT)) {
+ enabled = true;
+
+ arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_MODE_SELECT)) >>
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_MODE_SELECT);
+
+ if (arg == JHB100_LEGACY_FAST_MODE_PLUS)
+ arg = 1;
+ else if (arg == JHB100_LEGACY_FAST_MODE)
+ arg = 0;
+ else
+ return -ENOTSUPP;
+ } else {
+ return -ENOTSUPP;
+ }
+ break;
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_MODE_SELECT))
+ return -ENOTSUPP;
+
+ arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_MODE_SELECT)) >>
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_MODE_SELECT);
+
+ if (arg == JHB100_PUSH_PULL)
+ enabled = true;
+
+ break;
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_MODE_SELECT))
+ return -ENOTSUPP;
+
+ arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_MODE_SELECT)) >>
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_MODE_SELECT);
+
+ if (arg == JHB100_OPEN_DRAIN)
+ enabled = true;
+
+ break;
+ case PIN_CONFIG_INPUT_DEBOUNCE_NS:
+ if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DEBOUNCE_WIDTH))
+ return -ENOTSUPP;
+
+ enabled = true;
+
+ arg = (padcfg & RL_DESC_GENMASK(crl_desc, PAD_CFG_DEBOUNCE_WIDTH)) >>
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_DEBOUNCE_WIDTH);
+
+ arg *= JHB100_DEBOUNCE_WIDTH_STAGE_NS;
+
+ break;
+ case PIN_CONFIG_POWER_SOURCE:
+ if (!sfp->info->regs->vref.num_pv)
+ return -ENOTSUPP;
+
+ ret = jhb100_pincfg_pin_vref_get(sfp, pin);
+ if (ret < 0)
+ return ret;
+
+ arg = ret;
+ enabled = true;
+
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, arg);
+ return enabled ? 0 : -EINVAL;
+}
+
+static int jhb100_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *configs,
+ unsigned int num_configs)
+{
+ struct jhb100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
+ const struct config_reg_layout_desc *crl_desc;
+ bool vref_set = false;
+ u32 value = 0;
+ u32 mask = 0;
+ u32 vref = 0;
+ int i;
+
+ crl_desc = get_crl_desc_by_pin(sfp, pin);
+ if (!crl_desc) {
+ dev_err(sfp->dev, "pin %d can't not found reg layout descriptor\n", pin);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < num_configs; i++) {
+ int param = pinconf_to_config_param(configs[i]);
+ u32 arg = pinconf_to_config_argument(configs[i]);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_DOWN) ||
+ !RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_UP))
+ return -ENOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN) |
+ RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP);
+ value &= ~(RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN) |
+ RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP));
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (!arg || !RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_DOWN) ||
+ !RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_UP))
+ return -ENOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN) |
+ RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP);
+ value &= ~(RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN) |
+ RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP));
+ value |= RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN);
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if ((!arg || arg == 1) && RL_DESC_SUPPORTED(crl_desc, PAD_CFG_PULL_UP)) {
+ mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN) |
+ RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP);
+ value &= ~(RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_DOWN) |
+ RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP));
+ value |= RL_DESC_GENMASK(crl_desc, PAD_CFG_PULL_UP);
+ } else if (arg &&
+ RL_DESC_SUPPORTED(crl_desc, PAD_CFG_OPEN_DRAIN_PULL_UP_SEL)) {
+ mask |= RL_DESC_GENMASK(crl_desc,
+ PAD_CFG_OPEN_DRAIN_PULL_UP_SEL);
+ value &= ~RL_DESC_GENMASK(crl_desc,
+ PAD_CFG_OPEN_DRAIN_PULL_UP_SEL);
+ switch (arg) {
+ case 600:
+ value |= JHB100_I2C_OPEN_DRAIN_PU_600_OHMS <<
+ RL_DESC_SHIFT(crl_desc,
+ PAD_CFG_OPEN_DRAIN_PULL_UP_SEL);
+ break;
+ case 900:
+ value |= JHB100_I2C_OPEN_DRAIN_PU_900_OHMS <<
+ RL_DESC_SHIFT(crl_desc,
+ PAD_CFG_OPEN_DRAIN_PULL_UP_SEL);
+ break;
+ case 1200:
+ value |= JHB100_I2C_OPEN_DRAIN_PU_1200_OHMS <<
+ RL_DESC_SHIFT(crl_desc,
+ PAD_CFG_OPEN_DRAIN_PULL_UP_SEL);
+ break;
+ case 2000:
+ value |= JHB100_I2C_OPEN_DRAIN_PU_2000_OHMS <<
+ RL_DESC_SHIFT(crl_desc,
+ PAD_CFG_OPEN_DRAIN_PULL_UP_SEL);
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+ } else {
+ return -ENOTSUPP;
+ }
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT)) {
+ mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT);
+ value &= ~RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT);
+ value |= jhb100_padcfg_ds_from_mA(arg) <<
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT);
+ } else if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT)) {
+ mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT);
+ value &= ~RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT);
+ value |= jhb100_padcfg_ds_from_mA_3bit(arg) <<
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT);
+ } else {
+ return -ENOTSUPP;
+ }
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH_UA:
+ if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT)) {
+ mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT);
+ value &= ~RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT);
+ value |= jhb100_padcfg_ds_from_uA(arg) <<
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_DRIVE_STRENGTH_2BIT);
+ } else if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT)) {
+ mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT);
+ value &= ~RL_DESC_GENMASK(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT);
+ value |= jhb100_padcfg_ds_from_uA_3bit(arg) <<
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_DRIVE_STRENGTH_3BIT);
+ } else {
+ return -ENOTSUPP;
+ }
+ break;
+ case PIN_CONFIG_INPUT_ENABLE:
+ if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_INPUT_ENABLE))
+ return -ENOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_INPUT_ENABLE);
+ value = arg ? (value | RL_DESC_GENMASK(crl_desc, PAD_CFG_INPUT_ENABLE))
+ : value;
+ break;
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_SCHMITT_TRIGGER_SELECT))
+ return -ENOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_SCHMITT_TRIGGER_SELECT);
+ value = arg ?
+ (value | RL_DESC_GENMASK(crl_desc, PAD_CFG_SCHMITT_TRIGGER_SELECT))
+ : value;
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_SLEW_RATE)) {
+ mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_SLEW_RATE);
+ value = arg ?
+ (value | RL_DESC_GENMASK(crl_desc, PAD_CFG_SLEW_RATE)) :
+ value;
+ } else if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_MODE_SELECT)) {
+ mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_MODE_SELECT);
+ value &= ~RL_DESC_GENMASK(crl_desc, PAD_CFG_MODE_SELECT);
+ value |= arg ?
+ JHB100_LEGACY_FAST_MODE_PLUS <<
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_MODE_SELECT) :
+ JHB100_LEGACY_FAST_MODE <<
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_MODE_SELECT);
+ } else {
+ return -ENOTSUPP;
+ }
+ break;
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_MODE_SELECT))
+ return -ENOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_MODE_SELECT);
+ value &= ~RL_DESC_GENMASK(crl_desc, PAD_CFG_MODE_SELECT);
+ value |= JHB100_PUSH_PULL <<
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_MODE_SELECT);
+ break;
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_MODE_SELECT))
+ return -ENOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_MODE_SELECT);
+ value &= ~RL_DESC_GENMASK(crl_desc, PAD_CFG_MODE_SELECT);
+ value |= JHB100_OPEN_DRAIN <<
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_MODE_SELECT);
+ break;
+ case PIN_CONFIG_INPUT_DEBOUNCE_NS: {
+ u32 debounce_stage;
+
+ if (!RL_DESC_SUPPORTED(crl_desc, PAD_CFG_DEBOUNCE_WIDTH))
+ return -ENOTSUPP;
+
+ mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_DEBOUNCE_WIDTH);
+ value &= ~RL_DESC_GENMASK(crl_desc, PAD_CFG_DEBOUNCE_WIDTH);
+
+ debounce_stage = arg ? arg / JHB100_DEBOUNCE_WIDTH_STAGE_NS : 0;
+ debounce_stage = umin(debounce_stage, JHB100_DEBOUNCE_WIDTH_STAGES_MAX);
+
+ value |= (debounce_stage <<
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_DEBOUNCE_WIDTH));
+
+ break;
+ };
+ case PIN_CONFIG_POWER_SOURCE:
+ if (!sfp->info->regs->vref.num_pv &&
+ !RL_DESC_SUPPORTED(crl_desc, PAD_CFG_VSEL))
+ return -ENOTSUPP;
+
+ if (sfp->info->regs->vref.num_pv) {
+ vref_set = true;
+ vref = arg;
+ }
+
+ if (RL_DESC_SUPPORTED(crl_desc, PAD_CFG_VSEL)) {
+ mask |= RL_DESC_GENMASK(crl_desc, PAD_CFG_VSEL);
+ value &= ~RL_DESC_GENMASK(crl_desc, PAD_CFG_VSEL);
+
+ value |= jhb100_padcfg_vsel_to_reg(arg) <<
+ RL_DESC_SHIFT(crl_desc, PAD_CFG_VSEL);
+ }
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+ }
+
+ jhb100_padcfg_rmw(sfp, pin, mask, value);
+
+ if (vref_set)
+ jhb100_pincfg_pin_vref_set(sfp, pin, vref);
+
+ return 0;
+}
+
+static int jhb100_pinconf_group_get(struct pinctrl_dev *pctldev,
+ unsigned int gsel,
+ unsigned long *config)
+{
+ const struct group_desc *group;
+
+ group = pinctrl_generic_get_group(pctldev, gsel);
+ if (!group)
+ return -EINVAL;
+
+ return jhb100_pinconf_get(pctldev, group->grp.pins[0], config);
+}
+
+static int jhb100_pinconf_group_set(struct pinctrl_dev *pctldev,
+ unsigned int gsel,
+ unsigned long *configs,
+ unsigned int num_configs)
+{
+ const struct group_desc *group;
+ int ret;
+ u32 i;
+
+ group = pinctrl_generic_get_group(pctldev, gsel);
+ if (!group)
+ return -EINVAL;
+
+ for (i = 0; i < group->grp.npins; i++) {
+ ret = jhb100_pinconf_set(pctldev, group->grp.pins[i], configs, num_configs);
+ if (ret) {
+ dev_err(pctldev->dev, "failed to set config for pin %d\n",
+ group->grp.pins[i]);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops jhb100_pinconf_ops = {
+ .pin_config_get = jhb100_pinconf_get,
+ .pin_config_set = jhb100_pinconf_set,
+ .pin_config_group_get = jhb100_pinconf_group_get,
+ .pin_config_group_set = jhb100_pinconf_group_set,
+ .is_generic = true,
+};
+
+static int jhb100_gpio_get_direction(struct gpio_chip *gc,
+ unsigned int gpio)
+{
+ struct jhb100_pinctrl *sfp = gpiochip_get_data(gc);
+ const struct jhb100_pinctrl_domain_info *info = sfp->info;
+ unsigned int offset = JHB100_GPIO_REG_OFFSET(gpio);
+ u32 doen;
+ void __iomem *reg_gpio_oen;
+
+ reg_gpio_oen = sfp->base + info->regs->output_en + offset;
+
+ doen = !!(readl_relaxed(reg_gpio_oen) & JHB100_GPIO_MASK(gpio));
+
+ return doen == GPOEN_ENABLE ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
+}
+
+static int jhb100_gpio_get(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct jhb100_pinctrl *sfp = gpiochip_get_data(gc);
+ const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
+ void __iomem *reg_gpio_status;
+
+ reg_gpio_status = sfp->base + pinctrl_regs->gpio_status +
+ JHB100_GPIO_REG_OFFSET(gpio);
+
+ return !!(readl_relaxed(reg_gpio_status) & JHB100_GPIO_MASK(gpio));
+}
+
+static int jhb100_gpio_set(struct gpio_chip *gc, unsigned int gpio, int value)
+{
+ struct jhb100_pinctrl *sfp = gpiochip_get_data(gc);
+ const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
+ void __iomem *reg_gpio_out;
+ u32 dout;
+
+ reg_gpio_out = sfp->base + pinctrl_regs->output + JHB100_GPIO_REG_OFFSET(gpio);
+
+ guard(raw_spinlock_irqsave)(&sfp->lock);
+
+ dout = readl_relaxed(reg_gpio_out);
+
+ if (value)
+ dout |= JHB100_GPIO_MASK(gpio);
+ else
+ dout &= ~JHB100_GPIO_MASK(gpio);
+
+ writel_relaxed(dout, reg_gpio_out);
+
+ return 0;
+}
+
+static int jhb100_pinctrl_gpio_direction_output(struct gpio_chip *gc,
+ unsigned int gpio, int value)
+{
+ int ret;
+
+ ret = jhb100_gpio_set(gc, gpio, value);
+ if (ret)
+ return ret;
+
+ return pinctrl_gpio_direction_output(gc, gpio);
+}
+
+static void jhb100_irq_ack(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct jhb100_pinctrl *sfp = gpiochip_get_data(gc);
+ const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ unsigned int offset = JHB100_GPIO_REG_OFFSET(gpio);
+ void __iomem *ic;
+ u32 value;
+ u32 mask;
+
+ ic = sfp->base + pinctrl_regs->irq_clr + offset;
+ mask = JHB100_GPIO_MASK(gpio);
+
+ guard(raw_spinlock_irqsave)(&sfp->lock);
+
+ value = readl_relaxed(ic) & ~mask;
+ writel_relaxed(value | mask, ic);
+ value = readl_relaxed(ic) & ~mask;
+ writel_relaxed(value, ic);
+}
+
+static void jhb100_irq_mask(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct jhb100_pinctrl *sfp = gpiochip_get_data(gc);
+ const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ unsigned int offset = JHB100_GPIO_REG_OFFSET(gpio);
+ void __iomem *ien;
+ u32 value;
+ u32 mask;
+
+ ien = sfp->base + pinctrl_regs->irq_en + offset;
+ mask = JHB100_GPIO_MASK(gpio);
+
+ guard(raw_spinlock_irqsave)(&sfp->lock);
+
+ value = readl_relaxed(ien) & ~mask;
+ writel_relaxed(value, ien);
+
+ gpiochip_disable_irq(gc, d->hwirq);
+}
+
+static void jhb100_irq_mask_ack(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct jhb100_pinctrl *sfp = gpiochip_get_data(gc);
+ const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ unsigned int offset = JHB100_GPIO_REG_OFFSET(gpio);
+ void __iomem *ien;
+ void __iomem *ic;
+ u32 value;
+ u32 mask;
+
+ ien = sfp->base + pinctrl_regs->irq_en + offset;
+ ic = sfp->base + pinctrl_regs->irq_clr + offset;
+ mask = JHB100_GPIO_MASK(gpio);
+
+ guard(raw_spinlock_irqsave)(&sfp->lock);
+
+ value = readl_relaxed(ien) & ~mask;
+ writel_relaxed(value, ien);
+
+ value = readl_relaxed(ic) & ~mask;
+ writel_relaxed(value | mask, ic);
+ value = readl_relaxed(ic) & ~mask;
+ writel_relaxed(value, ic);
+}
+
+static void jhb100_irq_unmask(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct jhb100_pinctrl *sfp = gpiochip_get_data(gc);
+ const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ unsigned int offset = JHB100_GPIO_REG_OFFSET(gpio);
+ void __iomem *ien;
+ u32 value;
+ u32 mask;
+
+ ien = sfp->base + pinctrl_regs->irq_en + offset;
+ mask = JHB100_GPIO_MASK(gpio);
+
+ gpiochip_enable_irq(gc, d->hwirq);
+
+ guard(raw_spinlock_irqsave)(&sfp->lock);
+
+ value = readl_relaxed(ien) | mask;
+ writel_relaxed(value, ien);
+}
+
+static int jhb100_irq_set_type(struct irq_data *d, unsigned int trigger)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct jhb100_pinctrl *sfp = gpiochip_get_data(gc);
+ const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
+ irq_hw_number_t gpio = irqd_to_hwirq(d);
+ unsigned int offset = JHB100_GPIO_REG_OFFSET(gpio);
+ void __iomem *base;
+ u32 irq_type, edge_both, polarity, mask;
+
+ base = sfp->base + offset;
+ mask = JHB100_GPIO_MASK(gpio);
+
+ switch (trigger) {
+ case IRQ_TYPE_EDGE_RISING:
+ irq_type = mask; /* 1: edge triggered */
+ edge_both = 0; /* 0: single edge */
+ polarity = mask; /* 1: rising edge */
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ irq_type = mask; /* 1: edge triggered */
+ edge_both = 0; /* 0: single edge */
+ polarity = 0; /* 0: falling edge */
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ irq_type = mask; /* 1: edge triggered */
+ edge_both = mask; /* 1: both edges */
+ polarity = 0; /* 0: ignored */
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ irq_type = 0; /* 0: level triggered */
+ edge_both = 0; /* 0: ignored */
+ polarity = mask; /* 1: high level */
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ irq_type = 0; /* 0: level triggered */
+ edge_both = 0; /* 0: ignored */
+ polarity = 0; /* 0: low level */
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (trigger & IRQ_TYPE_EDGE_BOTH)
+ irq_set_handler_locked(d, handle_edge_irq);
+ else
+ irq_set_handler_locked(d, handle_level_irq);
+
+ guard(raw_spinlock_irqsave)(&sfp->lock);
+
+ irq_type |= readl_relaxed(base + pinctrl_regs->irq_trigger) & ~mask;
+ writel_relaxed(irq_type, base + pinctrl_regs->irq_trigger);
+
+ edge_both |= readl_relaxed(base + pinctrl_regs->irq_both_edge) & ~mask;
+ writel_relaxed(edge_both, base + pinctrl_regs->irq_both_edge);
+
+ if (irq_type & mask) { /* edge polarity */
+ polarity |= readl_relaxed(base + pinctrl_regs->irq_edge) & ~mask;
+ writel_relaxed(polarity, base + pinctrl_regs->irq_edge);
+ } else { /* level polarity */
+ polarity |= readl_relaxed(base + pinctrl_regs->irq_level) & ~mask;
+ writel_relaxed(polarity, base + pinctrl_regs->irq_level);
+ }
+
+ return 0;
+}
+
+static int jhb100_irq_set_wake(struct irq_data *d, unsigned int enable)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct jhb100_pinctrl *sfp = gpiochip_get_data(gc);
+ int ret;
+
+ if (enable)
+ ret = enable_irq_wake(sfp->irq);
+ else
+ ret = disable_irq_wake(sfp->irq);
+ if (ret)
+ dev_err(sfp->dev, "failed to %s wake-up interrupt\n",
+ enable ? "enable" : "disable");
+
+ return ret;
+}
+
+static void jhb100_irq_print_chip(struct irq_data *d, struct seq_file *p)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+
+ seq_puts(p, gc->label);
+}
+
+static const struct irq_chip jhb100_irq_chip = {
+ .irq_ack = jhb100_irq_ack,
+ .irq_mask = jhb100_irq_mask,
+ .irq_mask_ack = jhb100_irq_mask_ack,
+ .irq_unmask = jhb100_irq_unmask,
+ .irq_set_type = jhb100_irq_set_type,
+ .irq_set_wake = jhb100_irq_set_wake,
+ .irq_print_chip = jhb100_irq_print_chip,
+ .flags = IRQCHIP_SET_TYPE_MASKED |
+ IRQCHIP_IMMUTABLE |
+ IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND |
+ IRQCHIP_MASK_ON_SUSPEND,
+ GPIOCHIP_IRQ_RESOURCE_HELPERS,
+};
+
+static irqreturn_t jhb100_gpio_irq_handler(int irq, void *dev_id)
+{
+ struct jhb100_pinctrl *sfp = dev_id;
+ struct gpio_chip *gc = &sfp->gc;
+ struct gpio_irq_chip *girq = &gc->irq;
+ const struct starfive_pinctrl_regs *pinctrl_regs = sfp->info->regs;
+ irqreturn_t ret = IRQ_NONE;
+ unsigned int bit;
+ unsigned long is;
+
+ for (unsigned int i = 0; i < sfp->num_banks; i++) {
+ is = readl_relaxed(sfp->base + pinctrl_regs->irq_status +
+ JHB100_BANK_OFFSET(i));
+ if (!is)
+ continue;
+
+ for_each_set_bit(bit, &is, JHB100_NR_GPIOS_PER_BANK) {
+ unsigned int gpio = i * JHB100_NR_GPIOS_PER_BANK + bit;
+
+ if (gpio >= gc->ngpio)
+ break;
+
+ generic_handle_domain_irq(girq->domain, gpio);
+ }
+
+ ret = IRQ_HANDLED;
+ }
+
+ return ret;
+}
+
+static
+struct pinctrl_pin_desc *devm_create_pins_from_pld(struct device *dev,
+ const struct jhb100_pin_layout_desc *desc,
+ const char *prefix,
+ unsigned int *total_pins,
+ unsigned int *total_gpios,
+ s8 **gpio_func_sel_arr)
+{
+ struct pinctrl_pin_desc *pins = NULL;
+ unsigned int i, j, ngpios = 0, npins = 0, pin_index = 0;
+ unsigned int same_name_found = 0;
+ s8 *arr;
+
+ if (!dev || !desc || !prefix) {
+ dev_err(dev, "Invalid parameters: desc=%p, prefix=%s\n",
+ desc, prefix);
+ return ERR_PTR(-EINVAL);
+ }
+
+ for (i = 0; desc[i].pin_start != 0xff; i++) {
+ if (!desc[i].pin_cnt) {
+ dev_err(dev, "Invalid pin cnt\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ npins += desc[i].pin_cnt;
+ }
+
+ if (npins == 0) {
+ dev_err(dev, "No pins defined\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ dev_dbg(dev, "Total pins to create: %d\n", npins);
+
+ pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
+ if (!pins)
+ return ERR_PTR(-ENOMEM);
+
+ arr = devm_kzalloc(dev, npins, GFP_KERNEL);
+ if (!arr)
+ return ERR_PTR(-ENOMEM);
+
+ for (i = 0; desc[i].pin_start != 0xff; i++) {
+ same_name_found = 0;
+
+ for (j = 0; j < i; j++) {
+ if (!strcmp(desc[j].name, desc[i].name)) {
+ same_name_found = 1;
+ break;
+ }
+ }
+
+ for (j = 0; j < desc[i].pin_cnt; j++) {
+ char *name = NULL;
+ int pin_num = desc[i].pin_start + j;
+
+ pins[pin_index].number = pin_num;
+ if (same_name_found) {
+ name = devm_kasprintf(dev, GFP_KERNEL, "%s_%s_%d",
+ prefix, desc[i].name,
+ desc[i].pin_start + j);
+ } else {
+ if (desc[i].pin_cnt > 1)
+ name = devm_kasprintf(dev, GFP_KERNEL, "%s_%s_%d",
+ prefix, desc[i].name, j);
+ else
+ name = devm_kasprintf(dev, GFP_KERNEL, "%s_%s",
+ prefix, desc[i].name);
+ }
+
+ if (!name) {
+ dev_err(dev, "Failed to allocate pin name for pin %d\n",
+ pin_num);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ if (!strcmp(desc[i].name, "gpio") || desc[i].gpio_func_sel != -1)
+ ngpios++;
+
+ pins[pin_index].name = name;
+ arr[pin_index] = desc[i].gpio_func_sel;
+ pin_index++;
+ }
+ }
+
+ *total_pins = npins;
+ *total_gpios = ngpios;
+ *gpio_func_sel_arr = arr;
+
+ return pins;
+}
+
+static void jhb100_reset_control_assert(void *data)
+{
+ reset_control_assert(data);
+}
+
+int jhb100_pinctrl_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct gpio_irq_chip *girq;
+ struct gpio_chip *gc;
+ const struct jhb100_pinctrl_domain_info *info;
+ struct jhb100_pinctrl *sfp;
+ struct pinctrl_desc *jhb100_pinctrl_desc;
+ const struct starfive_pinctrl_regs *pinctrl_regs;
+ struct reset_control *rst;
+ struct clk *clk;
+ int ret;
+
+ info = device_get_match_data(&pdev->dev);
+ if (!info)
+ return -ENODEV;
+
+ pinctrl_regs = info->regs;
+
+ sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
+ if (!sfp)
+ return -ENOMEM;
+
+ sfp->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(sfp->base))
+ return PTR_ERR(sfp->base);
+
+ clk = devm_clk_get_optional_enabled(dev, NULL);
+ if (IS_ERR(clk))
+ return dev_err_probe(dev, PTR_ERR(clk), "could not get & enable clock\n");
+
+ rst = devm_reset_control_array_get_optional_shared(dev);
+ if (IS_ERR(rst))
+ return dev_err_probe(dev, PTR_ERR(rst), "could not get reset control\n");
+
+ ret = reset_control_deassert(rst);
+ if (ret)
+ return dev_err_probe(dev, ret, "could not deassert reset\n");
+
+ ret = devm_add_action_or_reset(dev, jhb100_reset_control_assert, rst);
+ if (ret)
+ return ret;
+
+ sfp->irq = platform_get_irq(pdev, 0);
+ if (sfp->irq < 0)
+ return sfp->irq;
+
+ sfp->pins = devm_create_pins_from_pld(dev, info->pl_desc, info->name,
+ &sfp->npins, &sfp->ngpios,
+ &sfp->gpio_func_sel_arr);
+ if (IS_ERR(sfp->pins))
+ return PTR_ERR(sfp->pins);
+
+ jhb100_pinctrl_desc = devm_kzalloc(&pdev->dev,
+ sizeof(*jhb100_pinctrl_desc),
+ GFP_KERNEL);
+ if (!jhb100_pinctrl_desc)
+ return -ENOMEM;
+
+ jhb100_pinctrl_desc->name = dev_name(dev);
+ jhb100_pinctrl_desc->pctlops = &jhb100_pinctrl_ops;
+ jhb100_pinctrl_desc->pmxops = &jhb100_pinmux_ops;
+ jhb100_pinctrl_desc->confops = &jhb100_pinconf_ops;
+ jhb100_pinctrl_desc->owner = THIS_MODULE;
+ jhb100_pinctrl_desc->pins = sfp->pins;
+ jhb100_pinctrl_desc->npins = sfp->npins;
+
+ sfp->info = info;
+ sfp->dev = dev;
+ platform_set_drvdata(pdev, sfp);
+
+ raw_spin_lock_init(&sfp->lock);
+
+ ret = devm_pinctrl_register_and_init(dev, jhb100_pinctrl_desc,
+ sfp, &sfp->pctl);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "could not register pinctrl driver\n");
+
+ ret = pinctrl_enable(sfp->pctl);
+ if (ret)
+ return ret;
+
+ sfp->num_banks = DIV_ROUND_UP(sfp->ngpios, JHB100_NR_GPIOS_PER_BANK);
+ if (sfp->num_banks > JHB100_MAX_BANKS)
+ return dev_err_probe(dev, -EINVAL,
+ "%u GPIOs need %u banks, max %d\n",
+ sfp->ngpios, sfp->num_banks, JHB100_MAX_BANKS);
+
+ for (unsigned int i = 0; i < sfp->num_banks; i++) {
+ /* mask all GPIO interrupts */
+ writel_relaxed(0U, sfp->base + pinctrl_regs->irq_en + JHB100_BANK_OFFSET(i));
+ /* clear all interrupts */
+ writel_relaxed(~0U, sfp->base + pinctrl_regs->irq_clr + JHB100_BANK_OFFSET(i));
+ writel_relaxed(0U, sfp->base + pinctrl_regs->irq_clr + JHB100_BANK_OFFSET(i));
+ }
+
+ gc = &sfp->gc;
+ gc->label = dev_name(dev);
+ gc->parent = dev;
+ gc->owner = THIS_MODULE;
+ gc->request = gpiochip_generic_request;
+ gc->free = gpiochip_generic_free;
+ gc->get_direction = jhb100_gpio_get_direction;
+ gc->direction_input = pinctrl_gpio_direction_input;
+ gc->direction_output = jhb100_pinctrl_gpio_direction_output;
+ gc->get = jhb100_gpio_get;
+ gc->set = jhb100_gpio_set;
+ gc->set_config = gpiochip_generic_config;
+ gc->base = -1;
+ gc->ngpio = sfp->ngpios;
+
+ girq = &gc->irq;
+ girq->handler = handle_simple_irq;
+
+ gpio_irq_chip_set_chip(girq, &jhb100_irq_chip);
+
+ ret = devm_gpiochip_add_data(dev, gc, sfp);
+ if (ret)
+ return dev_err_probe(dev, ret, "could not register gpiochip\n");
+
+ ret = devm_request_irq(dev, sfp->irq, jhb100_gpio_irq_handler, 0,
+ gc->label, sfp);
+ if (ret < 0)
+ return ret;
+
+ dev_info(dev, "StarFive JHB100 GPIO chip registered %d GPIOs\n",
+ sfp->ngpios);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(jhb100_pinctrl_probe);
+
+MODULE_DESCRIPTION("Pinctrl driver for the StarFive JHB100 SoC");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100.h b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100.h
new file mode 100644
index 000000000000..baac5978ba7e
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100.h
@@ -0,0 +1,153 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#ifndef __PINCTRL_STARFIVE_JHB100_H__
+#define __PINCTRL_STARFIVE_JHB100_H__
+
+#include <linux/gpio/driver.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinmux.h>
+
+/* power-source value */
+enum jhb100_pinvref {
+ JHB100_PINVREF_3_3V,
+ JHB100_PINVREF_2_5V,
+ JHB100_PINVREF_1_8V,
+ JHB100_PINVREF_NUM
+};
+
+#define JHB100_MAX_BANKS 2
+
+struct jhb100_pin_layout_desc {
+ unsigned int pin_start;
+ unsigned int pin_cnt;
+ const char *name;
+ s8 gpio_func_sel;
+};
+
+struct jhb100_pinctrl {
+ struct device *dev;
+ struct gpio_chip gc;
+ unsigned int num_banks;
+ struct pinctrl_gpio_range gpios;
+ raw_spinlock_t lock;
+ const char *iodomain_name;
+ void __iomem *base;
+ struct pinctrl_dev *pctl;
+ /* register read/write mutex */
+ struct mutex mutex;
+ const struct jhb100_pinctrl_domain_info *info;
+ int irq;
+ struct irq_domain *irq_domain;
+ const struct pinctrl_pin_desc *pins;
+ unsigned int npins;
+ unsigned int ngpios;
+ s8 *gpio_func_sel_arr;
+};
+
+struct pinvref_desc {
+ unsigned int range;
+ u32 pin_grp[32];
+ u32 num_pins;
+};
+
+struct pinvref_reg {
+ unsigned int reg;
+ const struct pinvref_desc *pv_desc;
+ u32 num_pv;
+};
+
+struct gpio_irq_reg {
+ unsigned int reg;
+ unsigned int width_per_pin;
+};
+
+struct starfive_pinctrl_regs {
+ struct pinvref_reg vref;
+ struct gpio_irq_reg func_sel;
+ unsigned int config;
+ unsigned int output;
+ unsigned int output_en;
+ unsigned int gpio_status;
+ unsigned int irq_en;
+ unsigned int irq_status;
+ unsigned int irq_clr;
+ unsigned int irq_trigger;
+ unsigned int irq_level;
+ unsigned int irq_both_edge;
+ unsigned int irq_edge;
+};
+
+struct reg_layout_field {
+ unsigned char shift;
+ unsigned char width;
+};
+
+enum jhb100_pad_cfg_field {
+ PAD_CFG_DEBOUNCE_WIDTH,
+ PAD_CFG_DRIVE_STRENGTH_2BIT,
+ PAD_CFG_DRIVE_STRENGTH_3BIT,
+ PAD_CFG_INPUT_ENABLE,
+ PAD_CFG_VSEL,
+ PAD_CFG_MODE_SELECT,
+ PAD_CFG_OPEN_DRAIN_PULL_UP_SEL,
+ PAD_CFG_PULL_DOWN,
+ PAD_CFG_PULL_UP,
+ PAD_CFG_SCHMITT_TRIGGER_SELECT,
+ PAD_CFG_SLEW_RATE,
+ PAD_CFG_COUNT
+};
+
+#define RL_DESC_SUPPORTED(crl_desc, field_enum) ({ \
+ typeof(crl_desc) _desc = (crl_desc); \
+ (_desc && (_desc)->fields[(field_enum)].width > 0); \
+})
+
+#define RL_DESC_SHIFT(crl_desc, field_enum) ({ \
+ typeof(crl_desc) __desc = (crl_desc); \
+ (__desc)->fields[(field_enum)].shift; \
+})
+
+#define RL_DESC_GENMASK(crl_desc, field_enum) ({ \
+ typeof(crl_desc) __desc = (crl_desc); \
+ RL_DESC_SUPPORTED(__desc, field_enum) ? \
+ GENMASK( \
+ (__desc)->fields[(field_enum)].shift + (__desc)->fields[(field_enum)].width - 1, \
+ (__desc)->fields[(field_enum)].shift \
+ ) : 0; \
+})
+
+struct config_reg_layout_desc {
+ unsigned int pin_start;
+ unsigned int pin_cnt;
+
+ struct reg_layout_field fields[PAD_CFG_COUNT];
+};
+
+#define JHB100_FUNC_MAPS_MAX_PIN(n) ((n) + 1)
+
+struct jhb100_pinctrl_func_maps {
+ char *func;
+ unsigned char val;
+ u32 max_pin;
+};
+
+struct jhb100_pinctrl_domain_info {
+ const char *name;
+ const struct pinctrl_pin_desc *pins;
+ const struct jhb100_pin_layout_desc *pl_desc;
+ const struct jhb100_pinctrl_func_maps *fmaps;
+ u32 num_maps;
+ const struct config_reg_layout_desc *crl_desc;
+ const struct starfive_pinctrl_regs *regs;
+};
+
+int jhb100_pinctrl_probe(struct platform_device *pdev);
+
+#endif /* __PINCTRL_STARFIVE_JHB100_H__ */
--
2.25.1
_______________________________________________
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linux-riscv@lists.infradead.org
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 05/22] dt-bindings: pinctrl: Add starfive,jhb100-sys0h-pinctrl
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (3 preceding siblings ...)
2026-09-10 10:03 ` [PATCH v8 04/22] pinctrl: starfive: Add StarFive JHB100 sys0 controller driver Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 06/22] pinctrl: starfive: Add StarFive JHB100 sys0h controller driver Changhuang Liang
` (16 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC System-0 host(sys0h) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../starfive,jhb100-sys0h-pinctrl.yaml | 162 ++++++++++++++++++
1 file changed, 162 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0h-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0h-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0h-pinctrl.yaml
new file mode 100644
index 000000000000..bfbd36928d7c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0h-pinctrl.yaml
@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys0h-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 System-0 Host Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "sys0h" pinctrl domain.
+
+ The "sys0h" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO pad configuration.
+ - GPIO interrupt handling.
+
+ In the SYS0H Pin Controller, there are 12 multi-function GPIO_PADs. Each of
+ them can be multiplexed to different hardware blocks through function
+ selection. Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3.
+ Function 0 is the default function which is generally the GPIO function
+ (or occasionally, it can be a peripheral signal).
+ Functions 1, 2, and 3 are the alternate functions or peripheral signals that
+ can be routed to the iopad. The function selection can be carried out by
+ writing the function number to the iopad function select register.
+
+ Each iopad is configurable with parameters such as input-enable, internal
+ pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
+ debounce nanoseconds.
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-sys0h-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges: true
+
+ gpio-line-names: true
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate, input debounce nanoseconds and
+ drive-strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ additionalProperties: false
+
+ properties:
+ pins:
+ description:
+ The list of IOs that properties in the pincfg node apply to.
+
+ function:
+ description:
+ A string containing the name of the function to mux for these
+ pins.
+ enum: [ espi, espi_reset, espi0_vw, espi1_vw, gpio, scap_trigger ]
+
+ bias-disable: true
+
+ bias-pull-down:
+ type: boolean
+
+ bias-pull-up:
+ type: boolean
+
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 4000, 8000, 12000 ]
+
+ input-debounce-ns:
+ minimum: 0
+ maximum: 10485680
+ description:
+ Debounce time in nanoseconds. The hardware counts in 80 ns
+ stages with a 17-bit counter, so the maximum is 10485680 ns.
+ input-disable: true
+
+ input-enable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow
+ 1: fast
+required:
+ - compatible
+ - reg
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_sys0h: pinctrl@13080800 {
+ compatible = "starfive,jhb100-sys0h-pinctrl";
+ reg = <0x0 0x13080800 0x0 0x800>;
+ resets = <&sys0crg 3>;
+ interrupts = <57>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_sys0h 0 0 12>;
+ };
+ };
--
2.25.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 06/22] pinctrl: starfive: Add StarFive JHB100 sys0h controller driver
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (4 preceding siblings ...)
2026-09-10 10:03 ` [PATCH v8 05/22] dt-bindings: pinctrl: Add starfive,jhb100-sys0h-pinctrl Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 07/22] dt-bindings: pinctrl: Add starfive,jhb100-sys1-pinctrl Changhuang Liang
` (15 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC System-0 Host(sys0h) pinctrl
controller.
Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Alex Soo <yuklin.soo@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 11 +++
drivers/pinctrl/starfive/Makefile | 1 +
.../starfive/pinctrl-starfive-jhb100-sys0h.c | 99 +++++++++++++++++++
3 files changed, 111 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0h.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index b3cb513c23de..992238f5b49d 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -66,3 +66,14 @@ config PINCTRL_STARFIVE_JHB100_SYS0
This also provides an interface to the GPIO pins not used by other
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+
+config PINCTRL_STARFIVE_JHB100_SYS0H
+ tristate "StarFive JHB100 SoC System-0 Host pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select PINCTRL_STARFIVE_JHB100
+ default ARCH_STARFIVE
+ help
+ Say yes here to support System-0 Host pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index c0d368f413bc..b26156a6d0eb 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0h.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0h.c
new file mode 100644
index 000000000000..fb486ac60072
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0h.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC System-0 host domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+/* sys0h pad numbers */
+#define PADNUM_SYS0H_GPIO_A10 6
+#define PADNUM_SYS0H_GPIO_A11 7
+#define PADNUM_SYS0H_GPIO_A15 11
+
+static const struct jhb100_pin_layout_desc jhb100_sys0h_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 7, .name = "gpio", .gpio_func_sel = 0 },
+ { .pin_start = 7, .pin_cnt = 1, .name = "espi0_reset", .gpio_func_sel = 1 },
+ { .pin_start = 8, .pin_cnt = 4, .name = "gpio", .gpio_func_sel = 0 },
+ { 0xff },
+};
+
+static const struct config_reg_layout_desc jhb100_sys0h_pinctrl_rl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 12,
+ .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 },
+ .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 },
+ .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 },
+ .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 },
+ .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 },
+ .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 },
+ .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 },
+ },
+ { 0xff },
+};
+
+static const struct starfive_pinctrl_regs jhb100_sys0h_pinctrl_regs = {
+ .func_sel = { .reg = 0x40, .width_per_pin = 2 },
+ .config = 0x04,
+ .output = 0x34,
+ .output_en = 0x38,
+ .gpio_status = 0x3c,
+ .irq_en = 0x44,
+ .irq_status = 0x48,
+ .irq_clr = 0x4c,
+ .irq_trigger = 0x50,
+ .irq_level = 0x54,
+ .irq_both_edge = 0x58,
+ .irq_edge = 0x5c,
+};
+
+static const struct jhb100_pinctrl_func_maps jhb100_func_maps_sys0h[] = {
+ { .func = "espi", .val = 1 },
+ { .func = "espi_reset", .val = 0 },
+ { .func = "espi0_vw", .val = 1 },
+ { .func = "espi1_vw", .val = 2 },
+ { .func = "gpio", .val = 0,
+ .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_SYS0H_GPIO_A10) },
+ { .func = "gpio", .val = 1,
+ .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_SYS0H_GPIO_A11) },
+ { .func = "gpio", .val = 0,
+ .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_SYS0H_GPIO_A15) },
+ { .func = "scap_trigger", .val = 3 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_sys0h_pinctrl_info = {
+ .name = "jhb100-sys0h",
+ .pl_desc = jhb100_sys0h_pl_desc,
+ .crl_desc = jhb100_sys0h_pinctrl_rl_desc,
+ .regs = &jhb100_sys0h_pinctrl_regs,
+ .fmaps = jhb100_func_maps_sys0h,
+ .num_maps = ARRAY_SIZE(jhb100_func_maps_sys0h),
+};
+
+static const struct of_device_id jhb100_sys0h_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-sys0h-pinctrl",
+ .data = &jhb100_sys0h_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_sys0h_pinctrl_of_match);
+
+static struct platform_driver jhb100_sys0h_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-sys0h-pinctrl",
+ .of_match_table = jhb100_sys0h_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_sys0h_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC System-0 host domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 07/22] dt-bindings: pinctrl: Add starfive,jhb100-sys1-pinctrl
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (5 preceding siblings ...)
2026-09-10 10:03 ` [PATCH v8 06/22] pinctrl: starfive: Add StarFive JHB100 sys0h controller driver Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 08/22] pinctrl: starfive: Add StarFive JHB100 sys1 controller driver Changhuang Liang
` (14 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC System-1(sys1) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../pinctrl/starfive,jhb100-sys1-pinctrl.yaml | 164 ++++++++++++++++++
1 file changed, 164 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys1-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys1-pinctrl.yaml
new file mode 100644
index 000000000000..55e111117ea0
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys1-pinctrl.yaml
@@ -0,0 +1,164 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys1-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 System-1 Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "sys1" pinctrl domain.
+
+ The "sys1" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO pad configuration.
+ - GPIO interrupt handling.
+
+ In the SYS1 Pin Controller, there are 8 multi-function GPIO_PADs. Each of
+ them can be multiplexed to different hardware blocks through function
+ selection. Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3.
+ Function 0 is the default function which is generally the GPIO function
+ (or occasionally, it can be a peripheral signal).
+ Function 1, 2, and 3 are the alternate functions or peripheral signals that
+ can be routed to the iopad. The function selection can be carried out by
+ writing the function number to the iopad function select register.
+
+ Each iopad is configurable with parameters such as input-enable, internal
+ pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
+ debounce nanoseconds.
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-sys1-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges: true
+
+ gpio-line-names: true
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate, input debounce nanoseconds
+ and drive-strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ additionalProperties: false
+
+ properties:
+ pins:
+ description:
+ The list of IOs that properties in the pincfg node apply to.
+
+ function:
+ description:
+ A string containing the name of the function to mux for these
+ pins.
+ enum: [ espi, espi_reset, gpio, host0_port80, host1_port80 ]
+
+ bias-disable: true
+
+ bias-pull-down:
+ type: boolean
+
+ bias-pull-up:
+ type: boolean
+
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 4000, 8000, 12000 ]
+
+ input-debounce-ns:
+ minimum: 0
+ maximum: 10485680
+ description:
+ Debounce time in nanoseconds. The hardware counts in 80 ns
+ stages with a 17-bit counter, so the maximum is 10485680 ns.
+
+ input-disable: true
+
+ input-enable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow
+ 1: fast
+
+required:
+ - compatible
+ - reg
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_sys1: pinctrl@13081000 {
+ compatible = "starfive,jhb100-sys1-pinctrl";
+ reg = <0x0 0x13081000 0x0 0x1000>;
+ resets = <&sys1crg 2>;
+ interrupts = <58>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_sys1 0 0 8>;
+ };
+ };
--
2.25.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 08/22] pinctrl: starfive: Add StarFive JHB100 sys1 controller driver
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (6 preceding siblings ...)
2026-09-10 10:03 ` [PATCH v8 07/22] dt-bindings: pinctrl: Add starfive,jhb100-sys1-pinctrl Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 09/22] dt-bindings: pinctrl: Add starfive,jhb100-sys2-pinctrl Changhuang Liang
` (13 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC System-1(sys1) pinctrl
controller.
Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Alex Soo <yuklin.soo@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 11 +++
drivers/pinctrl/starfive/Makefile | 1 +
.../starfive/pinctrl-starfive-jhb100-sys1.c | 94 +++++++++++++++++++
3 files changed, 106 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys1.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index 992238f5b49d..895b9cb0cb2a 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -77,3 +77,14 @@ config PINCTRL_STARFIVE_JHB100_SYS0H
This also provides an interface to the GPIO pins not used by other
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+
+config PINCTRL_STARFIVE_JHB100_SYS1
+ tristate "StarFive JHB100 SoC System-1 pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select PINCTRL_STARFIVE_JHB100
+ default ARCH_STARFIVE
+ help
+ Say yes here to support System-1 pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index b26156a6d0eb..8d96cf80d377 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys1.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys1.c
new file mode 100644
index 000000000000..2185c3d15bc2
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys1.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC System-1 domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+/* sys1 pad numbers */
+#define PADNUM_SYS1_GPIO_A22 6
+#define PADNUM_SYS1_GPIO_A23 7
+
+static const struct jhb100_pin_layout_desc jhb100_sys1_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 7, .name = "gpio", .gpio_func_sel = 0 },
+ { .pin_start = 7, .pin_cnt = 1, .name = "espi1_reset", .gpio_func_sel = 1 },
+ { 0xff },
+};
+
+static const struct config_reg_layout_desc jhb100_sys1_pinctrl_rl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 8,
+ .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 },
+ .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 },
+ .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 },
+ .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 },
+ .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 },
+ .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 },
+ .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 },
+ },
+ { 0xff },
+};
+
+static const struct starfive_pinctrl_regs jhb100_sys1_pinctrl_regs = {
+ .func_sel = { .reg = 0x30, .width_per_pin = 2 },
+ .config = 0x04,
+ .output = 0x24,
+ .output_en = 0x28,
+ .gpio_status = 0x2c,
+ .irq_en = 0x34,
+ .irq_status = 0x38,
+ .irq_clr = 0x3c,
+ .irq_trigger = 0x40,
+ .irq_level = 0x44,
+ .irq_both_edge = 0x48,
+ .irq_edge = 0x4c,
+};
+
+static const struct jhb100_pinctrl_func_maps jhb100_func_maps_sys1[] = {
+ { .func = "espi", .val = 1 },
+ { .func = "espi_reset", .val = 0 },
+ { .func = "gpio", .val = 0,
+ .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_SYS1_GPIO_A22) },
+ { .func = "gpio", .val = 1,
+ .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_SYS1_GPIO_A23) },
+ { .func = "host0_port80", .val = 2 },
+ { .func = "host1_port80", .val = 3 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_sys1_pinctrl_info = {
+ .name = "jhb100-sys1",
+ .pl_desc = jhb100_sys1_pl_desc,
+ .crl_desc = jhb100_sys1_pinctrl_rl_desc,
+ .regs = &jhb100_sys1_pinctrl_regs,
+ .fmaps = jhb100_func_maps_sys1,
+ .num_maps = ARRAY_SIZE(jhb100_func_maps_sys1),
+};
+
+static const struct of_device_id jhb100_sys1_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-sys1-pinctrl",
+ .data = &jhb100_sys1_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_sys1_pinctrl_of_match);
+
+static struct platform_driver jhb100_sys1_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-sys1-pinctrl",
+ .of_match_table = jhb100_sys1_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_sys1_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC System-1 domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 09/22] dt-bindings: pinctrl: Add starfive,jhb100-sys2-pinctrl
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (7 preceding siblings ...)
2026-09-10 10:03 ` [PATCH v8 08/22] pinctrl: starfive: Add StarFive JHB100 sys1 controller driver Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 10/22] pinctrl: starfive: Add StarFive JHB100 sys2 controller driver Changhuang Liang
` (12 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC System-2(sys2) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../pinctrl/starfive,jhb100-sys2-pinctrl.yaml | 165 ++++++++++++++++++
1 file changed, 165 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml
new file mode 100644
index 000000000000..e2d18e0d4916
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml
@@ -0,0 +1,165 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys2-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 System-2 Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "sys2" pinctrl domain.
+
+ The "sys2" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO pad configuration.
+ - GPIO interrupt handling.
+
+ In the SYS2 Pin Controller, there are 37 multi-function GPIO_PADs. Each of
+ them can be multiplexed to different hardware blocks through function
+ selection. Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3.
+ Function 0 is the default function which is the GPIO function.
+ Function 1, 2, and 3 are the alternate functions or peripheral signals that
+ can be routed to the iopad. The function selection can be carried out by
+ writing the function number to the iopad function select register.
+
+ Each iopad is configurable with parameters such as input-enable, internal
+ pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
+ debounce nanoseconds, power source.
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-sys2-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges: true
+
+ gpio-line-names: true
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate, input debounce nanoseconds,
+ power-source and drive-strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ additionalProperties: false
+
+ properties:
+ pins:
+ description:
+ The list of IOs that properties in the pincfg node apply to.
+
+ function:
+ description:
+ A string containing the name of the function to mux for these
+ pins.
+ enum: [ gpio, host0_port80, host1_port80, jtag, smbalert, uart ]
+
+ bias-disable: true
+
+ bias-pull-down:
+ type: boolean
+
+ bias-pull-up:
+ type: boolean
+
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 4000, 8000, 12000 ]
+
+ input-debounce-ns:
+ minimum: 0
+ maximum: 10485680
+ description:
+ Debounce time in nanoseconds. The hardware counts in 80 ns
+ stages with a 17-bit counter, so the maximum is 10485680 ns.
+
+ input-disable: true
+
+ input-enable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ power-source:
+ enum: [ 1800, 3300 ]
+ description: I/O voltage in millivolt.
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow
+ 1: fast
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_sys2: pinctrl@13082000 {
+ compatible = "starfive,jhb100-sys2-pinctrl";
+ reg = <0x0 0x13082000 0x0 0x1000>;
+ interrupts = <59>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_sys2 0 0 37>;
+ };
+ };
--
2.25.1
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 10/22] pinctrl: starfive: Add StarFive JHB100 sys2 controller driver
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (8 preceding siblings ...)
2026-09-10 10:03 ` [PATCH v8 09/22] dt-bindings: pinctrl: Add starfive,jhb100-sys2-pinctrl Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 11/22] dt-bindings: pinctrl: Add starfive,jhb100-per0-pinctrl Changhuang Liang
` (11 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC System-2(sys2) pinctrl
controller.
Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Alex Soo <yuklin.soo@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 11 ++
drivers/pinctrl/starfive/Makefile | 1 +
.../starfive/pinctrl-starfive-jhb100-sys2.c | 140 ++++++++++++++++++
3 files changed, 152 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys2.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index 895b9cb0cb2a..1d7e661455a8 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -88,3 +88,14 @@ config PINCTRL_STARFIVE_JHB100_SYS1
This also provides an interface to the GPIO pins not used by other
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+
+config PINCTRL_STARFIVE_JHB100_SYS2
+ tristate "StarFive JHB100 SoC System-2 pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select PINCTRL_STARFIVE_JHB100
+ default ARCH_STARFIVE
+ help
+ Say yes here to support System-2 pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index 8d96cf80d377..b817ad93b91d 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS2) += pinctrl-starfive-jhb100-sys2.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys2.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys2.c
new file mode 100644
index 000000000000..2744744882e8
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys2.c
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC System-2 domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+/* sys2 pad numbers */
+#define PADNUM_SYS2_GPIO_A36 12
+#define PADNUM_SYS2_GPIO_A37 13
+#define PADNUM_SYS2_GPIO_A38 14
+#define PADNUM_SYS2_GPIO_A39 15
+#define PADNUM_SYS2_GPIO_A40 16
+#define PADNUM_SYS2_GPIO_A41 17
+#define PADNUM_SYS2_GPIO_A42 18
+#define PADNUM_SYS2_GPIO_A43 19
+
+static const struct jhb100_pin_layout_desc jhb100_sys2_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 37, .name = "gpio", .gpio_func_sel = 0 },
+ { .pin_start = 37, .pin_cnt = 1, .name = "jtag_tck", .gpio_func_sel = -1 },
+ { .pin_start = 38, .pin_cnt = 1, .name = "jtag_tresetn", .gpio_func_sel = -1 },
+ { .pin_start = 39, .pin_cnt = 1, .name = "jtag_tmc", .gpio_func_sel = -1 },
+ { .pin_start = 40, .pin_cnt = 1, .name = "jtag_tdi", .gpio_func_sel = -1 },
+ { .pin_start = 41, .pin_cnt = 1, .name = "jtag_tdo", .gpio_func_sel = -1 },
+ { .pin_start = 42, .pin_cnt = 1, .name = "jtag_hpd", .gpio_func_sel = -1 },
+ { 0xff },
+};
+
+static const struct config_reg_layout_desc jhb100_sys2_pinctrl_rl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 37,
+ .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 },
+ .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 },
+ .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 },
+ .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 },
+ .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 },
+ .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 },
+ .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 },
+ },
+ {
+ .pin_start = 37,
+ .pin_cnt = 6,
+ .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 },
+ .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 },
+ .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 },
+ .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 },
+ .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 },
+ .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 },
+ },
+ { 0xff },
+};
+
+static const struct pinvref_desc pinvref_desc_sys2[] = {
+ {
+ /* gpiow */
+ .pin_grp = {
+ PADNUM_SYS2_GPIO_A36,
+ PADNUM_SYS2_GPIO_A37,
+ PADNUM_SYS2_GPIO_A38,
+ PADNUM_SYS2_GPIO_A39
+ },
+ .num_pins = 4,
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ {
+ /* gpiow-inner */
+ .pin_grp = {
+ PADNUM_SYS2_GPIO_A40,
+ PADNUM_SYS2_GPIO_A41,
+ PADNUM_SYS2_GPIO_A42,
+ PADNUM_SYS2_GPIO_A43
+ },
+ .num_pins = 4,
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+};
+
+static const struct starfive_pinctrl_regs jhb100_sys2_pinctrl_regs = {
+ .vref = { .reg = 0x000, .pv_desc = pinvref_desc_sys2,
+ .num_pv = ARRAY_SIZE(pinvref_desc_sys2) },
+ .func_sel = { .reg = 0x0d4, .width_per_pin = 2 },
+ .config = 0x010,
+ .output = 0x0bc,
+ .output_en = 0x0c4,
+ .gpio_status = 0x0cc,
+ .irq_en = 0x0e0,
+ .irq_status = 0x0e8,
+ .irq_clr = 0x0f0,
+ .irq_trigger = 0x0f8,
+ .irq_level = 0x100,
+ .irq_both_edge = 0x108,
+ .irq_edge = 0x110,
+};
+
+static const struct jhb100_pinctrl_func_maps jhb100_func_maps_sys2[] = {
+ { .func = "gpio", .val = 0 },
+ { .func = "host0_port80", .val = 2 },
+ { .func = "host1_port80", .val = 3 },
+ { .func = "jtag", .val = 2 },
+ { .func = "smbalert", .val = 2 },
+ { .func = "uart", .val = 1 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_sys2_pinctrl_info = {
+ .name = "jhb100-sys2",
+ .pl_desc = jhb100_sys2_pl_desc,
+ .crl_desc = jhb100_sys2_pinctrl_rl_desc,
+ .regs = &jhb100_sys2_pinctrl_regs,
+ .fmaps = jhb100_func_maps_sys2,
+ .num_maps = ARRAY_SIZE(jhb100_func_maps_sys2),
+};
+
+static const struct of_device_id jhb100_sys2_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-sys2-pinctrl",
+ .data = &jhb100_sys2_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_sys2_pinctrl_of_match);
+
+static struct platform_driver jhb100_sys2_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-sys2-pinctrl",
+ .of_match_table = jhb100_sys2_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_sys2_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC System-2 domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 11/22] dt-bindings: pinctrl: Add starfive,jhb100-per0-pinctrl
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (9 preceding siblings ...)
2026-09-10 10:03 ` [PATCH v8 10/22] pinctrl: starfive: Add StarFive JHB100 sys2 controller driver Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 12/22] pinctrl: starfive: Add StarFive JHB100 per0 controller driver Changhuang Liang
` (10 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC Peripheral-0(per0) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../pinctrl/starfive,jhb100-per0-pinctrl.yaml | 179 ++++++++++++++++++
1 file changed, 179 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml
new file mode 100644
index 000000000000..0e7e7f231e2b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml
@@ -0,0 +1,179 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per0-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 Peripheral-0 Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "per0" pinctrl domain.
+
+ The "per0" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO pad configuration.
+ - GPIO interrupt handling.
+
+ In the Peripheral-0 Pin Controller, there are 60 multi-function GPIO_PADs.
+ Each of them can be multiplexed to several hardware blocks through function
+ selection. Each iopad has a maximum of up to 3 functions - 0, 1, and 2.
+ Function 0 is the default function which is generally the GPIO function.
+ Function 1 and 2 are the alternate function or signal of an iopad. The
+ function 1 and function 2 are other optional functions or peripheral
+ signals that can be routed to an iopad. The function selection can be carried
+ out by writing the function number to the iopad function select register.
+
+ Each iopad is configurable with parameters such as input-enable, internal
+ pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
+ debounce nanoseconds, power source and drive type (open-drain or push-pull).
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-per0-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges: true
+
+ gpio-line-names: true
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate, input debounce nanoseconds,
+ drive-open-drain, drive-push-pull, power-source and drive-strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ additionalProperties: false
+
+ properties:
+ pins:
+ description:
+ The list of IOs that properties in the pincfg node apply to.
+
+ function:
+ description:
+ A string containing the name of the function to mux for these
+ pins.
+ enum: [ gmac_mdio, gpio, i2c, i3c, smbalert, wdt ]
+
+ bias-disable: true
+
+ bias-pull-down:
+ type: boolean
+
+ bias-pull-up:
+ oneOf:
+ - type: boolean
+ - enum: [ 600, 900, 1200, 2000 ]
+ description: Pull up RSEL type resistance values (in ohms)
+ description:
+ For normal pull up type there is no need to specify a resistance
+ value, hence this can be specified as a boolean property.
+ For RSEL pull up type a resistance value (in ohms) can be added.
+
+ drive-open-drain: true
+
+ drive-push-pull: true
+
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 4000, 8000, 12000 ]
+
+ input-debounce-ns:
+ minimum: 0
+ maximum: 10485680
+ description:
+ Debounce time in nanoseconds. The hardware counts in 80 ns
+ stages with a 17-bit counter, so the maximum is 10485680 ns.
+
+ input-disable: true
+
+ input-enable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ power-source:
+ enum: [ 1800, 3300 ]
+ description: I/O voltage in millivolt.
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow
+ 1: fast
+
+required:
+ - compatible
+ - reg
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_per0: pinctrl@11a0a000 {
+ compatible = "starfive,jhb100-per0-pinctrl";
+ reg = <0x0 0x11a0a000 0x0 0x1000>;
+ resets = <&per0crg 0>;
+ interrupts = <60>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per0 0 0 60>;
+ };
+ };
--
2.25.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 12/22] pinctrl: starfive: Add StarFive JHB100 per0 controller driver
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (10 preceding siblings ...)
2026-09-10 10:03 ` [PATCH v8 11/22] dt-bindings: pinctrl: Add starfive,jhb100-per0-pinctrl Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 13/22] dt-bindings: pinctrl: Add starfive,jhb100-per1-pinctrl Changhuang Liang
` (9 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC Peripheral-0(per0) pinctrl
controller.
Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Alex Soo <yuklin.soo@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 11 ++
drivers/pinctrl/starfive/Makefile | 1 +
.../starfive/pinctrl-starfive-jhb100-per0.c | 182 ++++++++++++++++++
3 files changed, 194 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per0.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index 1d7e661455a8..07f9cb3d6eae 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -56,6 +56,17 @@ config PINCTRL_STARFIVE_JHB100
select GPIOLIB_IRQCHIP
select OF_GPIO
+config PINCTRL_STARFIVE_JHB100_PER0
+ tristate "StarFive JHB100 SoC Peripheral-0 pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select PINCTRL_STARFIVE_JHB100
+ default ARCH_STARFIVE
+ help
+ Say yes here to support Peripheral-0 pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
+
config PINCTRL_STARFIVE_JHB100_SYS0
tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index b817ad93b91d..f2bb0c35a2a0 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_SYS) += pinctrl-starfive-jh7110-sys.o
obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per0.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per0.c
new file mode 100644
index 000000000000..679954b19808
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per0.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC Peripheral-0 domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+/* per0 pad numbers */
+#define PADNUM_PER0_GPIO_B8 8
+#define PADNUM_PER0_GPIO_B9 9
+#define PADNUM_PER0_GPIO_B10 10
+#define PADNUM_PER0_GPIO_B11 11
+#define PADNUM_PER0_GPIO_B12 12
+#define PADNUM_PER0_GPIO_B13 13
+#define PADNUM_PER0_GPIO_B14 14
+#define PADNUM_PER0_GPIO_B15 15
+#define PADNUM_PER0_GPIO_B16 16
+#define PADNUM_PER0_GPIO_B17 17
+#define PADNUM_PER0_GPIO_B18 18
+#define PADNUM_PER0_GPIO_B19 19
+#define PADNUM_PER0_GPIO_B20 20
+#define PADNUM_PER0_GPIO_B21 21
+#define PADNUM_PER0_GPIO_B22 22
+#define PADNUM_PER0_GPIO_B23 23
+#define PADNUM_PER0_GPIO_B32 32
+#define PADNUM_PER0_GPIO_B33 33
+#define PADNUM_PER0_GPIO_B34 34
+#define PADNUM_PER0_GPIO_B35 35
+#define PADNUM_PER0_GPIO_B36 36
+#define PADNUM_PER0_GPIO_B37 37
+#define PADNUM_PER0_GPIO_B38 38
+#define PADNUM_PER0_GPIO_B39 39
+#define PADNUM_PER0_GPIO_B40 40
+#define PADNUM_PER0_GPIO_B41 41
+#define PADNUM_PER0_GPIO_B42 42
+#define PADNUM_PER0_GPIO_B43 43
+#define PADNUM_PER0_GPIO_B59 59
+
+static const struct jhb100_pin_layout_desc jhb100_per0_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 60, .name = "gpio", .gpio_func_sel = 0 },
+ { 0xff },
+};
+
+static const struct config_reg_layout_desc jhb100_per0_pinctrl_rl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 60,
+ .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 0, .width = 1 },
+ .fields[PAD_CFG_MODE_SELECT] = { .shift = 1, .width = 2 },
+ .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 },
+ .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 },
+ .fields[PAD_CFG_OPEN_DRAIN_PULL_UP_SEL] = { .shift = 5, .width = 2 },
+ .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 7, .width = 1 },
+ .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 },
+ },
+ { 0xff },
+};
+
+static const struct pinvref_desc pinvref_desc_per0[] = {
+ {
+ /* gpioe-i3c0 */
+ .pin_grp = {
+ PADNUM_PER0_GPIO_B8,
+ PADNUM_PER0_GPIO_B9,
+ PADNUM_PER0_GPIO_B10,
+ PADNUM_PER0_GPIO_B11,
+ PADNUM_PER0_GPIO_B32,
+ PADNUM_PER0_GPIO_B33
+ },
+ .num_pins = 6,
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ {
+ /* gpioe-i3c1 */
+ .pin_grp = {
+ PADNUM_PER0_GPIO_B12,
+ PADNUM_PER0_GPIO_B13,
+ PADNUM_PER0_GPIO_B14,
+ PADNUM_PER0_GPIO_B15,
+ PADNUM_PER0_GPIO_B34,
+ PADNUM_PER0_GPIO_B35
+ },
+ .num_pins = 6,
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ {
+ /* gpioe-i3c2 */
+ .pin_grp = {
+ PADNUM_PER0_GPIO_B16,
+ PADNUM_PER0_GPIO_B17,
+ PADNUM_PER0_GPIO_B18,
+ PADNUM_PER0_GPIO_B19,
+ PADNUM_PER0_GPIO_B20,
+ PADNUM_PER0_GPIO_B21,
+ PADNUM_PER0_GPIO_B22,
+ PADNUM_PER0_GPIO_B23
+ },
+ .num_pins = 8,
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ {
+ /* gpioe-i3c4 */
+ .pin_grp = {
+ PADNUM_PER0_GPIO_B36,
+ PADNUM_PER0_GPIO_B37,
+ PADNUM_PER0_GPIO_B38,
+ PADNUM_PER0_GPIO_B39,
+ PADNUM_PER0_GPIO_B40,
+ PADNUM_PER0_GPIO_B41,
+ PADNUM_PER0_GPIO_B42,
+ PADNUM_PER0_GPIO_B43
+ },
+ .num_pins = 8,
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+};
+
+static const struct starfive_pinctrl_regs jhb100_per0_pinctrl_regs = {
+ .vref = { .reg = 0x004, .pv_desc = pinvref_desc_per0,
+ .num_pv = ARRAY_SIZE(pinvref_desc_per0) },
+ .func_sel = { .reg = 0x11c, .width_per_pin = 2 },
+ .config = 0x014,
+ .output = 0x104,
+ .output_en = 0x10c,
+ .gpio_status = 0x114,
+ .irq_en = 0x12c,
+ .irq_status = 0x134,
+ .irq_clr = 0x13c,
+ .irq_trigger = 0x144,
+ .irq_level = 0x14c,
+ .irq_both_edge = 0x154,
+ .irq_edge = 0x15c,
+};
+
+static const struct jhb100_pinctrl_func_maps jhb100_func_maps_per0[] = {
+ { .func = "gmac_mdio", .val = 2 },
+ { .func = "gpio", .val = 0 },
+ { .func = "i2c", .val = 1 },
+ { .func = "i3c", .val = 2,
+ .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER0_GPIO_B23) },
+ { .func = "i3c", .val = 1,
+ .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER0_GPIO_B59) },
+ { .func = "smbalert", .val = 1 },
+ { .func = "wdt", .val = 2 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_per0_pinctrl_info = {
+ .name = "jhb100-per0",
+ .pl_desc = jhb100_per0_pl_desc,
+ .crl_desc = jhb100_per0_pinctrl_rl_desc,
+ .regs = &jhb100_per0_pinctrl_regs,
+ .fmaps = jhb100_func_maps_per0,
+ .num_maps = ARRAY_SIZE(jhb100_func_maps_per0),
+};
+
+static const struct of_device_id jhb100_per0_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-per0-pinctrl",
+ .data = &jhb100_per0_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per0_pinctrl_of_match);
+
+static struct platform_driver jhb100_per0_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-per0-pinctrl",
+ .of_match_table = jhb100_per0_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_per0_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC Peripheral-0 domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 13/22] dt-bindings: pinctrl: Add starfive,jhb100-per1-pinctrl
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (11 preceding siblings ...)
2026-09-10 10:03 ` [PATCH v8 12/22] pinctrl: starfive: Add StarFive JHB100 per0 controller driver Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 14/22] pinctrl: starfive: Add StarFive JHB100 per1 controller driver Changhuang Liang
` (8 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC Peripheral-1(per1) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../pinctrl/starfive,jhb100-per1-pinctrl.yaml | 178 ++++++++++++++++++
1 file changed, 178 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml
new file mode 100644
index 000000000000..932dcc8ace85
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml
@@ -0,0 +1,178 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per1-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 Peripheral-1 Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "per1" pinctrl domain.
+
+ The "per1" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO pad configuration.
+ - GPIO interrupt handling.
+
+ In the Peripheral-1 Pin Controller, there are 36 multi-function GPIO_PADs.
+ Each of them can be multiplexed to several peripherals through function
+ selection. Each iopad has a maximum of up to 3 functions - 0, 1, and 2.
+ Function 0 is the default function which is generally the GPIO function.
+ Function 1 and 2 are the alternate functions or peripheral signals that
+ can be routed to the iopad. The function selection can be carried out by
+ writing the function number to the iopad function select register.
+
+ Each iopad is configurable with parameters such as input-enable, internal
+ pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
+ debounce nanoseconds, power source and drive type (open-drain or push-pull).
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-per1-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges: true
+
+ gpio-line-names: true
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate, input debounce nanoseconds,
+ drive-open-drain, drive-push-pull, power-source and drive-strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ additionalProperties: false
+
+ properties:
+ pins:
+ description:
+ The list of IOs that properties in the pincfg node apply to.
+
+ function:
+ description:
+ A string containing the name of the function to mux for these
+ pins.
+ enum: [ gpio, i2c, sfc, sgpio, spi ]
+
+ bias-disable: true
+
+ bias-pull-down:
+ type: boolean
+
+ bias-pull-up:
+ oneOf:
+ - type: boolean
+ - enum: [ 600, 900, 1200, 2000 ]
+ description: Pull up RSEL type resistance values (in ohms)
+ description:
+ For normal pull up type there is no need to specify a resistance
+ value, hence this can be specified as a boolean property.
+ For RSEL pull up type a resistance value (in ohms) can be added.
+
+ drive-open-drain: true
+
+ drive-push-pull: true
+
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 4000, 8000, 12000 ]
+
+ input-debounce-ns:
+ minimum: 0
+ maximum: 10485680
+ description:
+ Debounce time in nanoseconds. The hardware counts in 80 ns
+ stages with a 17-bit counter, so the maximum is 10485680 ns.
+
+ input-disable: true
+
+ input-enable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ power-source:
+ enum: [ 1800, 3300 ]
+ description: I/O voltage in millivolt.
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow
+ 1: fast
+
+required:
+ - compatible
+ - reg
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_per1: pinctrl@11b42000 {
+ compatible = "starfive,jhb100-per1-pinctrl";
+ reg = <0x0 0x11b42000 0x0 0x800>;
+ resets = <&per1crg 0>;
+ interrupts = <61>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per1 0 0 36>;
+ };
+ };
--
2.25.1
_______________________________________________
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linux-riscv@lists.infradead.org
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 14/22] pinctrl: starfive: Add StarFive JHB100 per1 controller driver
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (12 preceding siblings ...)
2026-09-10 10:03 ` [PATCH v8 13/22] dt-bindings: pinctrl: Add starfive,jhb100-per1-pinctrl Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 15/22] dt-bindings: pinctrl: Add starfive,jhb100-per2-pinctrl Changhuang Liang
` (7 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC Peripheral-1(per1) pinctrl
controller.
Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Alex Soo <yuklin.soo@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 11 +
drivers/pinctrl/starfive/Makefile | 1 +
.../starfive/pinctrl-starfive-jhb100-per1.c | 193 ++++++++++++++++++
3 files changed, 205 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index 07f9cb3d6eae..823062be6d9f 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -67,6 +67,17 @@ config PINCTRL_STARFIVE_JHB100_PER0
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+config PINCTRL_STARFIVE_JHB100_PER1
+ tristate "StarFive JHB100 SoC Peripheral-1 pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select PINCTRL_STARFIVE_JHB100
+ default ARCH_STARFIVE
+ help
+ Say yes here to support Peripheral-1 pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
+
config PINCTRL_STARFIVE_JHB100_SYS0
tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index f2bb0c35a2a0..6beef7e313ef 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER1) += pinctrl-starfive-jhb100-per1.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c
new file mode 100644
index 000000000000..45fc231e2c86
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC Peripheral-1 domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+/* per1 pad numbers */
+#define PADNUM_PER1_GPIO_C0 0
+#define PADNUM_PER1_GPIO_C1 1
+#define PADNUM_PER1_GPIO_C2 2
+#define PADNUM_PER1_GPIO_C3 3
+#define PADNUM_PER1_GPIO_C4 4
+#define PADNUM_PER1_GPIO_C5 5
+#define PADNUM_PER1_GPIO_C6 6
+#define PADNUM_PER1_GPIO_C7 7
+#define PADNUM_PER1_GPIO_C8 8
+#define PADNUM_PER1_GPIO_C9 9
+#define PADNUM_PER1_GPIO_C10 10
+#define PADNUM_PER1_GPIO_C11 11
+#define PADNUM_PER1_GPIO_C12 12
+#define PADNUM_PER1_GPIO_C13 13
+#define PADNUM_PER1_GPIO_C14 14
+#define PADNUM_PER1_GPIO_C15 15
+#define PADNUM_PER1_GPIO_C16 16
+#define PADNUM_PER1_GPIO_C17 17
+#define PADNUM_PER1_GPIO_C18 18
+#define PADNUM_PER1_GPIO_C19 19
+#define PADNUM_PER1_GPIO_C20 20
+#define PADNUM_PER1_GPIO_C21 21
+#define PADNUM_PER1_GPIO_C22 22
+#define PADNUM_PER1_GPIO_C23 23
+#define PADNUM_PER1_GPIO_C24 24
+#define PADNUM_PER1_GPIO_C25 25
+#define PADNUM_PER1_GPIO_C26 26
+#define PADNUM_PER1_GPIO_C27 27
+#define PADNUM_PER1_GPIO_C31 31
+#define PADNUM_PER1_GPIO_C35 35
+
+static const struct jhb100_pin_layout_desc jhb100_per1_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 36, .name = "gpio", .gpio_func_sel = 0 },
+ { 0xff },
+};
+
+static const struct config_reg_layout_desc jhb100_per1_pinctr_rldesc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 32,
+ .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 },
+ .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 },
+ .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 },
+ .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 },
+ .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 },
+ .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 },
+ .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 },
+ },
+ {
+ .pin_start = 32,
+ .pin_cnt = 4,
+ .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 0, .width = 1 },
+ .fields[PAD_CFG_MODE_SELECT] = { .shift = 1, .width = 2 },
+ .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 },
+ .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 },
+ .fields[PAD_CFG_OPEN_DRAIN_PULL_UP_SEL] = { .shift = 5, .width = 2 },
+ .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 7, .width = 1 },
+ .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 },
+ },
+ { 0xff },
+};
+
+static const struct pinvref_desc pinvref_desc_per1[] = {
+ {
+ /* gpioe-spi */
+ .pin_grp = {
+ PADNUM_PER1_GPIO_C0,
+ PADNUM_PER1_GPIO_C1,
+ PADNUM_PER1_GPIO_C2,
+ PADNUM_PER1_GPIO_C3,
+ PADNUM_PER1_GPIO_C4
+ },
+ .num_pins = 5,
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ {
+ /* gpioe-qspi0 */
+ .pin_grp = {
+ PADNUM_PER1_GPIO_C5,
+ PADNUM_PER1_GPIO_C6,
+ PADNUM_PER1_GPIO_C7,
+ PADNUM_PER1_GPIO_C8,
+ PADNUM_PER1_GPIO_C9,
+ PADNUM_PER1_GPIO_C10,
+ PADNUM_PER1_GPIO_C11
+ },
+ .num_pins = 7,
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ {
+ /* gpioe-qspi1 */
+ .pin_grp = {
+ PADNUM_PER1_GPIO_C12,
+ PADNUM_PER1_GPIO_C13,
+ PADNUM_PER1_GPIO_C14,
+ PADNUM_PER1_GPIO_C15,
+ PADNUM_PER1_GPIO_C16,
+ PADNUM_PER1_GPIO_C17,
+ PADNUM_PER1_GPIO_C18,
+ PADNUM_PER1_GPIO_C19
+ },
+ .num_pins = 8,
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+ {
+ /* gpioe-qspi2 */
+ .pin_grp = {
+ PADNUM_PER1_GPIO_C20,
+ PADNUM_PER1_GPIO_C21,
+ PADNUM_PER1_GPIO_C22,
+ PADNUM_PER1_GPIO_C23,
+ PADNUM_PER1_GPIO_C24,
+ PADNUM_PER1_GPIO_C25,
+ PADNUM_PER1_GPIO_C26,
+ PADNUM_PER1_GPIO_C27
+ },
+ .num_pins = 8,
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V)
+ },
+};
+
+static const struct starfive_pinctrl_regs jhb100_per1_pinctrl_regs = {
+ .vref = { .reg = 0x00, .pv_desc = pinvref_desc_per1,
+ .num_pv = ARRAY_SIZE(pinvref_desc_per1) },
+ .func_sel = { .reg = 0xbc, .width_per_pin = 2 },
+ .config = 0x14,
+ .output = 0xa4,
+ .output_en = 0xac,
+ .gpio_status = 0xb4,
+ .irq_en = 0xc8,
+ .irq_status = 0xd0,
+ .irq_clr = 0xd8,
+ .irq_trigger = 0xe0,
+ .irq_level = 0xe8,
+ .irq_both_edge = 0xf0,
+ .irq_edge = 0xf8,
+};
+
+static const struct jhb100_pinctrl_func_maps jhb100_func_maps_per1[] = {
+ { .func = "gpio", .val = 0 },
+ { .func = "i2c", .val = 1 },
+ { .func = "sfc", .val = 1 },
+ { .func = "sgpio", .val = 1,
+ .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER1_GPIO_C31) },
+ { .func = "sgpio", .val = 2,
+ .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER1_GPIO_C35) },
+ { .func = "spi", .val = 1 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_per1_pinctrl_info = {
+ .name = "jhb100-per1",
+ .pl_desc = jhb100_per1_pl_desc,
+ .crl_desc = jhb100_per1_pinctr_rldesc,
+ .regs = &jhb100_per1_pinctrl_regs,
+ .fmaps = jhb100_func_maps_per1,
+ .num_maps = ARRAY_SIZE(jhb100_func_maps_per1),
+};
+
+static const struct of_device_id jhb100_per1_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-per1-pinctrl",
+ .data = &jhb100_per1_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per1_pinctrl_of_match);
+
+static struct platform_driver jhb100_per1_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-per1-pinctrl",
+ .of_match_table = jhb100_per1_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_per1_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC Peripheral-1 domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 15/22] dt-bindings: pinctrl: Add starfive,jhb100-per2-pinctrl
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (13 preceding siblings ...)
2026-09-10 10:03 ` [PATCH v8 14/22] pinctrl: starfive: Add StarFive JHB100 per1 controller driver Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 16/22] pinctrl: starfive: Add StarFive JHB100 per2 controller driver Changhuang Liang
` (6 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC Peripheral-2(per2) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../pinctrl/starfive,jhb100-per2-pinctrl.yaml | 168 ++++++++++++++++++
1 file changed, 168 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2-pinctrl.yaml
new file mode 100644
index 000000000000..18ee37a2bb1f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2-pinctrl.yaml
@@ -0,0 +1,168 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per2-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 Peripheral-2 Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "per2" pinctrl domain.
+
+ The "per2" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO pad configuration.
+ - GPIO interrupt handling.
+
+ In the Peripheral-2 Pin Controller, there are 31 multi-function GPIO_PADs.
+ Each of them can be multiplexed to several peripherals through function
+ selection. Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3.
+ Function 0 is the default function which is generally the GPIO function.
+ Function 1, 2, and 3 are the alternate functions or peripheral signals
+ that can be routed to an iopad. The function selection can be carried
+ out by writing the function number to the iopad function select register.
+
+ Each iopad is configurable with parameters such as input-enable, internal
+ pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
+ debounce nanoseconds, power source.
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-per2-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges: true
+
+ gpio-line-names: true
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate, input debounce nanoseconds,
+ power-source and drive-strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ additionalProperties: false
+
+ properties:
+ pins:
+ description:
+ The list of IOs that properties in the pincfg node apply to.
+
+ function:
+ description:
+ A string containing the name of the function to mux for these
+ pins.
+ enum: [ fan_tach, gmac_rgmii, gmac_rmii, gpio, host0_port80,
+ host1_port80 ]
+
+ bias-disable: true
+
+ bias-pull-down:
+ type: boolean
+
+ bias-pull-up:
+ type: boolean
+
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 4000, 8000, 12000 ]
+
+ input-debounce-ns:
+ minimum: 0
+ maximum: 10485680
+ description:
+ Debounce time in nanoseconds. The hardware counts in 80 ns
+ stages with a 17-bit counter, so the maximum is 10485680 ns.
+
+ input-disable: true
+
+ input-enable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ power-source:
+ enum: [ 1800, 2500, 3300 ]
+ description: I/O voltage in millivolt.
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow
+ 1: fast
+
+required:
+ - compatible
+ - reg
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_per2: pinctrl@11bc2000 {
+ compatible = "starfive,jhb100-per2-pinctrl";
+ reg = <0x0 0x11bc2000 0x0 0x400>;
+ resets = <&per2crg 0>;
+ interrupts = <62>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per2 0 0 31>;
+ };
+ };
--
2.25.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 16/22] pinctrl: starfive: Add StarFive JHB100 per2 controller driver
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (14 preceding siblings ...)
2026-09-10 10:03 ` [PATCH v8 15/22] dt-bindings: pinctrl: Add starfive,jhb100-per2-pinctrl Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 17/22] dt-bindings: pinctrl: Add starfive,jhb100-per2pok-pinctrl Changhuang Liang
` (5 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC Peripheral-2(per2) pinctrl
controller.
Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Alex Soo <yuklin.soo@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 11 ++
drivers/pinctrl/starfive/Makefile | 1 +
.../starfive/pinctrl-starfive-jhb100-per2.c | 136 ++++++++++++++++++
3 files changed, 148 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index 823062be6d9f..0c55d712c2e8 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -78,6 +78,17 @@ config PINCTRL_STARFIVE_JHB100_PER1
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+config PINCTRL_STARFIVE_JHB100_PER2
+ tristate "StarFive JHB100 SoC Peripheral-2 pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select PINCTRL_STARFIVE_JHB100
+ default ARCH_STARFIVE
+ help
+ Say yes here to support Peripheral-2 pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
+
config PINCTRL_STARFIVE_JHB100_SYS0
tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index 6beef7e313ef..33213bd1919f 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER1) += pinctrl-starfive-jhb100-per1.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER2) += pinctrl-starfive-jhb100-per2.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2.c
new file mode 100644
index 000000000000..282266a127c7
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC Peripheral-2 domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+/* per2 pad numbers */
+#define PADNUM_PER2_GPIO_D19 19
+#define PADNUM_PER2_GPIO_D20 20
+#define PADNUM_PER2_GPIO_D21 21
+#define PADNUM_PER2_GPIO_D22 22
+#define PADNUM_PER2_GPIO_D23 23
+#define PADNUM_PER2_GPIO_D24 24
+#define PADNUM_PER2_GPIO_D25 25
+#define PADNUM_PER2_GPIO_D26 26
+#define PADNUM_PER2_GPIO_D27 27
+#define PADNUM_PER2_GPIO_D28 28
+#define PADNUM_PER2_GPIO_D29 29
+#define PADNUM_PER2_GPIO_D30 30
+
+static const struct jhb100_pin_layout_desc jhb100_per2_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 15, .name = "gpio", .gpio_func_sel = 0 },
+ { .pin_start = 15, .pin_cnt = 1, .name = "gpio", .gpio_func_sel = -1 },
+ { .pin_start = 16, .pin_cnt = 15, .name = "gpio", .gpio_func_sel = 0 },
+ { 0xff },
+};
+
+static const struct config_reg_layout_desc jhb100_per2_pinctrl_rl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 19,
+ .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 },
+ .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 },
+ .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 },
+ .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 },
+ .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 },
+ .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 },
+ .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 },
+ },
+ {
+ .pin_start = 19,
+ .pin_cnt = 12,
+ .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 0, .width = 1 },
+ .fields[PAD_CFG_SLEW_RATE] = { .shift = 1, .width = 1 },
+ .fields[PAD_CFG_VSEL] = { .shift = 2, .width = 2 },
+ .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 },
+ },
+ { 0xff },
+};
+
+static const struct pinvref_desc pinvref_desc_per2[] = {
+ {
+ /* gpionw */
+ .pin_grp = {
+ PADNUM_PER2_GPIO_D19,
+ PADNUM_PER2_GPIO_D20,
+ PADNUM_PER2_GPIO_D21,
+ PADNUM_PER2_GPIO_D22,
+ PADNUM_PER2_GPIO_D23,
+ PADNUM_PER2_GPIO_D24,
+ PADNUM_PER2_GPIO_D25,
+ PADNUM_PER2_GPIO_D26,
+ PADNUM_PER2_GPIO_D27,
+ PADNUM_PER2_GPIO_D28,
+ PADNUM_PER2_GPIO_D29,
+ PADNUM_PER2_GPIO_D30
+ },
+ .num_pins = 12,
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_2_5V) |
+ BIT(JHB100_PINVREF_3_3V)
+ },
+};
+
+static const struct starfive_pinctrl_regs jhb100_per2_pinctrl_regs = {
+ .vref = { .reg = 0x00, .pv_desc = pinvref_desc_per2,
+ .num_pv = ARRAY_SIZE(pinvref_desc_per2) },
+ .func_sel = { .reg = 0x8c, .width_per_pin = 2 },
+ .config = 0x04,
+ .output = 0x80,
+ .output_en = 0x84,
+ .gpio_status = 0x88,
+ .irq_en = 0x94,
+ .irq_status = 0x98,
+ .irq_clr = 0x9c,
+ .irq_trigger = 0xa0,
+ .irq_level = 0xa4,
+ .irq_both_edge = 0xa8,
+ .irq_edge = 0xac,
+};
+
+static const struct jhb100_pinctrl_func_maps jhb100_func_maps_per2[] = {
+ { .func = "fan_tach", .val = 1 },
+ { .func = "gmac_rgmii", .val = 1 },
+ { .func = "gmac_rmii", .val = 2 },
+ { .func = "gpio", .val = 0 },
+ { .func = "host0_port80", .val = 2 },
+ { .func = "host1_port80", .val = 3 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_per2_pinctrl_info = {
+ .name = "jhb100-per2",
+ .pl_desc = jhb100_per2_pl_desc,
+ .crl_desc = jhb100_per2_pinctrl_rl_desc,
+ .regs = &jhb100_per2_pinctrl_regs,
+ .fmaps = jhb100_func_maps_per2,
+ .num_maps = ARRAY_SIZE(jhb100_func_maps_per2),
+};
+
+static const struct of_device_id jhb100_per2_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-per2-pinctrl",
+ .data = &jhb100_per2_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per2_pinctrl_of_match);
+
+static struct platform_driver jhb100_per2_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-per2-pinctrl",
+ .of_match_table = jhb100_per2_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_per2_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC Peripheral-2 domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 17/22] dt-bindings: pinctrl: Add starfive,jhb100-per2pok-pinctrl
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (15 preceding siblings ...)
2026-09-10 10:03 ` [PATCH v8 16/22] pinctrl: starfive: Add StarFive JHB100 per2 controller driver Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 18/22] pinctrl: starfive: Add StarFive JHB100 per2pok controller driver Changhuang Liang
` (4 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC Peripheral-2 Power OK
(per2pok) pinctrl controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../starfive,jhb100-per2pok-pinctrl.yaml | 162 ++++++++++++++++++
1 file changed, 162 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2pok-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2pok-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2pok-pinctrl.yaml
new file mode 100644
index 000000000000..28a4d7f30cc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per2pok-pinctrl.yaml
@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per2pok-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 Peripheral-2 Power OK Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "per2pok" pinctrl domain.
+
+ The "per2pok" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO interrupt handling.
+
+ In the Peripheral-2 Power OK Pin Controller, there are 18 multi-function
+ GPIO_PADs. Each can be multiplexed to several peripherals through function
+ selection. Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3.
+ Function 0 is the default function or generally the GPIO function.
+ Function 1, 2, and 3 are alternate functions or peripheral signals that can
+ be routed to an iopad. The function selection can be carried out by writing
+ the function number to the iopad function select register.
+
+ Each iopad is configurable with parameters such as input-enable, internal
+ pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
+ debounce nanoseconds.
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-per2pok-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges: true
+
+ gpio-line-names: true
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate, input debounce nanoseconds
+ and drive-strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ additionalProperties: false
+
+ properties:
+ pins:
+ description:
+ The list of IOs that properties in the pincfg node apply to.
+
+ function:
+ description:
+ A string containing the name of the function to mux for these
+ pins.
+ enum: [ can, gpio, host0_port80, host1_port80, passthru, pwm ]
+
+ bias-disable: true
+
+ bias-pull-down:
+ type: boolean
+
+ bias-pull-up:
+ type: boolean
+
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 4000, 8000, 12000 ]
+
+ input-debounce-ns:
+ minimum: 0
+ maximum: 10485680
+ description:
+ Debounce time in nanoseconds. The hardware counts in 80 ns
+ stages with a 17-bit counter, so the maximum is 10485680 ns.
+
+ input-disable: true
+
+ input-enable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow
+ 1: fast
+
+required:
+ - compatible
+ - reg
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_per2pok: pinctrl@11bc2400 {
+ compatible = "starfive,jhb100-per2pok-pinctrl";
+ reg = <0x0 0x11bc2400 0x0 0x400>;
+ resets = <&per2crg 1>;
+ interrupts = <63>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per2pok 0 0 18>;
+ };
+ };
--
2.25.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 18/22] pinctrl: starfive: Add StarFive JHB100 per2pok controller driver
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (16 preceding siblings ...)
2026-09-10 10:03 ` [PATCH v8 17/22] dt-bindings: pinctrl: Add starfive,jhb100-per2pok-pinctrl Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 19/22] dt-bindings: pinctrl: Add starfive,jhb100-per3-pinctrl Changhuang Liang
` (3 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC Peripheral-2 Power OK
(per2pok) pinctrl controller.
Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Alex Soo <yuklin.soo@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 11 +++
drivers/pinctrl/starfive/Makefile | 1 +
.../pinctrl-starfive-jhb100-per2pok.c | 99 +++++++++++++++++++
3 files changed, 111 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2pok.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index 0c55d712c2e8..426be481a3fb 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -89,6 +89,17 @@ config PINCTRL_STARFIVE_JHB100_PER2
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+config PINCTRL_STARFIVE_JHB100_PER2POK
+ tristate "StarFive JHB100 SoC Peripheral-2 Power OK pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select PINCTRL_STARFIVE_JHB100
+ default ARCH_STARFIVE
+ help
+ Say yes here to support Peripheral-2 Power OK pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
+
config PINCTRL_STARFIVE_JHB100_SYS0
tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index 33213bd1919f..213002da9cdd 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER1) += pinctrl-starfive-jhb100-per1.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER2) += pinctrl-starfive-jhb100-per2.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER2POK) += pinctrl-starfive-jhb100-per2pok.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2pok.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2pok.c
new file mode 100644
index 000000000000..6bb3b47e65f0
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per2pok.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC Peripheral-2 Power OK domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+/* per2pok pad numbers */
+#define PADNUM_PER2POK_GPIO_D36 5
+#define PADNUM_PER2POK_GPIO_D40 9
+#define PADNUM_PER2POK_GPIO_D48 17
+
+static const struct jhb100_pin_layout_desc jhb100_per2pok_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 10, .name = "gpio", .gpio_func_sel = 0 },
+ { .pin_start = 10, .pin_cnt = 8, .name = "pwm_channel", .gpio_func_sel = 1 },
+ { 0xff },
+};
+
+static const struct config_reg_layout_desc jhb100_per2pok_pinctrl_rl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 18,
+ .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 },
+ .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 },
+ .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 },
+ .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 },
+ .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 },
+ .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 },
+ .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 },
+ },
+ { 0xff },
+};
+
+static const struct starfive_pinctrl_regs jhb100_per2pok_pinctrl_regs = {
+ .func_sel = { .reg = 0x58, .width_per_pin = 2 },
+ .config = 0x04,
+ .output = 0x4c,
+ .output_en = 0x50,
+ .gpio_status = 0x54,
+ .irq_en = 0x60,
+ .irq_status = 0x64,
+ .irq_clr = 0x68,
+ .irq_trigger = 0x6c,
+ .irq_level = 0x70,
+ .irq_both_edge = 0x74,
+ .irq_edge = 0x78,
+};
+
+static const struct jhb100_pinctrl_func_maps jhb100_func_maps_per2pok[] = {
+ { .func = "can", .val = 1 },
+ { .func = "gpio", .val = 0,
+ .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER2POK_GPIO_D40) },
+ { .func = "gpio", .val = 1,
+ .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER2POK_GPIO_D48) },
+ { .func = "host0_port80", .val = 2 },
+ { .func = "host1_port80", .val = 3 },
+ { .func = "passthru", .val = 2,
+ .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER2POK_GPIO_D36) },
+ { .func = "passthru", .val = 1,
+ .max_pin = JHB100_FUNC_MAPS_MAX_PIN(PADNUM_PER2POK_GPIO_D40) },
+ { .func = "pwm", .val = 0 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_per2pok_pinctrl_info = {
+ .name = "jhb100-per2pok",
+ .pl_desc = jhb100_per2pok_pl_desc,
+ .crl_desc = jhb100_per2pok_pinctrl_rl_desc,
+ .regs = &jhb100_per2pok_pinctrl_regs,
+ .fmaps = jhb100_func_maps_per2pok,
+ .num_maps = ARRAY_SIZE(jhb100_func_maps_per2pok),
+};
+
+static const struct of_device_id jhb100_per2pok_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-per2pok-pinctrl",
+ .data = &jhb100_per2pok_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per2pok_pinctrl_of_match);
+
+static struct platform_driver jhb100_per2pok_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-per2pok-pinctrl",
+ .of_match_table = jhb100_per2pok_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_per2pok_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC Peripheral-2 Power OK domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 19/22] dt-bindings: pinctrl: Add starfive,jhb100-per3-pinctrl
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (17 preceding siblings ...)
2026-09-10 10:03 ` [PATCH v8 18/22] pinctrl: starfive: Add StarFive JHB100 per2pok controller driver Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 20/22] pinctrl: starfive: Add StarFive JHB100 per3 controller driver Changhuang Liang
` (2 subsequent siblings)
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl bindings for StarFive JHB100 SoC Peripheral-3(per3) pinctrl
controller.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../pinctrl/starfive,jhb100-per3-pinctrl.yaml | 166 ++++++++++++++++++
1 file changed, 166 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per3-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per3-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per3-pinctrl.yaml
new file mode 100644
index 000000000000..92093315ef15
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per3-pinctrl.yaml
@@ -0,0 +1,166 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per3-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 Peripheral-3 Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "per3" pinctrl domain.
+
+ The "per3" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO interrupt handling.
+
+ In the Peripheral-3 Pin Controller, there are 11 multi-function GPIO_PADs.
+ Each of them can be multiplexed to several peripherals through function
+ selection. Each iopad has a maximum of up to 2 functions - 0 and 1.
+ Function 0 is the default function which is generally the GPIO function.
+ Function 1 is the alternate function or peripheral signal that can be
+ routed to an iopad. The function selection can be carried out by writing
+ the function number to the iopad function select register.
+
+ Each iopad is configurable with parameters such as input-enable, internal
+ pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
+ debounce nanoseconds, power source.
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-per3-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges: true
+
+ gpio-line-names: true
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate, input debounce nanoseconds,
+ power-source and drive-strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ additionalProperties: false
+
+ properties:
+ pins:
+ description:
+ The list of IOs that properties in the pincfg node apply to.
+
+ function:
+ description:
+ A string containing the name of the function to mux for these
+ pins.
+ enum: [ gmac_mdio, gmac_rmii, gpio ]
+
+ bias-disable: true
+
+ bias-pull-down:
+ type: boolean
+
+ bias-pull-up:
+ type: boolean
+
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 4000, 8000, 12000 ]
+
+ input-debounce-ns:
+ minimum: 0
+ maximum: 10485680
+ description:
+ Debounce time in nanoseconds. The hardware counts in 80 ns
+ stages with a 17-bit counter, so the maximum is 10485680 ns.
+
+ input-disable: true
+
+ input-enable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ power-source:
+ enum: [ 1800, 2500, 3300 ]
+ description: I/O voltage in millivolt.
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow
+ 1: fast
+
+required:
+ - compatible
+ - reg
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_per3: pinctrl@11c42000 {
+ compatible = "starfive,jhb100-per3-pinctrl";
+ reg = <0x0 0x11c42000 0x0 0x1000>;
+ resets = <&per3crg 6>;
+ interrupts = <64>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per3 0 0 11>;
+ };
+ };
--
2.25.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 20/22] pinctrl: starfive: Add StarFive JHB100 per3 controller driver
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (18 preceding siblings ...)
2026-09-10 10:03 ` [PATCH v8 19/22] dt-bindings: pinctrl: Add starfive,jhb100-per3-pinctrl Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 21/22] riscv: dts: starfive: Add JHB100 pinctrl pad number header Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 22/22] riscv: dts: starfive: jhb100: Add pinctrl nodes Changhuang Liang
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl driver for StarFive JHB100 SoC Peripheral-3(per3) pinctrl
controller.
Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Alex Soo <yuklin.soo@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/pinctrl/starfive/Kconfig | 11 ++
drivers/pinctrl/starfive/Makefile | 1 +
.../starfive/pinctrl-starfive-jhb100-per3.c | 129 ++++++++++++++++++
3 files changed, 141 insertions(+)
create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per3.c
diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig
index 426be481a3fb..11bd429b45b7 100644
--- a/drivers/pinctrl/starfive/Kconfig
+++ b/drivers/pinctrl/starfive/Kconfig
@@ -100,6 +100,17 @@ config PINCTRL_STARFIVE_JHB100_PER2POK
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
+config PINCTRL_STARFIVE_JHB100_PER3
+ tristate "StarFive JHB100 SoC Peripheral-3 pinctrl and GPIO driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select PINCTRL_STARFIVE_JHB100
+ default ARCH_STARFIVE
+ help
+ Say yes here to support Peripheral-3 pin control on the StarFive JHB100 SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
+
config PINCTRL_STARFIVE_JHB100_SYS0
tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile
index 213002da9cdd..351fce524fec 100644
--- a/drivers/pinctrl/starfive/Makefile
+++ b/drivers/pinctrl/starfive/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER1) += pinctrl-starfive-jhb100-per1.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER2) += pinctrl-starfive-jhb100-per2.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER2POK) += pinctrl-starfive-jhb100-per2pok.o
+obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER3) += pinctrl-starfive-jhb100-per3.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o
obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per3.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per3.c
new file mode 100644
index 000000000000..24158d90f75d
--- /dev/null
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per3.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Pinctrl / GPIO driver for StarFive JHB100 SoC Peripheral-3 domain
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Alex Soo <yuklin.soo@starfivetech.com>
+ *
+ */
+
+#include <linux/platform_device.h>
+
+#include "pinctrl-starfive-jhb100.h"
+
+/* per3 pad numbers */
+#define PADNUM_PER3_GPIO_E0 0
+#define PADNUM_PER3_GPIO_E1 1
+#define PADNUM_PER3_GPIO_E2 2
+#define PADNUM_PER3_GPIO_E3 3
+#define PADNUM_PER3_GPIO_E4 4
+#define PADNUM_PER3_GPIO_E5 5
+#define PADNUM_PER3_GPIO_E6 6
+#define PADNUM_PER3_GPIO_E7 7
+#define PADNUM_PER3_GPIO_E8 8
+#define PADNUM_PER3_GPIO_E9 9
+#define PADNUM_PER3_GPIO_E10 10
+
+static const struct jhb100_pin_layout_desc jhb100_per3_pl_desc[] = {
+ { .pin_start = 0, .pin_cnt = 11, .name = "gpio", .gpio_func_sel = 0 },
+ { 0xff },
+};
+
+static const struct config_reg_layout_desc jhb100_per3_pinctrl_rl_desc[] = {
+ {
+ .pin_start = 0,
+ .pin_cnt = 2,
+ .fields[PAD_CFG_DRIVE_STRENGTH_2BIT] = { .shift = 0, .width = 2 },
+ .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 2, .width = 1 },
+ .fields[PAD_CFG_PULL_DOWN] = { .shift = 3, .width = 1 },
+ .fields[PAD_CFG_PULL_UP] = { .shift = 4, .width = 1 },
+ .fields[PAD_CFG_SLEW_RATE] = { .shift = 5, .width = 1 },
+ .fields[PAD_CFG_SCHMITT_TRIGGER_SELECT] = { .shift = 6, .width = 1 },
+ .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 },
+ },
+ {
+ .pin_start = 2,
+ .pin_cnt = 9,
+ .fields[PAD_CFG_INPUT_ENABLE] = { .shift = 0, .width = 1 },
+ .fields[PAD_CFG_SLEW_RATE] = { .shift = 1, .width = 1 },
+ .fields[PAD_CFG_VSEL] = { .shift = 2, .width = 2 },
+ .fields[PAD_CFG_DEBOUNCE_WIDTH] = { .shift = 15, .width = 17 },
+ },
+ { 0xff },
+};
+
+static const struct pinvref_desc pinvref_desc_per3[] = {
+ {
+ /* gpios */
+ .pin_grp = {
+ PADNUM_PER3_GPIO_E0,
+ PADNUM_PER3_GPIO_E1,
+ PADNUM_PER3_GPIO_E2,
+ PADNUM_PER3_GPIO_E3,
+ PADNUM_PER3_GPIO_E4,
+ PADNUM_PER3_GPIO_E5,
+ PADNUM_PER3_GPIO_E6,
+ PADNUM_PER3_GPIO_E7,
+ PADNUM_PER3_GPIO_E8,
+ PADNUM_PER3_GPIO_E9,
+ PADNUM_PER3_GPIO_E10
+ },
+ .num_pins = 11,
+ .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_2_5V) |
+ BIT(JHB100_PINVREF_3_3V)
+ },
+};
+
+static const struct starfive_pinctrl_regs jhb100_per3_pinctrl_regs = {
+ .vref = { .reg = 0x00, .pv_desc = pinvref_desc_per3,
+ .num_pv = ARRAY_SIZE(pinvref_desc_per3) },
+ .func_sel = { .reg = 0x3c, .width_per_pin = 2 },
+ .config = 0x04,
+ .output = 0x30,
+ .output_en = 0x34,
+ .gpio_status = 0x38,
+ .irq_en = 0x40,
+ .irq_status = 0x44,
+ .irq_clr = 0x48,
+ .irq_trigger = 0x4c,
+ .irq_level = 0x50,
+ .irq_both_edge = 0x54,
+ .irq_edge = 0x58,
+};
+
+static const struct jhb100_pinctrl_func_maps jhb100_func_maps_per3[] = {
+ { .func = "gmac_mdio", .val = 1 },
+ { .func = "gmac_rmii", .val = 1 },
+ { .func = "gpio", .val = 0 },
+};
+
+static const struct jhb100_pinctrl_domain_info jhb100_per3_pinctrl_info = {
+ .name = "jhb100-per3",
+ .pl_desc = jhb100_per3_pl_desc,
+ .crl_desc = jhb100_per3_pinctrl_rl_desc,
+ .regs = &jhb100_per3_pinctrl_regs,
+ .fmaps = jhb100_func_maps_per3,
+ .num_maps = ARRAY_SIZE(jhb100_func_maps_per3),
+};
+
+static const struct of_device_id jhb100_per3_pinctrl_of_match[] = {
+ {
+ .compatible = "starfive,jhb100-per3-pinctrl",
+ .data = &jhb100_per3_pinctrl_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_per3_pinctrl_of_match);
+
+static struct platform_driver jhb100_per3_pinctrl_driver = {
+ .probe = jhb100_pinctrl_probe,
+ .driver = {
+ .name = "starfive-jhb100-per3-pinctrl",
+ .of_match_table = jhb100_per3_pinctrl_of_match,
+ },
+};
+module_platform_driver(jhb100_per3_pinctrl_driver);
+
+MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC Peripheral-3 domain");
+MODULE_AUTHOR("Alex Soo <yuklin.soo@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 21/22] riscv: dts: starfive: Add JHB100 pinctrl pad number header
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (19 preceding siblings ...)
2026-09-10 10:03 ` [PATCH v8 20/22] pinctrl: starfive: Add StarFive JHB100 per3 controller driver Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
2026-09-10 10:03 ` [PATCH v8 22/22] riscv: dts: starfive: jhb100: Add pinctrl nodes Changhuang Liang
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add the pad number definitions used by the JHB100 pinctrl device tree
nodes. The pad numbers are a property of the SoC pin controllers and are
only consumed by the StarFive JHB100 device trees.
Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
MAINTAINERS | 1 +
.../dts/starfive/starfive,jhb100-pinctrl.h | 247 ++++++++++++++++++
2 files changed, 248 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/starfive,jhb100-pinctrl.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 08201752d14a..f1a867babf85 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25903,6 +25903,7 @@ M: Changhuang Liang <changhuang.liang@starfivetech.com>
L: linux-riscv@lists.infradead.org
S: Supported
F: arch/riscv/boot/dts/starfive/jhb100*
+F: arch/riscv/boot/dts/starfive/starfive,jhb100-pinctrl.h
STARFIVE JHB100 EXTERNAL INTERRUPT CONTROLLER DRIVER
M: Changhuang Liang <changhuang.liang@starfivetech.com>
diff --git a/arch/riscv/boot/dts/starfive/starfive,jhb100-pinctrl.h b/arch/riscv/boot/dts/starfive/starfive,jhb100-pinctrl.h
new file mode 100644
index 000000000000..a645ddc836ff
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/starfive,jhb100-pinctrl.h
@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JHB100_H__
+#define __DT_BINDINGS_PINCTRL_STARFIVE_JHB100_H__
+
+/* sys0 pad numbers */
+#define PADNUM_SYS0_GPIO_A0 0
+#define PADNUM_SYS0_GPIO_A1 1
+#define PADNUM_SYS0_GPIO_A2 2
+#define PADNUM_SYS0_GPIO_A3 3
+
+/* sys0h pad numbers */
+#define PADNUM_SYS0H_GPIO_A4 0
+#define PADNUM_SYS0H_GPIO_A5 1
+#define PADNUM_SYS0H_GPIO_A6 2
+#define PADNUM_SYS0H_GPIO_A7 3
+#define PADNUM_SYS0H_GPIO_A8 4
+#define PADNUM_SYS0H_GPIO_A9 5
+#define PADNUM_SYS0H_GPIO_A10 6
+#define PADNUM_SYS0H_GPIO_A11 7
+#define PADNUM_SYS0H_GPIO_A12 8
+#define PADNUM_SYS0H_GPIO_A13 9
+#define PADNUM_SYS0H_GPIO_A14 10
+#define PADNUM_SYS0H_GPIO_A15 11
+
+/* sys1 pad numbers */
+#define PADNUM_SYS1_GPIO_A16 0
+#define PADNUM_SYS1_GPIO_A17 1
+#define PADNUM_SYS1_GPIO_A18 2
+#define PADNUM_SYS1_GPIO_A19 3
+#define PADNUM_SYS1_GPIO_A20 4
+#define PADNUM_SYS1_GPIO_A21 5
+#define PADNUM_SYS1_GPIO_A22 6
+#define PADNUM_SYS1_GPIO_A23 7
+
+/* sys2 pad numbers */
+#define PADNUM_SYS2_GPIO_A24 0
+#define PADNUM_SYS2_GPIO_A25 1
+#define PADNUM_SYS2_GPIO_A26 2
+#define PADNUM_SYS2_GPIO_A27 3
+#define PADNUM_SYS2_GPIO_A28 4
+#define PADNUM_SYS2_GPIO_A29 5
+#define PADNUM_SYS2_GPIO_A30 6
+#define PADNUM_SYS2_GPIO_A31 7
+#define PADNUM_SYS2_GPIO_A32 8
+#define PADNUM_SYS2_GPIO_A33 9
+#define PADNUM_SYS2_GPIO_A34 10
+#define PADNUM_SYS2_GPIO_A35 11
+#define PADNUM_SYS2_GPIO_A36 12
+#define PADNUM_SYS2_GPIO_A37 13
+#define PADNUM_SYS2_GPIO_A38 14
+#define PADNUM_SYS2_GPIO_A39 15
+#define PADNUM_SYS2_GPIO_A40 16
+#define PADNUM_SYS2_GPIO_A41 17
+#define PADNUM_SYS2_GPIO_A42 18
+#define PADNUM_SYS2_GPIO_A43 19
+#define PADNUM_SYS2_GPIO_A44 20
+#define PADNUM_SYS2_GPIO_A45 21
+#define PADNUM_SYS2_GPIO_A46 22
+#define PADNUM_SYS2_GPIO_A47 23
+#define PADNUM_SYS2_GPIO_A48 24
+#define PADNUM_SYS2_GPIO_A49 25
+#define PADNUM_SYS2_GPIO_A50 26
+#define PADNUM_SYS2_GPIO_A51 27
+#define PADNUM_SYS2_GPIO_A52 28
+#define PADNUM_SYS2_GPIO_A53 29
+#define PADNUM_SYS2_GPIO_A54 30
+#define PADNUM_SYS2_GPIO_A55 31
+#define PADNUM_SYS2_GPIO_A56 32
+#define PADNUM_SYS2_GPIO_A57 33
+#define PADNUM_SYS2_GPIO_A58 34
+#define PADNUM_SYS2_GPIO_A59 35
+#define PADNUM_SYS2_GPIO_A60 36
+
+/* per0 pad numbers */
+#define PADNUM_PER0_GPIO_B0 0
+#define PADNUM_PER0_GPIO_B1 1
+#define PADNUM_PER0_GPIO_B2 2
+#define PADNUM_PER0_GPIO_B3 3
+#define PADNUM_PER0_GPIO_B4 4
+#define PADNUM_PER0_GPIO_B5 5
+#define PADNUM_PER0_GPIO_B6 6
+#define PADNUM_PER0_GPIO_B7 7
+#define PADNUM_PER0_GPIO_B8 8
+#define PADNUM_PER0_GPIO_B9 9
+#define PADNUM_PER0_GPIO_B10 10
+#define PADNUM_PER0_GPIO_B11 11
+#define PADNUM_PER0_GPIO_B12 12
+#define PADNUM_PER0_GPIO_B13 13
+#define PADNUM_PER0_GPIO_B14 14
+#define PADNUM_PER0_GPIO_B15 15
+#define PADNUM_PER0_GPIO_B16 16
+#define PADNUM_PER0_GPIO_B17 17
+#define PADNUM_PER0_GPIO_B18 18
+#define PADNUM_PER0_GPIO_B19 19
+#define PADNUM_PER0_GPIO_B20 20
+#define PADNUM_PER0_GPIO_B21 21
+#define PADNUM_PER0_GPIO_B22 22
+#define PADNUM_PER0_GPIO_B23 23
+#define PADNUM_PER0_GPIO_B24 24
+#define PADNUM_PER0_GPIO_B25 25
+#define PADNUM_PER0_GPIO_B26 26
+#define PADNUM_PER0_GPIO_B27 27
+#define PADNUM_PER0_GPIO_B28 28
+#define PADNUM_PER0_GPIO_B29 29
+#define PADNUM_PER0_GPIO_B30 30
+#define PADNUM_PER0_GPIO_B31 31
+#define PADNUM_PER0_GPIO_B32 32
+#define PADNUM_PER0_GPIO_B33 33
+#define PADNUM_PER0_GPIO_B34 34
+#define PADNUM_PER0_GPIO_B35 35
+#define PADNUM_PER0_GPIO_B36 36
+#define PADNUM_PER0_GPIO_B37 37
+#define PADNUM_PER0_GPIO_B38 38
+#define PADNUM_PER0_GPIO_B39 39
+#define PADNUM_PER0_GPIO_B40 40
+#define PADNUM_PER0_GPIO_B41 41
+#define PADNUM_PER0_GPIO_B42 42
+#define PADNUM_PER0_GPIO_B43 43
+#define PADNUM_PER0_GPIO_B44 44
+#define PADNUM_PER0_GPIO_B45 45
+#define PADNUM_PER0_GPIO_B46 46
+#define PADNUM_PER0_GPIO_B47 47
+#define PADNUM_PER0_GPIO_B48 48
+#define PADNUM_PER0_GPIO_B49 49
+#define PADNUM_PER0_GPIO_B50 50
+#define PADNUM_PER0_GPIO_B51 51
+#define PADNUM_PER0_GPIO_B52 52
+#define PADNUM_PER0_GPIO_B53 53
+#define PADNUM_PER0_GPIO_B54 54
+#define PADNUM_PER0_GPIO_B55 55
+#define PADNUM_PER0_GPIO_B56 56
+#define PADNUM_PER0_GPIO_B57 57
+#define PADNUM_PER0_GPIO_B58 58
+#define PADNUM_PER0_GPIO_B59 59
+
+/* per1 pad numbers */
+#define PADNUM_PER1_GPIO_C0 0
+#define PADNUM_PER1_GPIO_C1 1
+#define PADNUM_PER1_GPIO_C2 2
+#define PADNUM_PER1_GPIO_C3 3
+#define PADNUM_PER1_GPIO_C4 4
+#define PADNUM_PER1_GPIO_C5 5
+#define PADNUM_PER1_GPIO_C6 6
+#define PADNUM_PER1_GPIO_C7 7
+#define PADNUM_PER1_GPIO_C8 8
+#define PADNUM_PER1_GPIO_C9 9
+#define PADNUM_PER1_GPIO_C10 10
+#define PADNUM_PER1_GPIO_C11 11
+#define PADNUM_PER1_GPIO_C12 12
+#define PADNUM_PER1_GPIO_C13 13
+#define PADNUM_PER1_GPIO_C14 14
+#define PADNUM_PER1_GPIO_C15 15
+#define PADNUM_PER1_GPIO_C16 16
+#define PADNUM_PER1_GPIO_C17 17
+#define PADNUM_PER1_GPIO_C18 18
+#define PADNUM_PER1_GPIO_C19 19
+#define PADNUM_PER1_GPIO_C20 20
+#define PADNUM_PER1_GPIO_C21 21
+#define PADNUM_PER1_GPIO_C22 22
+#define PADNUM_PER1_GPIO_C23 23
+#define PADNUM_PER1_GPIO_C24 24
+#define PADNUM_PER1_GPIO_C25 25
+#define PADNUM_PER1_GPIO_C26 26
+#define PADNUM_PER1_GPIO_C27 27
+#define PADNUM_PER1_GPIO_C28 28
+#define PADNUM_PER1_GPIO_C29 29
+#define PADNUM_PER1_GPIO_C30 30
+#define PADNUM_PER1_GPIO_C31 31
+#define PADNUM_PER1_GPIO_C32 32
+#define PADNUM_PER1_GPIO_C33 33
+#define PADNUM_PER1_GPIO_C34 34
+#define PADNUM_PER1_GPIO_C35 35
+
+/* per2 pad numbers */
+#define PADNUM_PER2_GPIO_D0 0
+#define PADNUM_PER2_GPIO_D1 1
+#define PADNUM_PER2_GPIO_D2 2
+#define PADNUM_PER2_GPIO_D3 3
+#define PADNUM_PER2_GPIO_D4 4
+#define PADNUM_PER2_GPIO_D5 5
+#define PADNUM_PER2_GPIO_D6 6
+#define PADNUM_PER2_GPIO_D7 7
+#define PADNUM_PER2_GPIO_D8 8
+#define PADNUM_PER2_GPIO_D9 9
+#define PADNUM_PER2_GPIO_D10 10
+#define PADNUM_PER2_GPIO_D11 11
+#define PADNUM_PER2_GPIO_D12 12
+#define PADNUM_PER2_GPIO_D13 13
+#define PADNUM_PER2_GPIO_D14 14
+#define PADNUM_PER2_GPIO_D15 15
+#define PADNUM_PER2_GPIO_D16 16
+#define PADNUM_PER2_GPIO_D17 17
+#define PADNUM_PER2_GPIO_D18 18
+#define PADNUM_PER2_GPIO_D19 19
+#define PADNUM_PER2_GPIO_D20 20
+#define PADNUM_PER2_GPIO_D21 21
+#define PADNUM_PER2_GPIO_D22 22
+#define PADNUM_PER2_GPIO_D23 23
+#define PADNUM_PER2_GPIO_D24 24
+#define PADNUM_PER2_GPIO_D25 25
+#define PADNUM_PER2_GPIO_D26 26
+#define PADNUM_PER2_GPIO_D27 27
+#define PADNUM_PER2_GPIO_D28 28
+#define PADNUM_PER2_GPIO_D29 29
+#define PADNUM_PER2_GPIO_D30 30
+
+/* per2pok pad numbers */
+#define PADNUM_PER2POK_GPIO_D31 0
+#define PADNUM_PER2POK_GPIO_D32 1
+#define PADNUM_PER2POK_GPIO_D33 2
+#define PADNUM_PER2POK_GPIO_D34 3
+#define PADNUM_PER2POK_GPIO_D35 4
+#define PADNUM_PER2POK_GPIO_D36 5
+#define PADNUM_PER2POK_GPIO_D37 6
+#define PADNUM_PER2POK_GPIO_D38 7
+#define PADNUM_PER2POK_GPIO_D39 8
+#define PADNUM_PER2POK_GPIO_D40 9
+#define PADNUM_PER2POK_GPIO_D41 10
+#define PADNUM_PER2POK_GPIO_D42 11
+#define PADNUM_PER2POK_GPIO_D43 12
+#define PADNUM_PER2POK_GPIO_D44 13
+#define PADNUM_PER2POK_GPIO_D45 14
+#define PADNUM_PER2POK_GPIO_D46 15
+#define PADNUM_PER2POK_GPIO_D47 16
+#define PADNUM_PER2POK_GPIO_D48 17
+
+/* per3 pad numbers */
+#define PADNUM_PER3_GPIO_E0 0
+#define PADNUM_PER3_GPIO_E1 1
+#define PADNUM_PER3_GPIO_E2 2
+#define PADNUM_PER3_GPIO_E3 3
+#define PADNUM_PER3_GPIO_E4 4
+#define PADNUM_PER3_GPIO_E5 5
+#define PADNUM_PER3_GPIO_E6 6
+#define PADNUM_PER3_GPIO_E7 7
+#define PADNUM_PER3_GPIO_E8 8
+#define PADNUM_PER3_GPIO_E9 9
+#define PADNUM_PER3_GPIO_E10 10
+#define PADNUM_PER3_GPIO_E11 11
+
+#endif
--
2.25.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v8 22/22] riscv: dts: starfive: jhb100: Add pinctrl nodes
2026-09-10 10:03 [PATCH v8 00/22] Add basic pinctrl drivers for JHB100 SoC Changhuang Liang
` (20 preceding siblings ...)
2026-09-10 10:03 ` [PATCH v8 21/22] riscv: dts: starfive: Add JHB100 pinctrl pad number header Changhuang Liang
@ 2026-09-10 10:03 ` Changhuang Liang
21 siblings, 0 replies; 23+ messages in thread
From: Changhuang Liang @ 2026-09-10 10:03 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Emil Renner Berthing, Paul Walmsley, Albert Ou, Palmer Dabbelt,
Alexandre Ghiti, Philipp Zabel, Bartosz Golaszewski
Cc: linux-gpio, linux-kernel, devicetree, linux-riscv,
Lianfeng Ouyang, Changhuang Liang
Add pinctrl nodes for starfive JHB100 SoC. They contain
pinctrl_per0/pinctrl_per1/pinctrl_per2/pinctrl_per2pok/pinctrl_per3/
pinctrl_sys0/pinctrl_sys0h/pinctrl_sys1/pinctrl_sys2.
Simultaneously add the pinctrl reference for uart6.
Co-developed-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jhb100-evb1.dts | 3 +
.../boot/dts/starfive/jhb100-pinctrl.dtsi | 23 ++++
arch/riscv/boot/dts/starfive/jhb100.dtsi | 107 ++++++++++++++++++
3 files changed, 133 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi
diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1.dts b/arch/riscv/boot/dts/starfive/jhb100-evb1.dts
index 462b6fb7953b..8ad2b30a4e0b 100644
--- a/arch/riscv/boot/dts/starfive/jhb100-evb1.dts
+++ b/arch/riscv/boot/dts/starfive/jhb100-evb1.dts
@@ -4,6 +4,7 @@
*/
#include "jhb100.dtsi"
+#include "jhb100-pinctrl.dtsi"
/ {
model = "StarFive JHB100 EVB-1";
@@ -29,4 +30,6 @@ memory@40000000 {
&uart6 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart6_pins>;
};
diff --git a/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi b/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi
new file mode 100644
index 000000000000..45fbef398a9e
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2025-2026 StarFive Technology Co., Ltd.
+ */
+
+#include "starfive,jhb100-pinctrl.h"
+
+&pinctrl_sys2 {
+ uart6_pins: uart6-grp {
+ uart6-tx-pins {
+ pins = <PADNUM_SYS2_GPIO_A38>;
+ function = "uart";
+ power-source = <3300>;
+ };
+
+ uart6-rx-pins {
+ pins = <PADNUM_SYS2_GPIO_A39>;
+ function = "uart";
+ input-enable;
+ power-source = <3300>;
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
index 943324b3b2fd..ecd952084535 100644
--- a/arch/riscv/boot/dts/starfive/jhb100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
@@ -428,6 +428,18 @@ per0crg: clock-controller@11a08000 {
#reset-cells = <1>;
};
+ pinctrl_per0: pinctrl@11a0a000 {
+ compatible = "starfive,jhb100-per0-pinctrl";
+ reg = <0x0 0x11a0a000 0x0 0x1000>;
+ resets = <&per0crg JHB100_PER0RST_GPIO_IOMUX_PRESETN>;
+ interrupts = <60>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per0 0 0 60>;
+ };
+
per1crg: clock-controller@11b40000 {
compatible = "starfive,jhb100-per1crg";
reg = <0x0 0x11b40000 0x0 0x1000>;
@@ -443,6 +455,18 @@ per1crg: clock-controller@11b40000 {
#reset-cells = <1>;
};
+ pinctrl_per1: pinctrl@11b42000 {
+ compatible = "starfive,jhb100-per1-pinctrl";
+ reg = <0x0 0x11b42000 0x0 0x800>;
+ resets = <&per1crg JHB100_PER1RST_IOMUX_PRESETN>;
+ interrupts = <61>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per1 0 0 36>;
+ };
+
per2crg: clock-controller@11bc0000 {
compatible = "starfive,jhb100-per2crg";
reg = <0x0 0x11bc0000 0x0 0x1000>;
@@ -464,6 +488,30 @@ per2crg: clock-controller@11bc0000 {
#reset-cells = <1>;
};
+ pinctrl_per2: pinctrl@11bc2000 {
+ compatible = "starfive,jhb100-per2-pinctrl";
+ reg = <0x0 0x11bc2000 0x0 0x400>;
+ resets = <&per2crg JHB100_PER2RST_IOMUX_PRESETN>;
+ interrupts = <62>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per2 0 0 31>;
+ };
+
+ pinctrl_per2pok: pinctrl@11bc2400 {
+ compatible = "starfive,jhb100-per2pok-pinctrl";
+ reg = <0x0 0x11bc2400 0x0 0x400>;
+ resets = <&per2crg JHB100_PER2RST_POK_IOMUX_PRESETN>;
+ interrupts = <63>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per2pok 0 0 18>;
+ };
+
per3crg: clock-controller@11c40000 {
compatible = "starfive,jhb100-per3crg";
reg = <0x0 0x11c40000 0x0 0x1000>;
@@ -483,6 +531,18 @@ per3crg: clock-controller@11c40000 {
#reset-cells = <1>;
};
+ pinctrl_per3: pinctrl@11c42000 {
+ compatible = "starfive,jhb100-per3-pinctrl";
+ reg = <0x0 0x11c42000 0x0 0x1000>;
+ resets = <&per3crg JHB100_PER3RST_IOMUX_PRESETN>;
+ interrupts = <64>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_per3 0 0 11>;
+ };
+
sys0crg: clock-controller@13000000 {
compatible = "starfive,jhb100-sys0crg";
reg = <0x0 0x13000000 0x0 0x4000>;
@@ -517,6 +577,53 @@ sys2crg: clock-controller@13008000 {
#reset-cells = <1>;
};
+ pinctrl_sys0: pinctrl@13080000 {
+ compatible = "starfive,jhb100-sys0-pinctrl";
+ reg = <0x0 0x13080000 0x0 0x800>;
+ resets = <&sys0crg JHB100_SYS0RST_SYS0_IOMUX_PRESETN>;
+ interrupts = <56>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_sys0 0 0 4>;
+ };
+
+ pinctrl_sys0h: pinctrl@13080800 {
+ compatible = "starfive,jhb100-sys0h-pinctrl";
+ reg = <0x0 0x13080800 0x0 0x800>;
+ resets = <&sys0crg JHB100_SYS0RST_SYS0H_IOMUX_PRESETN>;
+ interrupts = <57>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_sys0h 0 0 12>;
+ };
+
+ pinctrl_sys1: pinctrl@13081000 {
+ compatible = "starfive,jhb100-sys1-pinctrl";
+ reg = <0x0 0x13081000 0x0 0x1000>;
+ resets = <&sys1crg JHB100_SYS1RST_SYS1_IOMUX_PRESETN>;
+ interrupts = <58>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_sys1 0 0 8>;
+ };
+
+ pinctrl_sys2: pinctrl@13082000 {
+ compatible = "starfive,jhb100-sys2-pinctrl";
+ reg = <0x0 0x13082000 0x0 0x1000>;
+ interrupts = <59>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_sys2 0 0 37>;
+ };
+
intc: interrupt-controller@13220000 {
compatible = "starfive,jhb100-intc";
reg = <0x0 0x13220000 0x0 0x80>;
--
2.25.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread