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From: Pu Lehui <pulehui@huawei.com>
To: Peilin Ye <yepeilin@google.com>, <bpf@vger.kernel.org>
Cc: "Andrea Parri" <parri.andrea@gmail.com>,
	linux-riscv@lists.infradead.org, "Björn Töpel" <bjorn@kernel.org>,
	"Puranjay Mohan" <puranjay@kernel.org>,
	"Alexei Starovoitov" <ast@kernel.org>,
	"Daniel Borkmann" <daniel@iogearbox.net>,
	"Andrii Nakryiko" <andrii@kernel.org>,
	"Martin KaFai Lau" <martin.lau@linux.dev>,
	"Eduard Zingerman" <eddyz87@gmail.com>,
	"Paul E. McKenney" <paulmck@kernel.org>,
	"Song Liu" <song@kernel.org>,
	"Yonghong Song" <yonghong.song@linux.dev>,
	"John Fastabend" <john.fastabend@gmail.com>,
	"KP Singh" <kpsingh@kernel.org>,
	"Stanislav Fomichev" <sdf@fomichev.me>,
	"Hao Luo" <haoluo@google.com>, "Jiri Olsa" <jolsa@kernel.org>,
	"Luke Nelson" <luke.r.nels@gmail.com>,
	"Xi Wang" <xi.wang@gmail.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Alexandre Ghiti" <alex@ghiti.fr>,
	"Mykola Lysenko" <mykolal@fb.com>,
	"Shuah Khan" <shuah@kernel.org>, "Josh Don" <joshdon@google.com>,
	"Barret Rhoden" <brho@google.com>,
	"Neel Natu" <neelnatu@google.com>,
	"Benjamin Segall" <bsegall@google.com>
Subject: Re: [PATCH bpf-next 2/8] bpf, riscv64: Introduce emit_load_*() and emit_store_*()
Date: Wed, 30 Apr 2025 11:48:15 +0800	[thread overview]
Message-ID: <4b79abf9-7eb9-4530-b226-456c73f26b6b@huawei.com> (raw)
In-Reply-To: <3fd92afabeb9ed92a513b2c0aac091b69dbb76aa.1745970908.git.yepeilin@google.com>

On 2025/4/30 8:50, Peilin Ye wrote:
> From: Andrea Parri <parri.andrea@gmail.com>
> 
> We're planning to add support for the load-acquire and store-release
> BPF instructions.  Define emit_load_<size>() and emit_store_<size>()
> to enable/facilitate the (re)use of their code.
> 
> Tested-by: Peilin Ye <yepeilin@google.com>
> Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
> [yepeilin@google.com: cosmetic change to commit title]
> Signed-off-by: Peilin Ye <yepeilin@google.com>
> ---
>   arch/riscv/net/bpf_jit_comp64.c | 242 +++++++++++++++++++-------------
>   1 file changed, 143 insertions(+), 99 deletions(-)
> 
> diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
> index ca60db75199d..953b6a20c69f 100644
> --- a/arch/riscv/net/bpf_jit_comp64.c
> +++ b/arch/riscv/net/bpf_jit_comp64.c
> @@ -473,6 +473,140 @@ static inline void emit_kcfi(u32 hash, struct rv_jit_context *ctx)
>   		emit(hash, ctx);
>   }
>   
> +static int emit_load_8(bool sign_ext, u8 rd, s32 off, u8 rs, struct rv_jit_context *ctx)
> +{
> +	int insns_start;
> +
> +	if (is_12b_int(off)) {
> +		insns_start = ctx->ninsns;
> +		if (sign_ext)
> +			emit(rv_lb(rd, off, rs), ctx);
> +		else
> +			emit(rv_lbu(rd, off, rs), ctx);
> +		return ctx->ninsns - insns_start;
> +	}
> +
> +	emit_imm(RV_REG_T1, off, ctx);
> +	emit_add(RV_REG_T1, RV_REG_T1, rs, ctx);
> +	insns_start = ctx->ninsns;
> +	if (sign_ext)
> +		emit(rv_lb(rd, 0, RV_REG_T1), ctx);
> +	else
> +		emit(rv_lbu(rd, 0, RV_REG_T1), ctx);
> +	return ctx->ninsns - insns_start;
> +}
> +
> +static int emit_load_16(bool sign_ext, u8 rd, s32 off, u8 rs, struct rv_jit_context *ctx)
> +{
> +	int insns_start;
> +
> +	if (is_12b_int(off)) {
> +		insns_start = ctx->ninsns;
> +		if (sign_ext)
> +			emit(rv_lh(rd, off, rs), ctx);
> +		else
> +			emit(rv_lhu(rd, off, rs), ctx);
> +		return ctx->ninsns - insns_start;
> +	}
> +
> +	emit_imm(RV_REG_T1, off, ctx);
> +	emit_add(RV_REG_T1, RV_REG_T1, rs, ctx);
> +	insns_start = ctx->ninsns;
> +	if (sign_ext)
> +		emit(rv_lh(rd, 0, RV_REG_T1), ctx);
> +	else
> +		emit(rv_lhu(rd, 0, RV_REG_T1), ctx);
> +	return ctx->ninsns - insns_start;
> +}
> +
> +static int emit_load_32(bool sign_ext, u8 rd, s32 off, u8 rs, struct rv_jit_context *ctx)
> +{
> +	int insns_start;
> +
> +	if (is_12b_int(off)) {
> +		insns_start = ctx->ninsns;
> +		if (sign_ext)
> +			emit(rv_lw(rd, off, rs), ctx);
> +		else
> +			emit(rv_lwu(rd, off, rs), ctx);
> +		return ctx->ninsns - insns_start;
> +	}
> +
> +	emit_imm(RV_REG_T1, off, ctx);
> +	emit_add(RV_REG_T1, RV_REG_T1, rs, ctx);
> +	insns_start = ctx->ninsns;
> +	if (sign_ext)
> +		emit(rv_lw(rd, 0, RV_REG_T1), ctx);
> +	else
> +		emit(rv_lwu(rd, 0, RV_REG_T1), ctx);
> +	return ctx->ninsns - insns_start;
> +}
> +
> +static int emit_load_64(bool sign_ext, u8 rd, s32 off, u8 rs, struct rv_jit_context *ctx)
> +{
> +	int insns_start;
> +
> +	if (is_12b_int(off)) {
> +		insns_start = ctx->ninsns;
> +		emit_ld(rd, off, rs, ctx);
> +		return ctx->ninsns - insns_start;
> +	}
> +
> +	emit_imm(RV_REG_T1, off, ctx);
> +	emit_add(RV_REG_T1, RV_REG_T1, rs, ctx);
> +	insns_start = ctx->ninsns;
> +	emit_ld(rd, 0, RV_REG_T1, ctx);
> +	return ctx->ninsns - insns_start;
> +}
> +
> +static void emit_store_8(u8 rd, s32 off, u8 rs, struct rv_jit_context *ctx)
> +{
> +	if (is_12b_int(off)) {
> +		emit(rv_sb(rd, off, rs), ctx);
> +		return;
> +	}
> +
> +	emit_imm(RV_REG_T1, off, ctx);
> +	emit_add(RV_REG_T1, RV_REG_T1, rd, ctx);
> +	emit(rv_sb(RV_REG_T1, 0, rs), ctx);
> +}
> +
> +static void emit_store_16(u8 rd, s32 off, u8 rs, struct rv_jit_context *ctx)
> +{
> +	if (is_12b_int(off)) {
> +		emit(rv_sh(rd, off, rs), ctx);
> +		return;
> +	}
> +
> +	emit_imm(RV_REG_T1, off, ctx);
> +	emit_add(RV_REG_T1, RV_REG_T1, rd, ctx);
> +	emit(rv_sh(RV_REG_T1, 0, rs), ctx);
> +}
> +
> +static void emit_store_32(u8 rd, s32 off, u8 rs, struct rv_jit_context *ctx)
> +{
> +	if (is_12b_int(off)) {
> +		emit_sw(rd, off, rs, ctx);
> +		return;
> +	}
> +
> +	emit_imm(RV_REG_T1, off, ctx);
> +	emit_add(RV_REG_T1, RV_REG_T1, rd, ctx);
> +	emit_sw(RV_REG_T1, 0, rs, ctx);
> +}
> +
> +static void emit_store_64(u8 rd, s32 off, u8 rs, struct rv_jit_context *ctx)
> +{
> +	if (is_12b_int(off)) {
> +		emit_sd(rd, off, rs, ctx);
> +		return;
> +	}
> +
> +	emit_imm(RV_REG_T1, off, ctx);
> +	emit_add(RV_REG_T1, RV_REG_T1, rd, ctx);
> +	emit_sd(RV_REG_T1, 0, rs, ctx);
> +}
> +
>   static void emit_atomic(u8 rd, u8 rs, s16 off, s32 imm, bool is64,
>   			struct rv_jit_context *ctx)
>   {
> @@ -1650,8 +1784,8 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
>   	case BPF_LDX | BPF_PROBE_MEM32 | BPF_W:
>   	case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW:
>   	{
> -		int insn_len, insns_start;
>   		bool sign_ext;
> +		int insn_len;
>   
>   		sign_ext = BPF_MODE(insn->code) == BPF_MEMSX ||
>   			   BPF_MODE(insn->code) == BPF_PROBE_MEMSX;
> @@ -1663,78 +1797,16 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
>   
>   		switch (BPF_SIZE(code)) {
>   		case BPF_B:
> -			if (is_12b_int(off)) {
> -				insns_start = ctx->ninsns;
> -				if (sign_ext)
> -					emit(rv_lb(rd, off, rs), ctx);
> -				else
> -					emit(rv_lbu(rd, off, rs), ctx);
> -				insn_len = ctx->ninsns - insns_start;
> -				break;
> -			}
> -
> -			emit_imm(RV_REG_T1, off, ctx);
> -			emit_add(RV_REG_T1, RV_REG_T1, rs, ctx);
> -			insns_start = ctx->ninsns;
> -			if (sign_ext)
> -				emit(rv_lb(rd, 0, RV_REG_T1), ctx);
> -			else
> -				emit(rv_lbu(rd, 0, RV_REG_T1), ctx);
> -			insn_len = ctx->ninsns - insns_start;
> +			insn_len = emit_load_8(sign_ext, rd, off, rs, ctx);
>   			break;
>   		case BPF_H:
> -			if (is_12b_int(off)) {
> -				insns_start = ctx->ninsns;
> -				if (sign_ext)
> -					emit(rv_lh(rd, off, rs), ctx);
> -				else
> -					emit(rv_lhu(rd, off, rs), ctx);
> -				insn_len = ctx->ninsns - insns_start;
> -				break;
> -			}
> -
> -			emit_imm(RV_REG_T1, off, ctx);
> -			emit_add(RV_REG_T1, RV_REG_T1, rs, ctx);
> -			insns_start = ctx->ninsns;
> -			if (sign_ext)
> -				emit(rv_lh(rd, 0, RV_REG_T1), ctx);
> -			else
> -				emit(rv_lhu(rd, 0, RV_REG_T1), ctx);
> -			insn_len = ctx->ninsns - insns_start;
> +			insn_len = emit_load_16(sign_ext, rd, off, rs, ctx);
>   			break;
>   		case BPF_W:
> -			if (is_12b_int(off)) {
> -				insns_start = ctx->ninsns;
> -				if (sign_ext)
> -					emit(rv_lw(rd, off, rs), ctx);
> -				else
> -					emit(rv_lwu(rd, off, rs), ctx);
> -				insn_len = ctx->ninsns - insns_start;
> -				break;
> -			}
> -
> -			emit_imm(RV_REG_T1, off, ctx);
> -			emit_add(RV_REG_T1, RV_REG_T1, rs, ctx);
> -			insns_start = ctx->ninsns;
> -			if (sign_ext)
> -				emit(rv_lw(rd, 0, RV_REG_T1), ctx);
> -			else
> -				emit(rv_lwu(rd, 0, RV_REG_T1), ctx);
> -			insn_len = ctx->ninsns - insns_start;
> +			insn_len = emit_load_32(sign_ext, rd, off, rs, ctx);
>   			break;
>   		case BPF_DW:
> -			if (is_12b_int(off)) {
> -				insns_start = ctx->ninsns;
> -				emit_ld(rd, off, rs, ctx);
> -				insn_len = ctx->ninsns - insns_start;
> -				break;
> -			}
> -
> -			emit_imm(RV_REG_T1, off, ctx);
> -			emit_add(RV_REG_T1, RV_REG_T1, rs, ctx);
> -			insns_start = ctx->ninsns;
> -			emit_ld(rd, 0, RV_REG_T1, ctx);
> -			insn_len = ctx->ninsns - insns_start;
> +			insn_len = emit_load_64(sign_ext, rd, off, rs, ctx);
>   			break;
>   		}
>   
> @@ -1879,44 +1951,16 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
>   
>   	/* STX: *(size *)(dst + off) = src */
>   	case BPF_STX | BPF_MEM | BPF_B:
> -		if (is_12b_int(off)) {
> -			emit(rv_sb(rd, off, rs), ctx);
> -			break;
> -		}
> -
> -		emit_imm(RV_REG_T1, off, ctx);
> -		emit_add(RV_REG_T1, RV_REG_T1, rd, ctx);
> -		emit(rv_sb(RV_REG_T1, 0, rs), ctx);
> +		emit_store_8(rd, off, rs, ctx);
>   		break;
>   	case BPF_STX | BPF_MEM | BPF_H:
> -		if (is_12b_int(off)) {
> -			emit(rv_sh(rd, off, rs), ctx);
> -			break;
> -		}
> -
> -		emit_imm(RV_REG_T1, off, ctx);
> -		emit_add(RV_REG_T1, RV_REG_T1, rd, ctx);
> -		emit(rv_sh(RV_REG_T1, 0, rs), ctx);
> +		emit_store_16(rd, off, rs, ctx);
>   		break;
>   	case BPF_STX | BPF_MEM | BPF_W:
> -		if (is_12b_int(off)) {
> -			emit_sw(rd, off, rs, ctx);
> -			break;
> -		}
> -
> -		emit_imm(RV_REG_T1, off, ctx);
> -		emit_add(RV_REG_T1, RV_REG_T1, rd, ctx);
> -		emit_sw(RV_REG_T1, 0, rs, ctx);
> +		emit_store_32(rd, off, rs, ctx);
>   		break;
>   	case BPF_STX | BPF_MEM | BPF_DW:
> -		if (is_12b_int(off)) {
> -			emit_sd(rd, off, rs, ctx);
> -			break;
> -		}
> -
> -		emit_imm(RV_REG_T1, off, ctx);
> -		emit_add(RV_REG_T1, RV_REG_T1, rd, ctx);
> -		emit_sd(RV_REG_T1, 0, rs, ctx);
> +		emit_store_64(rd, off, rs, ctx);
>   		break;
>   	case BPF_STX | BPF_ATOMIC | BPF_W:
>   	case BPF_STX | BPF_ATOMIC | BPF_DW:

Reviewed-by: Pu Lehui <pulehui@huawei.com>

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linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2025-04-30  3:50 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-30  0:48 [PATCH bpf-next 0/8] bpf, riscv64: Support load-acquire and store-release instructions Peilin Ye
2025-04-30  0:50 ` [PATCH bpf-next 1/8] bpf/verifier: Handle BPF_LOAD_ACQ instructions in insn_def_regno() Peilin Ye
2025-05-06 14:03   ` Pu Lehui
2025-05-07  0:18     ` Peilin Ye
2025-04-30  0:50 ` [PATCH bpf-next 2/8] bpf, riscv64: Introduce emit_load_*() and emit_store_*() Peilin Ye
2025-04-30  3:48   ` Pu Lehui [this message]
2025-04-30  0:50 ` [PATCH bpf-next 3/8] bpf, riscv64: Support load-acquire and store-release instructions Peilin Ye
2025-04-30  3:48   ` Pu Lehui
2025-05-06 14:20   ` Pu Lehui
2025-05-07  0:23     ` Peilin Ye
2025-04-30  0:50 ` [PATCH bpf-next 4/8] bpf, riscv64: Skip redundant zext instruction after load-acquire Peilin Ye
2025-04-30  3:48   ` Pu Lehui
2025-04-30  0:51 ` [PATCH bpf-next 5/8] selftests/bpf: Use CAN_USE_LOAD_ACQ_STORE_REL when appropriate Peilin Ye
2025-05-06 14:22   ` Pu Lehui
2025-04-30  0:51 ` [PATCH bpf-next 6/8] selftests/bpf: Avoid passing out-of-range values to __retval() Peilin Ye
2025-05-06 14:23   ` Pu Lehui
2025-04-30  0:51 ` [PATCH bpf-next 7/8] selftests/bpf: Verify zero-extension behavior in load-acquire tests Peilin Ye
2025-05-06 14:23   ` Pu Lehui
2025-04-30  0:51 ` [PATCH bpf-next 8/8] selftests/bpf: Enable non-arena load-acquire/store-release selftests for riscv64 Peilin Ye
2025-05-06 14:23   ` Pu Lehui
2025-04-30  3:56 ` [PATCH bpf-next 0/8] bpf, riscv64: Support load-acquire and store-release instructions Pu Lehui
2025-04-30 19:47   ` Peilin Ye
2025-05-02 15:43 ` Björn Töpel
2025-05-03  1:03   ` Peilin Ye

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