Re: [PATCH bpf-next 3/8] bpf, riscv64: Support load-acquire and store-release instructions

From: Peilin Ye <yepeilin@google.com>
To: Pu Lehui <pulehui@huawei.com>
Cc: bpf@vger.kernel.org, "Andrea Parri" <parri.andrea@gmail.com>,
	linux-riscv@lists.infradead.org, "Björn Töpel" <bjorn@kernel.org>,
	"Puranjay Mohan" <puranjay@kernel.org>,
	"Alexei Starovoitov" <ast@kernel.org>,
	"Daniel Borkmann" <daniel@iogearbox.net>,
	"Andrii Nakryiko" <andrii@kernel.org>,
	"Martin KaFai Lau" <martin.lau@linux.dev>,
	"Eduard Zingerman" <eddyz87@gmail.com>,
	"Paul E. McKenney" <paulmck@kernel.org>,
	"Song Liu" <song@kernel.org>,
	"Yonghong Song" <yonghong.song@linux.dev>,
	"John Fastabend" <john.fastabend@gmail.com>,
	"KP Singh" <kpsingh@kernel.org>,
	"Stanislav Fomichev" <sdf@fomichev.me>,
	"Hao Luo" <haoluo@google.com>, "Jiri Olsa" <jolsa@kernel.org>,
	"Luke Nelson" <luke.r.nels@gmail.com>,
	"Xi Wang" <xi.wang@gmail.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Alexandre Ghiti" <alex@ghiti.fr>,
	"Mykola Lysenko" <mykolal@fb.com>,
	"Shuah Khan" <shuah@kernel.org>, "Josh Don" <joshdon@google.com>,
	"Barret Rhoden" <brho@google.com>,
	"Neel Natu" <neelnatu@google.com>,
	"Benjamin Segall" <bsegall@google.com>
Subject: Re: [PATCH bpf-next 3/8] bpf, riscv64: Support load-acquire and store-release instructions
Date: Wed, 7 May 2025 00:23:12 +0000	[thread overview]
Message-ID: <aBqn8C6Iz3tk6dAk@google.com> (raw)
In-Reply-To: <a50a1c64-683b-4356-99ec-103017f7a6be@huawei.com>

On Tue, May 06, 2025 at 10:20:04PM +0800, Pu Lehui wrote:
> On 2025/4/30 8:50, Peilin Ye wrote:
> > @@ -1259,7 +1318,7 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
> >   {
> >   	bool is64 = BPF_CLASS(insn->code) == BPF_ALU64 ||
> >   		    BPF_CLASS(insn->code) == BPF_JMP;
> > -	int s, e, rvoff, ret, i = insn - ctx->prog->insnsi;
> > +	int s, e, rvoff, ret = 0, i = insn - ctx->prog->insnsi;
> >   	struct bpf_prog_aux *aux = ctx->prog->aux;
> >   	u8 rd = -1, rs = -1, code = insn->code;
> >   	s16 off = insn->off;
> > @@ -1962,10 +2021,14 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
> >   	case BPF_STX | BPF_MEM | BPF_DW:
> >   		emit_store_64(rd, off, rs, ctx);
> >   		break;
> > +	case BPF_STX | BPF_ATOMIC | BPF_B:
> > +	case BPF_STX | BPF_ATOMIC | BPF_H:
> >   	case BPF_STX | BPF_ATOMIC | BPF_W:
> >   	case BPF_STX | BPF_ATOMIC | BPF_DW:
> > -		emit_atomic(rd, rs, off, imm,
> > -			    BPF_SIZE(code) == BPF_DW, ctx);
> > +		if (bpf_atomic_is_load_store(insn))
> > +			ret = emit_atomic_ld_st(rd, rs, off, imm, code, ctx);
> > +		else
> > +			ret = emit_atomic_rmw(rd, rs, off, imm, code, ctx);
> >   		break;
> >   	case BPF_STX | BPF_PROBE_MEM32 | BPF_B:
> > @@ -2050,7 +2113,7 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
> >   		return -EINVAL;
> >   	}
> > -	return 0;
> > +	return ret;
> 
> `ret` may be a value greater than zero, which will potentially cause
> build_body to skip the next instruction. Let's `return 0` here, and `return
> ret` if the above fails.

Sure, I'll change this in v2.

Thanks,
Peilin Ye

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