[GIT PULL] RISC-V Sophgo Devicetrees for v6.17

[Chen Wang <unicorn_wang@outlook.com>]

Hey Arnd,

Please pull this dt changes for RISC-V/Sophgo.

Thanks,

Chen

The following changes since commit 19272b37aa4f83ca52bdf9c16d5d81bdd1354494:

   Linux 6.16-rc1 (2025-06-08 13:44:43 -0700)

are available in the Git repository at:

   https://github.com/sophgo/linux.git tags/riscv-sophgo-dt-for-v6.17

for you to fetch changes up to 7f90573099e8a506a6874d691d884d7f5b77ec74:

   riscv: dts: sophgo: fix mdio node name for CV180X (2025-07-23 
09:55:16 +0800)

----------------------------------------------------------------
RISC-V Devicetrees for v6.17

Sophgo:

For CV18xx serials:
There are three major changes. The first is to add the
RTCSYS MFD node, which provides rich control registers
for soc power management and other rich control functions;
the second is to add the reset controller node and add
related reset properties for other peripherals; the third
is to add ethernet controller related nodes to the soc
and enable ethernet device control for HuashanPi.

For SG2042:
There are three major changes. The first is to add ISA
extensions such as xtheadvector/ziccrse/zfh for cpu cores;
the second is add ethernet controller support; the third
is add two new boards EVB_V1 & EVB_V2 which use SG2042
SoC.

For SG2044:
There are many changes. The first is to add pmu
configuration; the second is to add ISA extensions
ziccrse and add missing riscv,cbop-block-size property
for cpu cores; the third is to add more peripherals
nodes for SoC after clock controller is ready, such as
MSI/PCIe/pwm/SPI-NOR etc. This PR also add HWMON MCU
device for the sophgo-srd3-10 board and reserve uart0
node for sophgo-srd3-10 board because uart0 is already
occupied by the firmware.

This PR also moves sophgo.yaml from the riscv directory
to soc/sophgo for sharing between riscv and arm. CV18xx
SoC contains a RISC-V big core and an ARM64 big core.
Moving sophgo.yaml to a shared location will help us
add support for ARM cores to the CV18xx chip in the future.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

----------------------------------------------------------------
Alexander Sverdlin (2):
       riscv: dts: sophgo: cv18xx: Add RTCSYS device node
       dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, 
add SG2000

Han Gao (7):
       riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
       riscv: dts: sophgo: add ziccrse for sg2042
       riscv: dts: sophgo: add zfh for sg2042
       riscv: dts: sophgo: sg2044: add ziccrse extension
       dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings
       riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree
       riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree

Inochi Amaoto (21):
       riscv: dts: sophgo: sg2044: Add system controller device
       riscv: dts: sophgo: sg2044: Add clock controller device
       riscv: dts: sophgo: sg2044: Add GPIO device
       riscv: dts: sophgo: sg2044: Add I2C device
       riscv: dts: sophgo: sg2044: add DMA controller device
       riscv: dts: sophgo: sg2044: Add MMC controller device
       riscv: dts: sophgo: sophgo-srd3-10: add HWMON MCU device
       riscv: dts: sophgo: sg2044: Add ethernet control device
       riscv: dts: sophgo: sg2044: Add pinctrl device
       riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size 
property
       riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
       riscv: dts: sophgo: add reset configuration for Sophgo CV1800 
series SoC
       riscv: dts: sophgo: sg2044: add MSI device support for SG2044
       riscv: dts: sophgo: sg2044: add PCIe device support for SG2044
       riscv: dts: sophgo: sg2044: add pmu configuration
       riscv: dts: sophgo: Add ethernet device for cv18xx
       riscv: dts: sophgo: Add mdio multiplexer device for cv18xx
       riscv: dts: sophgo: Enable ethernet device for Huashan Pi
       riscv: dts: sophgo: add ethernet GMAC device for sg2042
       riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device
       riscv: dts: sophgo: fix mdio node name for CV180X

Longbin Li (2):
       riscv: dts: sophgo: add SG2044 SPI NOR controller driver
       riscv: dts: sophgo: add pwm controller for SG2044

  .../bindings/{riscv => soc/sophgo}/sophgo.yaml     |   9 +-
  arch/riscv/boot/dts/sophgo/Makefile                |   2 +
  arch/riscv/boot/dts/sophgo/cv180x.dtsi             | 110 +++++
  arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts  |   8 +
  arch/riscv/boot/dts/sophgo/cv18xx-reset.h          |  98 ++++
  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi        | 384 ++++++++++------
  arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts       | 245 ++++++++++
  arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts       | 233 ++++++++++
  arch/riscv/boot/dts/sophgo/sg2042.dtsi             |  61 +++
  arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi        | 283 +++++++++---
  .../boot/dts/sophgo/sg2044-sophgo-srd3-10.dts      |  87 ++++
  arch/riscv/boot/dts/sophgo/sg2044.dtsi             | 499 
+++++++++++++++++++++
  12 files changed, 1826 insertions(+), 193 deletions(-)
  rename Documentation/devicetree/bindings/{riscv => 
soc/sophgo}/sophgo.yaml (76%)
  create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-reset.h
  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts


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