[PATCH] RISC-V: Define pgprot_dmacoherent() for non-coherent devices

[PATCH] RISC-V: Define pgprot_dmacoherent() for non-coherent devices

[Anup Patel]

The pgprot_dmacoherent() is used when allocating memory for
non-coherent devices and by default pgprot_dmacoherent() is
same as pgprot_noncached() unless architecture overrides it.

Currently, there is no pgprot_dmacoherent() definition for
RISC-V hence non-coherent device memory is being mapped as
IO thereby making CPU access to such memory slow.

Define pgprot_dmacoherent() to be same as pgprot_writecombine()
for RISC-V so that CPU access non-coherent device memory as
NOCACHE which is better than accessing it as IO.

Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/include/asm/pgtable.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 91697fbf1f90..00d8bdaf1e8d 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -653,6 +653,8 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
 	return __pgprot(prot);
 }
 
+#define pgprot_dmacoherent pgprot_writecombine
+
 /*
  * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By
  * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in
-- 
2.43.0


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Re: [PATCH] RISC-V: Define pgprot_dmacoherent() for non-coherent devices

[Guo Ren]

On Wed, Aug 20, 2025 at 08:53:16PM +0530, Anup Patel wrote:
> The pgprot_dmacoherent() is used when allocating memory for
> non-coherent devices and by default pgprot_dmacoherent() is
> same as pgprot_noncached() unless architecture overrides it.
> 
> Currently, there is no pgprot_dmacoherent() definition for
> RISC-V hence non-coherent device memory is being mapped as
> IO thereby making CPU access to such memory slow.
> 
> Define pgprot_dmacoherent() to be same as pgprot_writecombine()
> for RISC-V so that CPU access non-coherent device memory as
> NOCACHE which is better than accessing it as IO.
> 
> Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support")
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  arch/riscv/include/asm/pgtable.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 91697fbf1f90..00d8bdaf1e8d 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -653,6 +653,8 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
>  	return __pgprot(prot);
>  }
>  
> +#define pgprot_dmacoherent pgprot_writecombine
I missed this patch and sent out a duplicate one [1]. Maybe the comments
from [1] could be appended to this one.

Tested-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org>

> +
>  /*
>   * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By
>   * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in
> -- 
> 2.43.0
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
> 

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Re: [PATCH] RISC-V: Define pgprot_dmacoherent() for non-coherent devices

[Guo Ren]

On Sun, Oct 12, 2025 at 02:07:34AM -0400, Guo Ren wrote:
> On Wed, Aug 20, 2025 at 08:53:16PM +0530, Anup Patel wrote:
> > The pgprot_dmacoherent() is used when allocating memory for
> > non-coherent devices and by default pgprot_dmacoherent() is
> > same as pgprot_noncached() unless architecture overrides it.
> > 
> > Currently, there is no pgprot_dmacoherent() definition for
> > RISC-V hence non-coherent device memory is being mapped as
> > IO thereby making CPU access to such memory slow.
> > 
> > Define pgprot_dmacoherent() to be same as pgprot_writecombine()
> > for RISC-V so that CPU access non-coherent device memory as
> > NOCACHE which is better than accessing it as IO.
> > 
> > Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support")
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > ---
> >  arch/riscv/include/asm/pgtable.h | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> > index 91697fbf1f90..00d8bdaf1e8d 100644
> > --- a/arch/riscv/include/asm/pgtable.h
> > +++ b/arch/riscv/include/asm/pgtable.h
> > @@ -653,6 +653,8 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
> >  	return __pgprot(prot);
> >  }
> >  
> > +#define pgprot_dmacoherent pgprot_writecombine
> I missed this patch and sent out a duplicate one [1]. Maybe the comments
> from [1] could be appended to this one.
[1]: https://lore.kernel.org/linux-riscv/20251011155746.1558731-1-guoren@kernel.org/

> 
> Tested-by: Guo Ren (Alibaba DAMO Academy) <guoren@kernel.org>
> 
> > +
> >  /*
> >   * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By
> >   * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in
> > -- 
> > 2.43.0
> > 
> > 
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
> > 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
> 

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Re: [PATCH] RISC-V: Define pgprot_dmacoherent() for non-coherent devices

[Han Gao (Revy)]

> On Aug 20, 2025, at 23:23, Anup Patel <apatel@ventanamicro.com> wrote:
> 
> The pgprot_dmacoherent() is used when allocating memory for
> non-coherent devices and by default pgprot_dmacoherent() is
> same as pgprot_noncached() unless architecture overrides it.
> 
> Currently, there is no pgprot_dmacoherent() definition for
> RISC-V hence non-coherent device memory is being mapped as
> IO thereby making CPU access to such memory slow.
> 
> Define pgprot_dmacoherent() to be same as pgprot_writecombine()
> for RISC-V so that CPU access non-coherent device memory as
> NOCACHE which is better than accessing it as IO.
> 
> Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support")
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Tested-by: Han Gao <rabenda.cn@gmail.com>
> ---
> arch/riscv/include/asm/pgtable.h | 2 ++
> 1 file changed, 2 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 91697fbf1f90..00d8bdaf1e8d 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -653,6 +653,8 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
> return __pgprot(prot);
> }
> 
> +#define pgprot_dmacoherent pgprot_writecombine
> +
> /*
>  * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By
>  * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in
> -- 
> 2.43.0
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
> 


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Re: [PATCH] RISC-V: Define pgprot_dmacoherent() for non-coherent devices

[patchwork-bot+linux-riscv]

Hello:

This patch was applied to riscv/linux.git (fixes)
by Paul Walmsley <pjw@kernel.org>:

On Wed, 20 Aug 2025 20:53:16 +0530 you wrote:
> The pgprot_dmacoherent() is used when allocating memory for
> non-coherent devices and by default pgprot_dmacoherent() is
> same as pgprot_noncached() unless architecture overrides it.
> 
> Currently, there is no pgprot_dmacoherent() definition for
> RISC-V hence non-coherent device memory is being mapped as
> IO thereby making CPU access to such memory slow.
> 
> [...]

Here is the summary with links:
  - RISC-V: Define pgprot_dmacoherent() for non-coherent devices
    https://git.kernel.org/riscv/c/ca525d53f994

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html



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Re: [PATCH] RISC-V: Define pgprot_dmacoherent() for non-coherent devices

[Vadim Akimov]

Hi,

On Wed, Aug 20, 2025 at 08:53:16PM +0530, Anup Patel wrote:

> The pgprot_dmacoherent() is used when allocating memory for
> non-coherent devices and by default pgprot_dmacoherent() is
> same as pgprot_noncached() unless architecture overrides it.
 
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 91697fbf1f90..00d8bdaf1e8d 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h

> +#define pgprot_dmacoherent pgprot_writecombine

This single-line patch, as implemented in commit 00b58d2c25d10fecffbebaa0c369fc9d0a6de397 for 6.6.y,
breaks allwinner D1 SDcard handling:

[    0.000000] Linux version 6.6.115 (surfin@nedoserver) (riscv64-unknown-linux-gnu-gcc () 11.3.0, GNU ld (GNU Binutils) 2.38) #1 Tue May  5 10:25:47 MSK 2026

[    4.886823] sunxi-mmc 4020000.mmc: Got CD GPIO
[    4.893625] sunxi-mmc 4021000.mmc: allocated mmc-pwrseq
[    4.941711] sunxi-mmc 4021000.mmc: initialized, max. request size: 2048 KB, uses new timings mode
[    4.958033] sunxi-mmc 4020000.mmc: initialized, max. request size: 2048 KB, uses new timings mode
[    4.990692] sunxi-mmc 4021000.mmc: card claims to support voltages below defined range
[    5.009712] mmc1: new high speed SDIO card at address 0001

then following never happens with that patch, i.e. no SD card is found.

#[    5.109896] mmc0: new high speed SDHC card at address 0001
#[    5.116546] mmcblk0: mmc0:0001 EB1QT 29.8 GiB
#[    5.128887]  mmcblk0: p1 p2


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