* [PATCH v1] riscv: irqflags: Conditionally enable interrupts in arch_local_irq_restore()
@ 2026-11-10 22:50 Andy Chiu
2026-11-11 4:05 ` Jisheng Zhang
0 siblings, 1 reply; 2+ messages in thread
From: Andy Chiu @ 2026-11-10 22:50 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-riscv
Cc: mpe, andybnac, Anton Blanchard, Nicholas Piggin, Andy Chiu,
dfustini, greentime.hu
From: Anton Blanchard <antonb@tenstorrent.com>
The Tenstorrent Ascalon core has an optimization that reduces pipeline
synchronisation for immediate writes of SIE. This optimization does not
work with register-based CSR writes, which occur when restoring flags in
arch_local_irq_restore().
Refactor arch_local_irq_restore() to conditionally call
arch_local_irq_enable() only when saved flags indicate interrupts were
enabled.
On a simple nginx benchmark serving a small static HTML file this patch
improves performance by 4%.
Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
Co-developed-by: Nicholas Piggin <npiggin@oss.tenstorrent.com>
Signed-off-by: Nicholas Piggin <npiggin@oss.tenstorrent.com>
Signed-off-by: Andy Chiu <tchiu@tenstorrent.com>
---
arch/riscv/include/asm/irqflags.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h
index 6fd8cbfcfcc7..5b1bca17bdc4 100644
--- a/arch/riscv/include/asm/irqflags.h
+++ b/arch/riscv/include/asm/irqflags.h
@@ -48,7 +48,8 @@ static inline int arch_irqs_disabled(void)
/* set interrupt enabled status */
static inline void arch_local_irq_restore(unsigned long flags)
{
- csr_set(CSR_STATUS, flags & SR_IE);
+ if (!arch_irqs_disabled_flags(flags))
+ arch_local_irq_enable();
}
#endif /* _ASM_RISCV_IRQFLAGS_H */
base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
--
2.43.0
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v1] riscv: irqflags: Conditionally enable interrupts in arch_local_irq_restore()
2026-11-10 22:50 [PATCH v1] riscv: irqflags: Conditionally enable interrupts in arch_local_irq_restore() Andy Chiu
@ 2026-11-11 4:05 ` Jisheng Zhang
0 siblings, 0 replies; 2+ messages in thread
From: Jisheng Zhang @ 2026-11-11 4:05 UTC (permalink / raw)
To: Andy Chiu
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-riscv, mpe, andybnac, Anton Blanchard, Nicholas Piggin,
dfustini, greentime.hu
On Tue, Nov 10, 2026 at 04:50:38PM -0600, Andy Chiu wrote:
> From: Anton Blanchard <antonb@tenstorrent.com>
>
> The Tenstorrent Ascalon core has an optimization that reduces pipeline
> synchronisation for immediate writes of SIE. This optimization does not
> work with register-based CSR writes, which occur when restoring flags in
> arch_local_irq_restore().
>
> Refactor arch_local_irq_restore() to conditionally call
> arch_local_irq_enable() only when saved flags indicate interrupts were
> enabled.
>
> On a simple nginx benchmark serving a small static HTML file this patch
> improves performance by 4%.
>
> Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
> Co-developed-by: Nicholas Piggin <npiggin@oss.tenstorrent.com>
> Signed-off-by: Nicholas Piggin <npiggin@oss.tenstorrent.com>
> Signed-off-by: Andy Chiu <tchiu@tenstorrent.com>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> arch/riscv/include/asm/irqflags.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h
> index 6fd8cbfcfcc7..5b1bca17bdc4 100644
> --- a/arch/riscv/include/asm/irqflags.h
> +++ b/arch/riscv/include/asm/irqflags.h
> @@ -48,7 +48,8 @@ static inline int arch_irqs_disabled(void)
> /* set interrupt enabled status */
> static inline void arch_local_irq_restore(unsigned long flags)
> {
> - csr_set(CSR_STATUS, flags & SR_IE);
> + if (!arch_irqs_disabled_flags(flags))
> + arch_local_irq_enable();
> }
>
> #endif /* _ASM_RISCV_IRQFLAGS_H */
>
> base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
> --
> 2.43.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
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