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From: Jiaxing Hu <gahing@gahingwoo.com>
To: royalnet026@gmail.com
Cc: tomeu@tomeuvizoso.net, heiko@sntech.de,
	chaoyi.chen@rock-chips.com, alchark@flipper.net,
	dri-devel@lists.freedesktop.org,
	linux-rockchip@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v7 08/10] accel/rocket: add RK3576 NPU (RKNN) support
Date: Sat, 22 Aug 2026 22:09:56 +1200	[thread overview]
Message-ID: <20260822100956.636407-1-gahing@gahingwoo.com> (raw)
In-Reply-To: <20260820185056.20643-1-royalnet026@gmail.com>

Hi Igor,

SIZE_E_1 stays at 0 and the diff stays as it is. Your reason is better than the
one I would have given: a register built from the trace with one field swapped
to upstream's value is a configuration nothing has ever run.

I crossed SIZE_E_1 with the channel count, seven values, with the control beside
each one in the same boot:

    N                      16   24   32   40   48   56   64
    SIZE_E_1 = 1  written  16   24   32   40   48   56   64
                  correct  16   24   32   40   48   56   64
    SIZE_E_1 = 0  written   8   24   32   40   48   56   64
                  correct   8   24   32   40   48   56   64

Six of the seven are identical. At N = 16 they are not: upstream's 0 asks for
sixteen channels and delivers eight, in both the words written and the count
that comes out correct.

So your conservative choice is right, and one shape in seven is what two shapes
could never have found.

Two corrections I owe you. The first version of this reply said I had not run
the cross sweep, and I had; the round is named after you. And I nearly handed
you an old floor(n/16)*16 shortfall as a possible SIZE_E_1 effect, but the
traced value writes all 24 at N = 24 in this round too, so that one belongs to
the channel count register and not to this field.

Separately, on the int4 path at 64 output channels, SIZE_E_2 moves the words the
block writes but not the channels it computes:

    SIZE_E_2       1    2    3
    words written  32   36   40

and the correct count stayed at 32 in all three. Additive in fours, not in
sixteens, which does not sit well with the semantics I sent you on the 17th. It
is a different register value on a different precision, so it does not refute
the reading for the path it was read from, and I am not going to pretend it
supports it either.

The re-run offer is noted and I will take it when v9 goes. Glad the trip was
fine, and I hope the countryside is treating the board well.

Regards,
Jiaxing

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  reply	other threads:[~2026-08-22 10:10 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-12  9:40 [PATCH v7 00/10] accel/rocket: RK3576 NPU (RKNN) enablement Jiaxing Hu
2026-08-12  9:40 ` [PATCH v7 01/10] accel/rocket: take the completion register writes under job_lock Jiaxing Hu
2026-08-12 12:47   ` Igor Paunovic
2026-08-12  9:40 ` [PATCH v7 02/10] dt-bindings: npu: rockchip: add rockchip,rk3576-rknn-core Jiaxing Hu
2026-08-13  7:04   ` Krzysztof Kozlowski
2026-08-12  9:40 ` [PATCH v7 03/10] dt-bindings: power: rockchip: allow resets in a power domain node Jiaxing Hu
2026-08-13  7:06   ` Krzysztof Kozlowski
2026-08-14  8:21     ` Jiaxing Hu
2026-08-12  9:40 ` [PATCH v7 04/10] dt-bindings: iommu: rockchip: allow the RK3576 NPU MMU clock set Jiaxing Hu
2026-08-12 10:45   ` Diederik de Haas
2026-08-13  9:27     ` Jiaxing Hu
2026-08-12  9:41 ` [PATCH v7 05/10] pmdomain/rockchip: add optional per-domain power-on settle delay Jiaxing Hu
2026-08-12  9:41 ` [PATCH v7 06/10] pmdomain/rockchip: cycle optional power-domain resets on power-on Jiaxing Hu
2026-08-12  9:41 ` [PATCH v7 07/10] accel/rocket: select the per-core clock and reset counts from match data Jiaxing Hu
2026-08-12  9:41 ` [PATCH v7 08/10] accel/rocket: add RK3576 NPU (RKNN) support Jiaxing Hu
2026-08-12 12:48   ` Igor Paunovic
2026-08-13  9:26     ` Jiaxing Hu
2026-08-13  9:56       ` Igor Paunovic
2026-08-14  8:26         ` Jiaxing Hu
2026-08-14 11:08           ` Igor Paunovic
     [not found]   ` <20260814110841.11238-1-royalnet026@gmail.com>
2026-08-15  3:12     ` Jiaxing Hu
2026-08-15 13:05       ` Igor Paunovic
2026-08-16  4:12         ` Jiaxing Hu
2026-08-16 18:53           ` Igor Paunovic
2026-08-16 19:58             ` Jiaxing Hu
2026-08-16 20:25               ` Igor Paunovic
2026-08-17  8:31                 ` Jiaxing Hu
2026-08-17  9:45                 ` Jiaxing Hu
2026-08-17 10:00                   ` Igor Paunovic
2026-08-17 10:20                     ` Jiaxing Hu
2026-08-17 11:05                       ` Igor Paunovic
2026-08-19 10:57                 ` Jiaxing Hu
2026-08-19 15:46                   ` Igor Paunovic
2026-08-19 18:48                     ` Igor Paunovic
2026-08-19 21:50                       ` Jiaxing Hu
2026-08-20 10:07                       ` Jiaxing Hu
2026-08-20 18:50                         ` Igor Paunovic
2026-08-22 10:09                           ` Jiaxing Hu [this message]
2026-08-12  9:41 ` [PATCH v7 09/10] arm64: dts: rockchip: rk3576: add NPU (RKNN) nodes Jiaxing Hu
2026-08-12  9:41 ` [PATCH v7 10/10] arm64: dts: rockchip: rk3576-rock-4d: enable NPU Jiaxing Hu
2026-08-12 10:20   ` Chaoyi Chen

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