* [PATCH 1/2] arm64: dts: rockchip: add max-link-speed for rk3399
@ 2016-12-16 9:42 Shawn Lin
[not found] ` <1481881357-1793-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Shawn Lin @ 2016-12-16 9:42 UTC (permalink / raw)
To: Heiko Stuebner
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Shawn Lin,
Brian Norris
Per the errata of TRM, rk3399 won't support gen2 from
now on, so let's set max-link-speed to 1 in order not
to doing training for gen2.
Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 66a11d1..0be5f71 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -297,6 +297,7 @@
<0 0 0 3 &pcie0_intc 2>,
<0 0 0 4 &pcie0_intc 3>;
msi-map = <0x0 &its 0x0 0x1000>;
+ max-link-speed = <1>;
phys = <&pcie_phy>;
phy-names = "pcie-phy";
ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread[parent not found: <1481881357-1793-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>]
* [PATCH 2/2] arm64: dts: rockchip: add aspm-no-l0s for rk3399 [not found] ` <1481881357-1793-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> @ 2016-12-16 9:42 ` Shawn Lin [not found] ` <1481881357-1793-2-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2017-01-06 9:11 ` [PATCH 1/2] arm64: dts: rockchip: add max-link-speed " Heiko Stuebner 1 sibling, 1 reply; 6+ messages in thread From: Shawn Lin @ 2016-12-16 9:42 UTC (permalink / raw) To: Heiko Stuebner Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Shawn Lin, Brian Norris Per the discussion of bug fix[1], we now actually leaves the default clock choice for pcie phy is derived from 24MHz OSC to guarantee the least BER. So let's add aspm-no-l0s here and folks could delete this property from their dts. [1] https://patchwork.kernel.org/patch/9470519/ Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 0be5f71..1037693 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -282,6 +282,7 @@ #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; + aspm-no-l0s; bus-range = <0x0 0x1>; clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
[parent not found: <1481881357-1793-2-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>]
* Re: [PATCH 2/2] arm64: dts: rockchip: add aspm-no-l0s for rk3399 [not found] ` <1481881357-1793-2-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> @ 2017-01-06 9:13 ` Heiko Stuebner 2017-01-13 1:43 ` Shawn Lin 2017-01-13 11:05 ` Heiko Stuebner 1 sibling, 1 reply; 6+ messages in thread From: Heiko Stuebner @ 2017-01-06 9:13 UTC (permalink / raw) To: Shawn Lin; +Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Brian Norris Hi Shawn, Am Freitag, 16. Dezember 2016, 17:42:37 CET schrieb Shawn Lin: > Per the discussion of bug fix[1], we now actually > leaves the default clock choice for pcie phy is > derived from 24MHz OSC to guarantee the least BER. > So let's add aspm-no-l0s here and folks could delete > this property from their dts. > > [1] https://patchwork.kernel.org/patch/9470519/ > Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> looks ok, but the underlying property addition hasn't been included yet, so we'll have to wait for a bit longer. If you notice the pci-host change going in, could you ping this patch please. Thanks Heiko ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] arm64: dts: rockchip: add aspm-no-l0s for rk3399 2017-01-06 9:13 ` Heiko Stuebner @ 2017-01-13 1:43 ` Shawn Lin 0 siblings, 0 replies; 6+ messages in thread From: Shawn Lin @ 2017-01-13 1:43 UTC (permalink / raw) To: Heiko Stuebner Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, shawn.lin-TNX95d0MmH7DzftRWevZcw, Brian Norris Hi Heiko, On 2017/1/6 17:13, Heiko Stuebner wrote: > Hi Shawn, > > Am Freitag, 16. Dezember 2016, 17:42:37 CET schrieb Shawn Lin: >> Per the discussion of bug fix[1], we now actually >> leaves the default clock choice for pcie phy is >> derived from 24MHz OSC to guarantee the least BER. >> So let's add aspm-no-l0s here and folks could delete >> this property from their dts. >> >> [1] https://patchwork.kernel.org/patch/9470519/ >> Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > > looks ok, but the underlying property addition hasn't been included yet, so > we'll have to wait for a bit longer. > > If you notice the pci-host change going in, could you ping this patch please. > > yes, it was merged into Bjorn's pci-host yesterday , so could you kindly pull this one? :) > Thanks > Heiko > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip > -- Best Regards Shawn Lin ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] arm64: dts: rockchip: add aspm-no-l0s for rk3399 [not found] ` <1481881357-1793-2-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2017-01-06 9:13 ` Heiko Stuebner @ 2017-01-13 11:05 ` Heiko Stuebner 1 sibling, 0 replies; 6+ messages in thread From: Heiko Stuebner @ 2017-01-13 11:05 UTC (permalink / raw) To: Shawn Lin; +Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Brian Norris Am Freitag, 16. Dezember 2016, 17:42:37 CET schrieb Shawn Lin: > Per the discussion of bug fix[1], we now actually > leaves the default clock choice for pcie phy is > derived from 24MHz OSC to guarantee the least BER. > So let's add aspm-no-l0s here and folks could delete > this property from their dts. > > [1] https://patchwork.kernel.org/patch/9470519/ > Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> applied for 4.11 Thanks Heiko ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] arm64: dts: rockchip: add max-link-speed for rk3399 [not found] ` <1481881357-1793-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2016-12-16 9:42 ` [PATCH 2/2] arm64: dts: rockchip: add aspm-no-l0s " Shawn Lin @ 2017-01-06 9:11 ` Heiko Stuebner 1 sibling, 0 replies; 6+ messages in thread From: Heiko Stuebner @ 2017-01-06 9:11 UTC (permalink / raw) To: Shawn Lin; +Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Brian Norris Am Freitag, 16. Dezember 2016, 17:42:36 CET schrieb Shawn Lin: > Per the errata of TRM, rk3399 won't support gen2 from > now on, so let's set max-link-speed to 1 in order not > to doing training for gen2. > > Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> I've moved the new line above msi-map and applied the result for 4.11 Thanks Heiko ^ permalink raw reply [flat|nested] 6+ messages in thread
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2016-12-16 9:42 [PATCH 1/2] arm64: dts: rockchip: add max-link-speed for rk3399 Shawn Lin
[not found] ` <1481881357-1793-1-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-12-16 9:42 ` [PATCH 2/2] arm64: dts: rockchip: add aspm-no-l0s " Shawn Lin
[not found] ` <1481881357-1793-2-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2017-01-06 9:13 ` Heiko Stuebner
2017-01-13 1:43 ` Shawn Lin
2017-01-13 11:05 ` Heiko Stuebner
2017-01-06 9:11 ` [PATCH 1/2] arm64: dts: rockchip: add max-link-speed " Heiko Stuebner
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