* [PATCH v3 0/5] support rockchip dwc3 driver
@ 2016-05-27 11:28 William Wu
2016-05-27 11:28 ` [PATCH v3 1/5] usb: dwc3: of-simple: add compatible for rockchip William Wu
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: William Wu @ 2016-05-27 11:28 UTC (permalink / raw)
To: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
balbi-DgEjT+Ai2ygdnm+yROfE0A, heiko-4mtYJXux2i+zQB+pC5nmwQ
Cc: huangtao-TNX95d0MmH7DzftRWevZcw,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA,
kever.yang-TNX95d0MmH7DzftRWevZcw,
dianders-hpIqsD4AKlfQT0dZR+AlfA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
eddie.cai-TNX95d0MmH7DzftRWevZcw, William Wu,
briannorris-hpIqsD4AKlfQT0dZR+AlfA,
John.Youn-HKixBCOQz3hWk0Htik3J/w
This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip platform).
William Wu (5):
usb: dwc3: of-simple: add compatible for rockchip
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: add phyif_utmi_quirk
usb: dwc3: add dis_del_phy_power_chg_quirk
usb: dwc3: rockchip: add devicetree bindings documentation
Documentation/devicetree/bindings/usb/dwc3.txt | 9 +++++
.../devicetree/bindings/usb/rockchip,dwc3.txt | 45 ++++++++++++++++++++++
drivers/usb/dwc3/core.c | 39 ++++++++++++++++++-
drivers/usb/dwc3/core.h | 20 ++++++++++
drivers/usb/dwc3/dwc3-of-simple.c | 1 +
drivers/usb/dwc3/platform_data.h | 4 ++
6 files changed, 117 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
--
1.9.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v3 1/5] usb: dwc3: of-simple: add compatible for rockchip 2016-05-27 11:28 [PATCH v3 0/5] support rockchip dwc3 driver William Wu @ 2016-05-27 11:28 ` William Wu 2016-05-27 11:28 ` [PATCH v3 3/5] usb: dwc3: add phyif_utmi_quirk William Wu [not found] ` <1464348488-20760-1-git-send-email-william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2 siblings, 0 replies; 6+ messages in thread From: William Wu @ 2016-05-27 11:28 UTC (permalink / raw) To: gregkh, balbi, heiko Cc: linux-rockchip, briannorris, dianders, kever.yang, huangtao, frank.wang, eddie.cai, John.Youn, linux-kernel, linux-usb, William Wu Rockchip platform merely enable usb3 clocks and populate its children. So we can use this generic glue layer to support Rockchip dwc3. Signed-off-by: William Wu <william.wu@rock-chips.com> --- Changes in v3: - None Changes in v2: - sort the list of_dwc3_simple_match (Doug) drivers/usb/dwc3/dwc3-of-simple.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c index 9743353..6da9656 100644 --- a/drivers/usb/dwc3/dwc3-of-simple.c +++ b/drivers/usb/dwc3/dwc3-of-simple.c @@ -161,6 +161,7 @@ static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = { static const struct of_device_id of_dwc3_simple_match[] = { { .compatible = "qcom,dwc3" }, + { .compatible = "rockchip,dwc3" }, { .compatible = "xlnx,zynqmp-dwc3" }, { /* Sentinel */ } }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 3/5] usb: dwc3: add phyif_utmi_quirk 2016-05-27 11:28 [PATCH v3 0/5] support rockchip dwc3 driver William Wu 2016-05-27 11:28 ` [PATCH v3 1/5] usb: dwc3: of-simple: add compatible for rockchip William Wu @ 2016-05-27 11:28 ` William Wu [not found] ` <1464348488-20760-1-git-send-email-william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2 siblings, 0 replies; 6+ messages in thread From: William Wu @ 2016-05-27 11:28 UTC (permalink / raw) To: gregkh, balbi, heiko Cc: linux-rockchip, briannorris, dianders, kever.yang, huangtao, frank.wang, eddie.cai, John.Youn, linux-kernel, linux-usb, William Wu Add a quirk to configure the core to support the UTMI+ PHY with an 8- or 16-bit interface. UTMI+ PHY interface is hardware property, and it's platform dependent. Normall, the PHYIf can be configured during coreconsultant. But for some specific usb cores(e.g. rk3399 soc dwc3), the default PHYIf configuration value is fault, so we need to reconfigure it by software. And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM must be set to the corresponding value according to the UTMI+ PHY interface. Signed-off-by: William Wu <william.wu@rock-chips.com> --- Changes in v3: - None Changes in v2: - add a quirk for phyif_utmi (Felipe) Documentation/devicetree/bindings/usb/dwc3.txt | 4 ++++ drivers/usb/dwc3/core.c | 23 +++++++++++++++++++++++ drivers/usb/dwc3/core.h | 12 ++++++++++++ drivers/usb/dwc3/platform_data.h | 2 ++ 4 files changed, 41 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 1ada121..34d13a5 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -42,6 +42,10 @@ Optional properties: - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2 PHY doesn't provide a free-running PHY clock. + - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface. + - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY + with an 8- or 16-bit interface. Value 0 select 8-bit + interface, value 1 select 16-bit interface. - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal utmi_l1_suspend_n, false when asserts utmi_sleep_n - snps,hird-threshold: HIRD threshold diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 8bcd3cc..d99c170 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -410,6 +410,7 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc) static int dwc3_phy_setup(struct dwc3 *dwc) { u32 reg; + u32 usbtrdtim; int ret; reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); @@ -505,6 +506,15 @@ static int dwc3_phy_setup(struct dwc3 *dwc) if (dwc->dis_u2_freeclk_exists_quirk) reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; + if (dwc->phyif_utmi_quirk) { + reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | + DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); + usbtrdtim = dwc->phyif_utmi ? USBTRDTIM_UTMI_16_BIT : + USBTRDTIM_UTMI_8_BIT; + reg |= DWC3_GUSB2PHYCFG_PHYIF(dwc->phyif_utmi) | + DWC3_GUSB2PHYCFG_USBTRDTIM(usbtrdtim); + } + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); return 0; @@ -800,6 +810,7 @@ static int dwc3_probe(struct platform_device *pdev) struct resource *res; struct dwc3 *dwc; u8 lpm_nyet_threshold; + u8 phyif_utmi; u8 tx_de_emphasis; u8 hird_threshold; u32 fladj = 0; @@ -857,6 +868,9 @@ static int dwc3_probe(struct platform_device *pdev) /* default to highest possible threshold */ lpm_nyet_threshold = 0xff; + /* default to UTMI+ 8-bit interface */ + phyif_utmi = 0; + /* default to -3.5dB de-emphasis */ tx_de_emphasis = 1; @@ -907,6 +921,10 @@ static int dwc3_probe(struct platform_device *pdev) dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, "snps,dis_u2_freeclk_exists_quirk"); + dwc->phyif_utmi_quirk = device_property_read_bool(dev, + "snps,phyif_utmi_quirk"); + device_property_read_u8(dev, "snps,phyif_utmi", + &phyif_utmi); dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, "snps,tx_de_emphasis_quirk"); device_property_read_u8(dev, "snps,tx_de_emphasis", @@ -943,6 +961,10 @@ static int dwc3_probe(struct platform_device *pdev) dwc->dis_u2_freeclk_exists_quirk = pdata->dis_u2_freeclk_exists_quirk; + dwc->phyif_utmi_quirk = pdata->phyif_utmi_quirk; + if (pdata->phyif_utmi) + phyif_utmi = pdata->phyif_utmi; + dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk; if (pdata->tx_de_emphasis) tx_de_emphasis = pdata->tx_de_emphasis; @@ -952,6 +974,7 @@ static int dwc3_probe(struct platform_device *pdev) } dwc->lpm_nyet_threshold = lpm_nyet_threshold; + dwc->phyif_utmi = phyif_utmi; dwc->tx_de_emphasis = tx_de_emphasis; dwc->hird_threshold = hird_threshold diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index ac2e6b5..e1fcae8 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -200,6 +200,12 @@ #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) #define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4) #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) +#define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3) +#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) +#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10) +#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) +#define USBTRDTIM_UTMI_8_BIT 9 +#define USBTRDTIM_UTMI_16_BIT 5 /* Global USB2 PHY Vendor Control Register */ #define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25) @@ -774,6 +780,10 @@ struct dwc3_scratchpad_array { * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists * in GUSB2PHYCFG, specify that USB2 PHY doesn't * provide a free-running PHY clock. + * @phyif_utmi_quirk: set if we enable phyif UTMI+ quirk + * @phyif_utmi: UTMI+ PHY interface value + * 0 - 8 bits + * 1 - 16 bits * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk * @tx_de_emphasis: Tx de-emphasis value * 0 - -6dB de-emphasis @@ -919,6 +929,8 @@ struct dwc3 { unsigned dis_rxdet_inp3_quirk:1; unsigned dis_u2_freeclk_exists_quirk:1; + unsigned phyif_utmi_quirk:1; + unsigned phyif_utmi:1; unsigned tx_de_emphasis_quirk:1; unsigned tx_de_emphasis:2; }; diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h index e1a1631..b521565 100644 --- a/drivers/usb/dwc3/platform_data.h +++ b/drivers/usb/dwc3/platform_data.h @@ -45,6 +45,8 @@ struct dwc3_platform_data { unsigned dis_rxdet_inp3_quirk:1; unsigned dis_u2_freeclk_exists_quirk:1; + unsigned phyif_utmi_quirk:1; + unsigned phyif_utmi:1; unsigned tx_de_emphasis_quirk:1; unsigned tx_de_emphasis:2; -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
[parent not found: <1464348488-20760-1-git-send-email-william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>]
* [PATCH v3 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk [not found] ` <1464348488-20760-1-git-send-email-william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> @ 2016-05-27 11:28 ` William Wu 2016-05-27 12:54 ` Felipe Balbi 2016-05-27 11:28 ` [PATCH v3 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk William Wu 1 sibling, 1 reply; 6+ messages in thread From: William Wu @ 2016-05-27 11:28 UTC (permalink / raw) To: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, balbi-DgEjT+Ai2ygdnm+yROfE0A, heiko-4mtYJXux2i+zQB+pC5nmwQ Cc: huangtao-TNX95d0MmH7DzftRWevZcw, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-usb-u79uwXL29TY76Z2rM5mHXA, kever.yang-TNX95d0MmH7DzftRWevZcw, dianders-hpIqsD4AKlfQT0dZR+AlfA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, eddie.cai-TNX95d0MmH7DzftRWevZcw, William Wu, briannorris-hpIqsD4AKlfQT0dZR+AlfA, John.Youn-HKixBCOQz3hWk0Htik3J/w Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Signed-off-by: William Wu <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- Changes in v3: - None Changes in v2: - None Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++ drivers/usb/dwc3/core.c | 7 +++++++ drivers/usb/dwc3/core.h | 5 +++++ drivers/usb/dwc3/platform_data.h | 1 + 4 files changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 7d7ce08..1ada121 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -39,6 +39,9 @@ Optional properties: disabling the suspend signal to the PHY. - snps,dis_rxdet_inp3_quirk: when set core will disable receiver detection in PHY P3 power state. + - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists + in GUSB2PHYCFG, specify that USB2 PHY doesn't provide + a free-running PHY clock. - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal utmi_l1_suspend_n, false when asserts utmi_sleep_n - snps,hird-threshold: HIRD threshold diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index a590cd2..8bcd3cc 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -502,6 +502,9 @@ static int dwc3_phy_setup(struct dwc3 *dwc) if (dwc->dis_enblslpm_quirk) reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; + if (dwc->dis_u2_freeclk_exists_quirk) + reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); return 0; @@ -901,6 +904,8 @@ static int dwc3_probe(struct platform_device *pdev) "snps,dis_enblslpm_quirk"); dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, "snps,dis_rxdet_inp3_quirk"); + dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, + "snps,dis_u2_freeclk_exists_quirk"); dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, "snps,tx_de_emphasis_quirk"); @@ -935,6 +940,8 @@ static int dwc3_probe(struct platform_device *pdev) dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk; dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk; dwc->dis_rxdet_inp3_quirk = pdata->dis_rxdet_inp3_quirk; + dwc->dis_u2_freeclk_exists_quirk = + pdata->dis_u2_freeclk_exists_quirk; dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk; if (pdata->tx_de_emphasis) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 7ddf944..ac2e6b5 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -196,6 +196,7 @@ /* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) +#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30) #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) #define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4) #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) @@ -770,6 +771,9 @@ struct dwc3_scratchpad_array { * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, * disabling the suspend signal to the PHY. + * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists + * in GUSB2PHYCFG, specify that USB2 PHY doesn't + * provide a free-running PHY clock. * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk * @tx_de_emphasis: Tx de-emphasis value * 0 - -6dB de-emphasis @@ -913,6 +917,7 @@ struct dwc3 { unsigned dis_u2_susphy_quirk:1; unsigned dis_enblslpm_quirk:1; unsigned dis_rxdet_inp3_quirk:1; + unsigned dis_u2_freeclk_exists_quirk:1; unsigned tx_de_emphasis_quirk:1; unsigned tx_de_emphasis:2; diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h index 8826cca..e1a1631 100644 --- a/drivers/usb/dwc3/platform_data.h +++ b/drivers/usb/dwc3/platform_data.h @@ -43,6 +43,7 @@ struct dwc3_platform_data { unsigned dis_u2_susphy_quirk:1; unsigned dis_enblslpm_quirk:1; unsigned dis_rxdet_inp3_quirk:1; + unsigned dis_u2_freeclk_exists_quirk:1; unsigned tx_de_emphasis_quirk:1; unsigned tx_de_emphasis:2; -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk 2016-05-27 11:28 ` [PATCH v3 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk William Wu @ 2016-05-27 12:54 ` Felipe Balbi 0 siblings, 0 replies; 6+ messages in thread From: Felipe Balbi @ 2016-05-27 12:54 UTC (permalink / raw) To: gregkh, heiko Cc: linux-rockchip, briannorris, dianders, kever.yang, huangtao, frank.wang, eddie.cai, John.Youn, linux-kernel, linux-usb, William Wu [-- Attachment #1: Type: text/plain, Size: 405 bytes --] Hi, William Wu <william.wu@rock-chips.com> writes: > Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, > which specifies whether the USB2.0 PHY provides a free-running > PHY clock, which is active when the clock control input is active. > > Signed-off-by: William Wu <william.wu@rock-chips.com> can you rebase on top of my testing/next? We're dropping pdata support. -- balbi [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 818 bytes --] ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk [not found] ` <1464348488-20760-1-git-send-email-william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2016-05-27 11:28 ` [PATCH v3 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk William Wu @ 2016-05-27 11:28 ` William Wu 1 sibling, 0 replies; 6+ messages in thread From: William Wu @ 2016-05-27 11:28 UTC (permalink / raw) To: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, balbi-DgEjT+Ai2ygdnm+yROfE0A, heiko-4mtYJXux2i+zQB+pC5nmwQ Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, briannorris-hpIqsD4AKlfQT0dZR+AlfA, dianders-hpIqsD4AKlfQT0dZR+AlfA, kever.yang-TNX95d0MmH7DzftRWevZcw, huangtao-TNX95d0MmH7DzftRWevZcw, frank.wang-TNX95d0MmH7DzftRWevZcw, eddie.cai-TNX95d0MmH7DzftRWevZcw, John.Youn-HKixBCOQz3hWk0Htik3J/w, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-usb-u79uwXL29TY76Z2rM5mHXA, William Wu Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, which specifies whether disable delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. Signed-off-by: William Wu <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- Changes in v3: - None Changes in v2: - None Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++ drivers/usb/dwc3/core.c | 7 +++++++ drivers/usb/dwc3/core.h | 3 +++ drivers/usb/dwc3/platform_data.h | 1 + 4 files changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 34d13a5..bd5bef0 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -42,6 +42,8 @@ Optional properties: - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2 PHY doesn't provide a free-running PHY clock. + - snps,dis_del_phy_power_chg_quirk: when set core will change PHY power + from P0 to P1/P2/P3 without delay. - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface. - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface. Value 0 select 8-bit diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index d99c170..c06870c 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -451,6 +451,9 @@ static int dwc3_phy_setup(struct dwc3 *dwc) if (dwc->dis_u3_susphy_quirk) reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; + if (dwc->dis_del_phy_power_chg_quirk) + reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); @@ -920,6 +923,8 @@ static int dwc3_probe(struct platform_device *pdev) "snps,dis_rxdet_inp3_quirk"); dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, "snps,dis_u2_freeclk_exists_quirk"); + dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, + "snps,dis_del_phy_power_chg_quirk"); dwc->phyif_utmi_quirk = device_property_read_bool(dev, "snps,phyif_utmi_quirk"); @@ -960,6 +965,8 @@ static int dwc3_probe(struct platform_device *pdev) dwc->dis_rxdet_inp3_quirk = pdata->dis_rxdet_inp3_quirk; dwc->dis_u2_freeclk_exists_quirk = pdata->dis_u2_freeclk_exists_quirk; + dwc->dis_del_phy_power_chg_quirk = + pdata->dis_del_phy_power_chg_quirk; dwc->phyif_utmi_quirk = pdata->phyif_utmi_quirk; if (pdata->phyif_utmi) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index e1fcae8..abed84f 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -780,6 +780,8 @@ struct dwc3_scratchpad_array { * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists * in GUSB2PHYCFG, specify that USB2 PHY doesn't * provide a free-running PHY clock. + * @dis_del_phy_power_chg_quirk: set if we disable delay phy power + * change quirk. * @phyif_utmi_quirk: set if we enable phyif UTMI+ quirk * @phyif_utmi: UTMI+ PHY interface value * 0 - 8 bits @@ -928,6 +930,7 @@ struct dwc3 { unsigned dis_enblslpm_quirk:1; unsigned dis_rxdet_inp3_quirk:1; unsigned dis_u2_freeclk_exists_quirk:1; + unsigned dis_del_phy_power_chg_quirk:1; unsigned phyif_utmi_quirk:1; unsigned phyif_utmi:1; diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h index b521565..ab45d91 100644 --- a/drivers/usb/dwc3/platform_data.h +++ b/drivers/usb/dwc3/platform_data.h @@ -44,6 +44,7 @@ struct dwc3_platform_data { unsigned dis_enblslpm_quirk:1; unsigned dis_rxdet_inp3_quirk:1; unsigned dis_u2_freeclk_exists_quirk:1; + unsigned dis_del_phy_power_chg_quirk:1; unsigned phyif_utmi_quirk:1; unsigned phyif_utmi:1; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-05-27 12:54 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2016-05-27 11:28 [PATCH v3 0/5] support rockchip dwc3 driver William Wu
2016-05-27 11:28 ` [PATCH v3 1/5] usb: dwc3: of-simple: add compatible for rockchip William Wu
2016-05-27 11:28 ` [PATCH v3 3/5] usb: dwc3: add phyif_utmi_quirk William Wu
[not found] ` <1464348488-20760-1-git-send-email-william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-05-27 11:28 ` [PATCH v3 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk William Wu
2016-05-27 12:54 ` Felipe Balbi
2016-05-27 11:28 ` [PATCH v3 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk William Wu
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