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From: Heiko Stuebner <heiko@sntech.de>
To: Shawn Lin <shawn.lin@rock-chips.com>
Cc: linux-rockchip@lists.infradead.org,
	Shawn Lin <shawn.lin@rock-chips.com>,
	Andrew Powers-Holmes <aholmes@omnom.net>
Subject: Re: [PATCH 1/2] arm64: dts: rockchip: Fix rk356x PCIe range mappings
Date: Tue, 20 Jan 2026 10:44:15 +0100	[thread overview]
Message-ID: <9350956.lvqk35OSZv@phil> (raw)
In-Reply-To: <1767600929-195341-1-git-send-email-shawn.lin@rock-chips.com>

Hi Shawn,

Am Montag, 5. Januar 2026, 09:15:28 Mitteleuropäische Normalzeit schrieb Shawn Lin:
> The pcie bus address should be mapped 1:1 to the cpu side MMIO address, so
> that there is no same address allocated from normal system memory. Otherwise
> it's broken if the same address assigned to the EP for DMA purpose.Fix it to
> sync with the vendor BSP.
> 
> Fixes: 568a67e742df ("arm64: dts: rockchip: Fix rk356x PCIe register and range mappings")
> Fixes: 66b51ea7d70f ("arm64: dts: rockchip: Add rk3568 PCIe2x1 controller")
> Cc: Andrew Powers-Holmes <aholmes@omnom.net>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

Is there some way to reproduce the issue?

Or alternatively, if you're just syncing with the vendor BSP here,
can you describe where the issue happend or was noticed?


Thanks a lot
Heiko

> ---
> 
>  arch/arm64/boot/dts/rockchip/rk3568.dtsi      | 4 ++--
>  arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index e719a3d..658097e 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -185,7 +185,7 @@
>  		      <0x0 0xf2000000 0x0 0x00100000>;
>  		ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
>  			 <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
> -			 <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
> +			 <0x03000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>;
>  		reg-names = "dbi", "apb", "config";
>  		resets = <&cru SRST_PCIE30X1_POWERUP>;
>  		reset-names = "pipe";
> @@ -238,7 +238,7 @@
>  		      <0x0 0xf0000000 0x0 0x00100000>;
>  		ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
>  			 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
> -			 <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
> +			 <0x03000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>;
>  		reg-names = "dbi", "apb", "config";
>  		resets = <&cru SRST_PCIE30X2_POWERUP>;
>  		reset-names = "pipe";
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
> index 8893b7b..a2c4957 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
> @@ -1022,7 +1022,7 @@
>  		power-domains = <&power RK3568_PD_PIPE>;
>  		ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
>  			 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
> -			 <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
> +			 <0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
>  		resets = <&cru SRST_PCIE20_POWERUP>;
>  		reset-names = "pipe";
>  		#address-cells = <3>;
> 





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  parent reply	other threads:[~2026-01-20  9:44 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-05  8:15 [PATCH 1/2] arm64: dts: rockchip: Fix rk356x PCIe range mappings Shawn Lin
2026-01-05  8:15 ` [PATCH 2/2] arm64: dts: rockchip: Fix rk3588 " Shawn Lin
2026-01-20  9:44 ` Heiko Stuebner [this message]
2026-01-20 10:14   ` [PATCH 1/2] arm64: dts: rockchip: Fix rk356x " Shawn Lin
2026-02-04 19:11 ` Heiko Stübner

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