* [PATCH 1/2] arm64: dts: rockchip: Fix rk356x PCIe range mappings
@ 2026-01-05 8:15 Shawn Lin
2026-01-05 8:15 ` [PATCH 2/2] arm64: dts: rockchip: Fix rk3588 " Shawn Lin
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Shawn Lin @ 2026-01-05 8:15 UTC (permalink / raw)
To: Heiko Stuebner; +Cc: linux-rockchip, Shawn Lin, Andrew Powers-Holmes
The pcie bus address should be mapped 1:1 to the cpu side MMIO address, so
that there is no same address allocated from normal system memory. Otherwise
it's broken if the same address assigned to the EP for DMA purpose.Fix it to
sync with the vendor BSP.
Fixes: 568a67e742df ("arm64: dts: rockchip: Fix rk356x PCIe register and range mappings")
Fixes: 66b51ea7d70f ("arm64: dts: rockchip: Add rk3568 PCIe2x1 controller")
Cc: Andrew Powers-Holmes <aholmes@omnom.net>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 ++--
arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index e719a3d..658097e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -185,7 +185,7 @@
<0x0 0xf2000000 0x0 0x00100000>;
ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
- <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
+ <0x03000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE30X1_POWERUP>;
reset-names = "pipe";
@@ -238,7 +238,7 @@
<0x0 0xf0000000 0x0 0x00100000>;
ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
- <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
+ <0x03000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE30X2_POWERUP>;
reset-names = "pipe";
diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
index 8893b7b..a2c4957 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
@@ -1022,7 +1022,7 @@
power-domains = <&power RK3568_PD_PIPE>;
ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
- <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
+ <0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
resets = <&cru SRST_PCIE20_POWERUP>;
reset-names = "pipe";
#address-cells = <3>;
--
2.7.4
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] arm64: dts: rockchip: Fix rk3588 PCIe range mappings
2026-01-05 8:15 [PATCH 1/2] arm64: dts: rockchip: Fix rk356x PCIe range mappings Shawn Lin
@ 2026-01-05 8:15 ` Shawn Lin
2026-01-20 9:44 ` [PATCH 1/2] arm64: dts: rockchip: Fix rk356x " Heiko Stuebner
2026-02-04 19:11 ` Heiko Stübner
2 siblings, 0 replies; 5+ messages in thread
From: Shawn Lin @ 2026-01-05 8:15 UTC (permalink / raw)
To: Heiko Stuebner; +Cc: linux-rockchip, Shawn Lin, Sebastian Reichel
The pcie bus address should be mapped 1:1 to the cpu side MMIO address, so
that there is no same address allocated from normal system memory. Otherwise
it's broken if the same address assigned to the EP for DMA purpose.Fix it to
sync with the vendor BSP.
Fixes: 0acf4fa7f187 ("arm64: dts: rockchip: add PCIe3 support for rk3588")
Fixes: 8d81b77f4c49 ("arm64: dts: rockchip: add rk3588 PCIe2 support")
Cc: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 4 ++--
| 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 7ab12d1..fdb0172 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1955,7 +1955,7 @@
power-domains = <&power RK3588_PD_PCIE>;
ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
<0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
- <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
+ <0x03000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>;
reg = <0xa 0x40c00000 0x0 0x00400000>,
<0x0 0xfe180000 0x0 0x00010000>,
<0x0 0xf3000000 0x0 0x00100000>;
@@ -2007,7 +2007,7 @@
power-domains = <&power RK3588_PD_PCIE>;
ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
- <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
+ <0x03000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;
reg = <0xa 0x41000000 0x0 0x00400000>,
<0x0 0xfe190000 0x0 0x00010000>,
<0x0 0xf4000000 0x0 0x00100000>;
--git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
index 6e5a584..a264001 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
@@ -375,7 +375,7 @@
power-domains = <&power RK3588_PD_PCIE>;
ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
- <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
+ <0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
reg = <0xa 0x40000000 0x0 0x00400000>,
<0x0 0xfe150000 0x0 0x00010000>,
<0x0 0xf0000000 0x0 0x00100000>;
@@ -462,7 +462,7 @@
power-domains = <&power RK3588_PD_PCIE>;
ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
<0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
- <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
+ <0x03000000 0x9 0x40000000 0x9 0x40000000 0x0 0x40000000>;
reg = <0xa 0x40400000 0x0 0x00400000>,
<0x0 0xfe160000 0x0 0x00010000>,
<0x0 0xf1000000 0x0 0x00100000>;
@@ -512,7 +512,7 @@
power-domains = <&power RK3588_PD_PCIE>;
ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
- <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
+ <0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
reg = <0xa 0x40800000 0x0 0x00400000>,
<0x0 0xfe170000 0x0 0x00010000>,
<0x0 0xf2000000 0x0 0x00100000>;
--
2.7.4
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http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] arm64: dts: rockchip: Fix rk356x PCIe range mappings
2026-01-05 8:15 [PATCH 1/2] arm64: dts: rockchip: Fix rk356x PCIe range mappings Shawn Lin
2026-01-05 8:15 ` [PATCH 2/2] arm64: dts: rockchip: Fix rk3588 " Shawn Lin
@ 2026-01-20 9:44 ` Heiko Stuebner
2026-01-20 10:14 ` Shawn Lin
2026-02-04 19:11 ` Heiko Stübner
2 siblings, 1 reply; 5+ messages in thread
From: Heiko Stuebner @ 2026-01-20 9:44 UTC (permalink / raw)
To: Shawn Lin; +Cc: linux-rockchip, Shawn Lin, Andrew Powers-Holmes
Hi Shawn,
Am Montag, 5. Januar 2026, 09:15:28 Mitteleuropäische Normalzeit schrieb Shawn Lin:
> The pcie bus address should be mapped 1:1 to the cpu side MMIO address, so
> that there is no same address allocated from normal system memory. Otherwise
> it's broken if the same address assigned to the EP for DMA purpose.Fix it to
> sync with the vendor BSP.
>
> Fixes: 568a67e742df ("arm64: dts: rockchip: Fix rk356x PCIe register and range mappings")
> Fixes: 66b51ea7d70f ("arm64: dts: rockchip: Add rk3568 PCIe2x1 controller")
> Cc: Andrew Powers-Holmes <aholmes@omnom.net>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Is there some way to reproduce the issue?
Or alternatively, if you're just syncing with the vendor BSP here,
can you describe where the issue happend or was noticed?
Thanks a lot
Heiko
> ---
>
> arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 ++--
> arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index e719a3d..658097e 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -185,7 +185,7 @@
> <0x0 0xf2000000 0x0 0x00100000>;
> ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
> <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
> - <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
> + <0x03000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>;
> reg-names = "dbi", "apb", "config";
> resets = <&cru SRST_PCIE30X1_POWERUP>;
> reset-names = "pipe";
> @@ -238,7 +238,7 @@
> <0x0 0xf0000000 0x0 0x00100000>;
> ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
> <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
> - <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
> + <0x03000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>;
> reg-names = "dbi", "apb", "config";
> resets = <&cru SRST_PCIE30X2_POWERUP>;
> reset-names = "pipe";
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
> index 8893b7b..a2c4957 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
> @@ -1022,7 +1022,7 @@
> power-domains = <&power RK3568_PD_PIPE>;
> ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
> <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
> - <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
> + <0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
> resets = <&cru SRST_PCIE20_POWERUP>;
> reset-names = "pipe";
> #address-cells = <3>;
>
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] arm64: dts: rockchip: Fix rk356x PCIe range mappings
2026-01-20 9:44 ` [PATCH 1/2] arm64: dts: rockchip: Fix rk356x " Heiko Stuebner
@ 2026-01-20 10:14 ` Shawn Lin
0 siblings, 0 replies; 5+ messages in thread
From: Shawn Lin @ 2026-01-20 10:14 UTC (permalink / raw)
To: Heiko Stuebner; +Cc: shawn.lin, linux-rockchip, Andrew Powers-Holmes
在 2026/01/20 星期二 17:44, Heiko Stuebner 写道:
> Hi Shawn,
>
> Am Montag, 5. Januar 2026, 09:15:28 Mitteleuropäische Normalzeit schrieb Shawn Lin:
>> The pcie bus address should be mapped 1:1 to the cpu side MMIO address, so
>> that there is no same address allocated from normal system memory. Otherwise
>> it's broken if the same address assigned to the EP for DMA purpose.Fix it to
>> sync with the vendor BSP.
>>
>> Fixes: 568a67e742df ("arm64: dts: rockchip: Fix rk356x PCIe register and range mappings")
>> Fixes: 66b51ea7d70f ("arm64: dts: rockchip: Add rk3568 PCIe2x1 controller")
>> Cc: Andrew Powers-Holmes <aholmes@omnom.net>
>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>
> Is there some way to reproduce the issue?
>
Yes. Mount a full NVMe attached to RK3568, and do md5sum for the files
in NVMe in loop, there is a certain probability that the MD5 value of a
file is incorrect.
> Or alternatively, if you're just syncing with the vendor BSP here,
> can you describe where the issue happend or was noticed?
>
>
> Thanks a lot
> Heiko
>
>> ---
>>
>> arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 ++--
>> arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 +-
>> 2 files changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
>> index e719a3d..658097e 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
>> @@ -185,7 +185,7 @@
>> <0x0 0xf2000000 0x0 0x00100000>;
>> ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
>> <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
>> - <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
>> + <0x03000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>;
>> reg-names = "dbi", "apb", "config";
>> resets = <&cru SRST_PCIE30X1_POWERUP>;
>> reset-names = "pipe";
>> @@ -238,7 +238,7 @@
>> <0x0 0xf0000000 0x0 0x00100000>;
>> ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
>> <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
>> - <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
>> + <0x03000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>;
>> reg-names = "dbi", "apb", "config";
>> resets = <&cru SRST_PCIE30X2_POWERUP>;
>> reset-names = "pipe";
>> diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
>> index 8893b7b..a2c4957 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
>> @@ -1022,7 +1022,7 @@
>> power-domains = <&power RK3568_PD_PIPE>;
>> ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
>> <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
>> - <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
>> + <0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
>> resets = <&cru SRST_PCIE20_POWERUP>;
>> reset-names = "pipe";
>> #address-cells = <3>;
>>
>
>
>
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
_______________________________________________
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] arm64: dts: rockchip: Fix rk356x PCIe range mappings
2026-01-05 8:15 [PATCH 1/2] arm64: dts: rockchip: Fix rk356x PCIe range mappings Shawn Lin
2026-01-05 8:15 ` [PATCH 2/2] arm64: dts: rockchip: Fix rk3588 " Shawn Lin
2026-01-20 9:44 ` [PATCH 1/2] arm64: dts: rockchip: Fix rk356x " Heiko Stuebner
@ 2026-02-04 19:11 ` Heiko Stübner
2 siblings, 0 replies; 5+ messages in thread
From: Heiko Stübner @ 2026-02-04 19:11 UTC (permalink / raw)
To: Shawn Lin; +Cc: linux-rockchip, Shawn Lin, Andrew Powers-Holmes
Am Montag, 5. Januar 2026, 09:15:28 Mitteleuropäische Normalzeit schrieb Shawn Lin:
> The pcie bus address should be mapped 1:1 to the cpu side MMIO address, so
> that there is no same address allocated from normal system memory. Otherwise
> it's broken if the same address assigned to the EP for DMA purpose.Fix it to
> sync with the vendor BSP.
>
> Fixes: 568a67e742df ("arm64: dts: rockchip: Fix rk356x PCIe register and range mappings")
> Fixes: 66b51ea7d70f ("arm64: dts: rockchip: Add rk3568 PCIe2x1 controller")
> Cc: Andrew Powers-Holmes <aholmes@omnom.net>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
somehow I seem to have forgotten to send the "applied" mail.
Anyway, both patches were applied 2 weeks ago, and are on their way
to the next merge-window.
With their stable-tags, they then should also migrate to older kernels.
Heiko
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2026-02-04 19:11 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2026-01-05 8:15 [PATCH 1/2] arm64: dts: rockchip: Fix rk356x PCIe range mappings Shawn Lin
2026-01-05 8:15 ` [PATCH 2/2] arm64: dts: rockchip: Fix rk3588 " Shawn Lin
2026-01-20 9:44 ` [PATCH 1/2] arm64: dts: rockchip: Fix rk356x " Heiko Stuebner
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