* [PATCH v13 00/12] media: rkisp1: Add support for i.MX8MP
@ 2024-02-18 20:43 Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 01/12] media: rkisp1: Add and use rkisp1_has_feature() macro Laurent Pinchart
` (12 more replies)
0 siblings, 13 replies; 17+ messages in thread
From: Laurent Pinchart @ 2024-02-18 20:43 UTC (permalink / raw)
To: linux-media
Cc: Adam Ford, Alexander Stein, Conor Dooley, Dafna Hirschfeld,
Heiko Stuebner, Helen Koike, Kieran Bingham, Krzysztof Kozlowski,
Paul Elder, Rob Herring, Tomi Valkeinen, devicetree,
linux-rockchip
Hello,
This series extends the rkisp1 driver to support the ISP found in the
NXP i.MX8MP SoC.
The ISP IP cores in the Rockchip RK3399 (known as the "Rockchip ISP1")
and in the NXP i.MX8MP have the same origin, and have slightly diverged
over time as they are now independently developed (afaik) by Rockchip
and VeriSilicon. The latter is marketed under the name "ISP8000Nano",
and is close enough to the RK3399 ISP that it can easily be supported by
the same driver.
This version of the series specifically has been tested on a Polyhex
Debix model A with an IMX219 camera sensor (Raspberry Pi cam v2).
See individual patches for a detailed description of changes compared to
v12.
This should hopefully be the last version, I plan to send a pull request
in a few days, in time for v6.9.
Laurent Pinchart (2):
media: rkisp1: Add and use rkisp1_has_feature() macro
media: rkisp1: Configure gasket on i.MX8MP
Paul Elder (10):
media: rkisp1: Support setting memory stride for main path
media: rkisp1: Support devices lacking self path
media: rkisp1: Support devices lacking dual crop
dt-bindings: media: rkisp1: Add i.MX8MP ISP to compatible
media: rkisp1: Add version enum for i.MX8MP ISP
media: rkisp1: Support i.MX8MP's 34-bit DMA
media: rkisp1: Add YC swap capability
media: rkisp1: Add UYVY as an output format
media: rkisp1: Fix endianness on raw streams on i.MX8MP
media: rkisp1: Add match data for i.MX8MP ISP
.../bindings/media/rockchip-isp1.yaml | 37 +++-
.../platform/rockchip/rkisp1/rkisp1-capture.c | 180 ++++++++++++++----
.../platform/rockchip/rkisp1/rkisp1-common.h | 35 +++-
.../platform/rockchip/rkisp1/rkisp1-dev.c | 71 ++++++-
.../platform/rockchip/rkisp1/rkisp1-isp.c | 131 ++++++++++++-
.../platform/rockchip/rkisp1/rkisp1-regs.h | 35 ++++
.../platform/rockchip/rkisp1/rkisp1-resizer.c | 19 +-
include/uapi/linux/rkisp1-config.h | 50 ++---
8 files changed, 472 insertions(+), 86 deletions(-)
base-commit: e0b8eb0f6d652981bfd9ba7c619c9d81ed087ad0
--
Regards,
Laurent Pinchart
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v13 01/12] media: rkisp1: Add and use rkisp1_has_feature() macro
2024-02-18 20:43 [PATCH v13 00/12] media: rkisp1: Add support for i.MX8MP Laurent Pinchart
@ 2024-02-18 20:43 ` Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 02/12] media: rkisp1: Support setting memory stride for main path Laurent Pinchart
` (11 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Laurent Pinchart @ 2024-02-18 20:43 UTC (permalink / raw)
To: linux-media
Cc: Adam Ford, Alexander Stein, Dafna Hirschfeld, Heiko Stuebner,
Helen Koike, Kieran Bingham, Paul Elder, Tomi Valkeinen,
linux-rockchip
Simplify feature tests with a macro that shortens lines.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
---
.../media/platform/rockchip/rkisp1/rkisp1-common.h | 3 +++
drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c | 12 ++++++------
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
index 4b6b28c05b89..35efdabf9db1 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
@@ -119,6 +119,9 @@ enum rkisp1_feature {
RKISP1_FEATURE_MIPI_CSI2 = BIT(0),
};
+#define rkisp1_has_feature(rkisp1, feature) \
+ ((rkisp1)->info->features & RKISP1_FEATURE_##feature)
+
/*
* struct rkisp1_info - Model-specific ISP Information
*
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
index f96f821a7b50..8c1040ca02a3 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
@@ -207,7 +207,7 @@ static int rkisp1_subdev_notifier_register(struct rkisp1_device *rkisp1)
switch (reg) {
case 0:
/* MIPI CSI-2 port */
- if (!(rkisp1->info->features & RKISP1_FEATURE_MIPI_CSI2)) {
+ if (!rkisp1_has_feature(rkisp1, MIPI_CSI2)) {
dev_err(rkisp1->dev,
"internal CSI must be available for port 0\n");
ret = -EINVAL;
@@ -339,7 +339,7 @@ static int rkisp1_create_links(struct rkisp1_device *rkisp1)
unsigned int i;
int ret;
- if (rkisp1->info->features & RKISP1_FEATURE_MIPI_CSI2) {
+ if (rkisp1_has_feature(rkisp1, MIPI_CSI2)) {
/* Link the CSI receiver to the ISP. */
ret = media_create_pad_link(&rkisp1->csi.sd.entity,
RKISP1_CSI_PAD_SRC,
@@ -391,7 +391,7 @@ static int rkisp1_create_links(struct rkisp1_device *rkisp1)
static void rkisp1_entities_unregister(struct rkisp1_device *rkisp1)
{
- if (rkisp1->info->features & RKISP1_FEATURE_MIPI_CSI2)
+ if (rkisp1_has_feature(rkisp1, MIPI_CSI2))
rkisp1_csi_unregister(rkisp1);
rkisp1_params_unregister(rkisp1);
rkisp1_stats_unregister(rkisp1);
@@ -424,7 +424,7 @@ static int rkisp1_entities_register(struct rkisp1_device *rkisp1)
if (ret)
goto error;
- if (rkisp1->info->features & RKISP1_FEATURE_MIPI_CSI2) {
+ if (rkisp1_has_feature(rkisp1, MIPI_CSI2)) {
ret = rkisp1_csi_register(rkisp1);
if (ret)
goto error;
@@ -628,7 +628,7 @@ static int rkisp1_probe(struct platform_device *pdev)
err_unreg_entities:
rkisp1_entities_unregister(rkisp1);
err_cleanup_csi:
- if (rkisp1->info->features & RKISP1_FEATURE_MIPI_CSI2)
+ if (rkisp1_has_feature(rkisp1, MIPI_CSI2))
rkisp1_csi_cleanup(rkisp1);
err_unreg_media_dev:
media_device_unregister(&rkisp1->media_dev);
@@ -649,7 +649,7 @@ static void rkisp1_remove(struct platform_device *pdev)
v4l2_async_nf_cleanup(&rkisp1->notifier);
rkisp1_entities_unregister(rkisp1);
- if (rkisp1->info->features & RKISP1_FEATURE_MIPI_CSI2)
+ if (rkisp1_has_feature(rkisp1, MIPI_CSI2))
rkisp1_csi_cleanup(rkisp1);
rkisp1_debug_cleanup(rkisp1);
--
Regards,
Laurent Pinchart
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v13 02/12] media: rkisp1: Support setting memory stride for main path
2024-02-18 20:43 [PATCH v13 00/12] media: rkisp1: Add support for i.MX8MP Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 01/12] media: rkisp1: Add and use rkisp1_has_feature() macro Laurent Pinchart
@ 2024-02-18 20:43 ` Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 03/12] media: rkisp1: Support devices lacking self path Laurent Pinchart
` (10 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Laurent Pinchart @ 2024-02-18 20:43 UTC (permalink / raw)
To: linux-media
Cc: Paul Elder, Adam Ford, Alexander Stein, Dafna Hirschfeld,
Heiko Stuebner, Helen Koike, Kieran Bingham, Tomi Valkeinen,
linux-rockchip
From: Paul Elder <paul.elder@ideasonboard.com>
Some versions of the ISP supported by the rkisp1 driver, such as the ISP
in the i.MX8MP, implement configurable memory stride for the main path
the same way as already implemented by the driver for the self path.
Support this feature by adding a main stride feature flag and program
the corresponding registers accordingly.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
---
Changes since v3:
- Implement memory stride support
- Squash patch that adds register bits definitions
- Reword the commit message
Changes since v2:
- Document the RKISP1_FEATURE_MAIN_STRIDE bit
- Use the rkisp1_has_feature() macro
---
.../platform/rockchip/rkisp1/rkisp1-capture.c | 34 ++++++++++++-------
.../platform/rockchip/rkisp1/rkisp1-common.h | 6 ++--
.../platform/rockchip/rkisp1/rkisp1-regs.h | 27 +++++++++++++++
3 files changed, 52 insertions(+), 15 deletions(-)
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
index aebd3c12020b..3c24c8c7ad68 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
@@ -442,6 +442,14 @@ static void rkisp1_mp_config(struct rkisp1_capture *cap)
rkisp1_write(rkisp1, cap->config->mi.cr_size_init,
rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR));
+ if (rkisp1_has_feature(rkisp1, MAIN_STRIDE)) {
+ rkisp1_write(rkisp1, RKISP1_CIF_MI_MP_Y_LLENGTH, cap->stride);
+ rkisp1_write(rkisp1, RKISP1_CIF_MI_MP_Y_PIC_WIDTH, pixm->width);
+ rkisp1_write(rkisp1, RKISP1_CIF_MI_MP_Y_PIC_HEIGHT, pixm->height);
+ rkisp1_write(rkisp1, RKISP1_CIF_MI_MP_Y_PIC_SIZE,
+ cap->stride * pixm->height);
+ }
+
rkisp1_irq_frame_end_enable(cap);
/* set uv swapping for semiplanar formats */
@@ -479,11 +487,11 @@ static void rkisp1_sp_config(struct rkisp1_capture *cap)
rkisp1_write(rkisp1, cap->config->mi.cr_size_init,
rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR));
- rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_LLENGTH, cap->sp_y_stride);
+ rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_LLENGTH, cap->stride);
rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_PIC_WIDTH, pixm->width);
rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_PIC_HEIGHT, pixm->height);
rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_PIC_SIZE,
- cap->sp_y_stride * pixm->height);
+ cap->stride * pixm->height);
rkisp1_irq_frame_end_enable(cap);
@@ -1092,8 +1100,8 @@ static const struct vb2_ops rkisp1_vb2_ops = {
*/
static const struct v4l2_format_info *
-rkisp1_fill_pixfmt(struct v4l2_pix_format_mplane *pixm,
- enum rkisp1_stream_id id)
+rkisp1_fill_pixfmt(const struct rkisp1_capture *cap,
+ struct v4l2_pix_format_mplane *pixm)
{
struct v4l2_plane_pix_format *plane_y = &pixm->plane_fmt[0];
const struct v4l2_format_info *info;
@@ -1106,10 +1114,13 @@ rkisp1_fill_pixfmt(struct v4l2_pix_format_mplane *pixm,
/*
* The SP supports custom strides, expressed as a number of pixels for
- * the Y plane. Clamp the stride to a reasonable value to avoid integer
- * overflows when calculating the bytesperline and sizeimage values.
+ * the Y plane, and so does the MP in ISP versions that have the
+ * MAIN_STRIDE feature. Clamp the stride to a reasonable value to avoid
+ * integer overflows when calculating the bytesperline and sizeimage
+ * values.
*/
- if (id == RKISP1_SELFPATH)
+ if (cap->id == RKISP1_SELFPATH ||
+ rkisp1_has_feature(cap->rkisp1, MAIN_STRIDE))
stride = clamp(DIV_ROUND_UP(plane_y->bytesperline, info->bpp[0]),
pixm->width, 65536U);
else
@@ -1184,7 +1195,7 @@ static void rkisp1_try_fmt(const struct rkisp1_capture *cap,
pixm->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
pixm->quantization = V4L2_QUANTIZATION_DEFAULT;
- info = rkisp1_fill_pixfmt(pixm, cap->id);
+ info = rkisp1_fill_pixfmt(cap, pixm);
if (fmt_cfg)
*fmt_cfg = fmt;
@@ -1196,12 +1207,9 @@ static void rkisp1_set_fmt(struct rkisp1_capture *cap,
struct v4l2_pix_format_mplane *pixm)
{
rkisp1_try_fmt(cap, pixm, &cap->pix.cfg, &cap->pix.info);
- cap->pix.fmt = *pixm;
- /* SP supports custom stride in number of pixels of the Y plane */
- if (cap->id == RKISP1_SELFPATH)
- cap->sp_y_stride = pixm->plane_fmt[0].bytesperline /
- cap->pix.info->bpp[0];
+ cap->pix.fmt = *pixm;
+ cap->stride = pixm->plane_fmt[0].bytesperline / cap->pix.info->bpp[0];
}
static int rkisp1_try_fmt_vid_cap_mplane(struct file *file, void *fh,
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
index 35efdabf9db1..0da497222579 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
@@ -110,6 +110,7 @@ enum rkisp1_isp_pad {
* enum rkisp1_feature - ISP features
*
* @RKISP1_FEATURE_MIPI_CSI2: The ISP has an internal MIPI CSI-2 receiver
+ * @RKISP1_FEATURE_MAIN_STRIDE: The ISP supports configurable stride on the main path
*
* The ISP features are stored in a bitmask in &rkisp1_info.features and allow
* the driver to implement support for features present in some ISP versions
@@ -117,6 +118,7 @@ enum rkisp1_isp_pad {
*/
enum rkisp1_feature {
RKISP1_FEATURE_MIPI_CSI2 = BIT(0),
+ RKISP1_FEATURE_MAIN_STRIDE = BIT(1),
};
#define rkisp1_has_feature(rkisp1, feature) \
@@ -266,7 +268,7 @@ struct rkisp1_device;
* handler to stop the streaming by waiting on the 'done' wait queue.
* If the irq handler is not called, the stream is stopped by the callback
* after timeout.
- * @sp_y_stride: the selfpath allows to configure a y stride that is longer than the image width.
+ * @stride: the line stride for the first plane, in pixel units
* @buf.lock: lock to protect buf.queue
* @buf.queue: queued buffer list
* @buf.dummy: dummy space to store dropped data
@@ -287,7 +289,7 @@ struct rkisp1_capture {
bool is_streaming;
bool is_stopping;
wait_queue_head_t done;
- unsigned int sp_y_stride;
+ unsigned int stride;
struct {
/* protects queue, curr and next */
spinlock_t lock;
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
index bea69a0d766a..3b19c8411360 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
@@ -207,6 +207,24 @@
#define RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP BIT(1)
#define RKISP1_CIF_MI_XTD_FMT_CTRL_DMA_CB_CR_SWAP BIT(2)
+/* MI_OUTPUT_ALIGN_FORMAT */
+#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_LSB_ALIGNMENT BIT(0)
+#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES BIT(1)
+#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_WORDS BIT(2)
+#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_DWORDS BIT(3)
+#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_SP_BYTE_SWAP_BYTES BIT(4)
+#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_SP_BYTE_SWAP_WORDS BIT(5)
+#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_SP_BYTE_SWAP_DWORDS BIT(6)
+#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_DMA_BYTE_SWAP_BYTES BIT(7)
+#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_DMA_BYTE_SWAP_WORDS BIT(8)
+#define RKISP1_CIF_OUTPUT_ALIGN_FORMAT_DMA_BYTE_SWAP_DWORDS BIT(9)
+
+/* MI_MP_OUTPUT_FIFO_SIZE */
+#define RKISP1_CIF_MI_MP_OUTPUT_FIFO_SIZE_OUTPUT_FIFO_DEPTH_FULL (0 << 0)
+#define RKISP1_CIF_MI_MP_OUTPUT_FIFO_SIZE_OUTPUT_FIFO_DEPTH_HALF (1 << 0)
+#define RKISP1_CIF_MI_MP_OUTPUT_FIFO_SIZE_OUTPUT_FIFO_DEPTH_QUARTER (2 << 0)
+#define RKISP1_CIF_MI_MP_OUTPUT_FIFO_SIZE_OUTPUT_FIFO_DEPTH_EIGHT (3 << 0)
+
/* VI_CCL */
#define RKISP1_CIF_CCL_CIF_CLK_DIS BIT(2)
/* VI_ISP_CLK_CTRL */
@@ -1000,6 +1018,15 @@
#define RKISP1_CIF_MI_SP_CB_BASE_AD_INIT2 (RKISP1_CIF_MI_BASE + 0x00000140)
#define RKISP1_CIF_MI_SP_CR_BASE_AD_INIT2 (RKISP1_CIF_MI_BASE + 0x00000144)
#define RKISP1_CIF_MI_XTD_FORMAT_CTRL (RKISP1_CIF_MI_BASE + 0x00000148)
+#define RKISP1_CIF_MI_MP_HANDSHAKE_0 (RKISP1_CIF_MI_BASE + 0x0000014C)
+#define RKISP1_CIF_MI_MP_Y_LLENGTH (RKISP1_CIF_MI_BASE + 0x00000150)
+#define RKISP1_CIF_MI_MP_Y_SLICE_OFFSET (RKISP1_CIF_MI_BASE + 0x00000154)
+#define RKISP1_CIF_MI_MP_C_SLICE_OFFSET (RKISP1_CIF_MI_BASE + 0x00000158)
+#define RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT (RKISP1_CIF_MI_BASE + 0x0000015C)
+#define RKISP1_CIF_MI_MP_OUTPUT_FIFO_SIZE (RKISP1_CIF_MI_BASE + 0x00000160)
+#define RKISP1_CIF_MI_MP_Y_PIC_WIDTH (RKISP1_CIF_MI_BASE + 0x00000164)
+#define RKISP1_CIF_MI_MP_Y_PIC_HEIGHT (RKISP1_CIF_MI_BASE + 0x00000168)
+#define RKISP1_CIF_MI_MP_Y_PIC_SIZE (RKISP1_CIF_MI_BASE + 0x0000016C)
#define RKISP1_CIF_SMIA_BASE 0x00001a00
#define RKISP1_CIF_SMIA_CTRL (RKISP1_CIF_SMIA_BASE + 0x00000000)
--
Regards,
Laurent Pinchart
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v13 03/12] media: rkisp1: Support devices lacking self path
2024-02-18 20:43 [PATCH v13 00/12] media: rkisp1: Add support for i.MX8MP Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 01/12] media: rkisp1: Add and use rkisp1_has_feature() macro Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 02/12] media: rkisp1: Support setting memory stride for main path Laurent Pinchart
@ 2024-02-18 20:43 ` Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 04/12] media: rkisp1: Support devices lacking dual crop Laurent Pinchart
` (9 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Laurent Pinchart @ 2024-02-18 20:43 UTC (permalink / raw)
To: linux-media
Cc: Paul Elder, Adam Ford, Alexander Stein, Dafna Hirschfeld,
Heiko Stuebner, Helen Koike, Kieran Bingham, Tomi Valkeinen,
linux-rockchip
From: Paul Elder <paul.elder@ideasonboard.com>
Some versions of the ISP supported by the rkisp1 driver, such as the ISP
in the i.MX8MP, lack the self path. Support those ISP versions by adding
a self path feature flag, and massage the rest of the driver to support
the lack of a self path.
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
Changes since v3:
- Document the feature bit
- Reorder commit
Changes since v2:
- Simplify rkisp1_path_count()
- Use the rkisp1_has_feature() macro
---
.../platform/rockchip/rkisp1/rkisp1-capture.c | 9 ++++++---
.../platform/rockchip/rkisp1/rkisp1-common.h | 15 +++++++++++++++
.../media/platform/rockchip/rkisp1/rkisp1-dev.c | 9 ++++++---
.../platform/rockchip/rkisp1/rkisp1-resizer.c | 6 ++++--
4 files changed, 31 insertions(+), 8 deletions(-)
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
index 3c24c8c7ad68..7d56874c3106 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
@@ -730,6 +730,7 @@ irqreturn_t rkisp1_capture_isr(int irq, void *ctx)
{
struct device *dev = ctx;
struct rkisp1_device *rkisp1 = dev_get_drvdata(dev);
+ unsigned int dev_count = rkisp1_path_count(rkisp1);
unsigned int i;
u32 status;
@@ -739,7 +740,7 @@ irqreturn_t rkisp1_capture_isr(int irq, void *ctx)
rkisp1_write(rkisp1, RKISP1_CIF_MI_ICR, status);
- for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); ++i) {
+ for (i = 0; i < dev_count; ++i) {
struct rkisp1_capture *cap = &rkisp1->capture_devs[i];
if (!(status & RKISP1_CIF_MI_FRAME(cap)))
@@ -896,6 +897,7 @@ static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap)
{
struct rkisp1_device *rkisp1 = cap->rkisp1;
struct rkisp1_capture *other = &rkisp1->capture_devs[cap->id ^ 1];
+ bool has_self_path = rkisp1_has_feature(rkisp1, SELF_PATH);
cap->ops->set_data_path(cap);
cap->ops->config(cap);
@@ -913,7 +915,7 @@ static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap)
* This's also required because the second FE maybe corrupt
* especially when run at 120fps.
*/
- if (!other->is_streaming) {
+ if (!has_self_path || !other->is_streaming) {
/* force cfg update */
rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT,
RKISP1_CIF_MI_INIT_SOFT_UPD);
@@ -1506,10 +1508,11 @@ rkisp1_capture_init(struct rkisp1_device *rkisp1, enum rkisp1_stream_id id)
int rkisp1_capture_devs_register(struct rkisp1_device *rkisp1)
{
+ unsigned int dev_count = rkisp1_path_count(rkisp1);
unsigned int i;
int ret;
- for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); i++) {
+ for (i = 0; i < dev_count; i++) {
struct rkisp1_capture *cap = &rkisp1->capture_devs[i];
rkisp1_capture_init(rkisp1, i);
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
index 0da497222579..998fe45f5df3 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
@@ -111,6 +111,7 @@ enum rkisp1_isp_pad {
*
* @RKISP1_FEATURE_MIPI_CSI2: The ISP has an internal MIPI CSI-2 receiver
* @RKISP1_FEATURE_MAIN_STRIDE: The ISP supports configurable stride on the main path
+ * @RKISP1_FEATURE_SELF_PATH: The ISP has a self path
*
* The ISP features are stored in a bitmask in &rkisp1_info.features and allow
* the driver to implement support for features present in some ISP versions
@@ -119,6 +120,7 @@ enum rkisp1_isp_pad {
enum rkisp1_feature {
RKISP1_FEATURE_MIPI_CSI2 = BIT(0),
RKISP1_FEATURE_MAIN_STRIDE = BIT(1),
+ RKISP1_FEATURE_SELF_PATH = BIT(2),
};
#define rkisp1_has_feature(rkisp1, feature) \
@@ -529,6 +531,19 @@ int rkisp1_cap_enum_mbus_codes(struct rkisp1_capture *cap,
*/
const struct rkisp1_mbus_info *rkisp1_mbus_info_get_by_index(unsigned int index);
+/*
+ * rkisp1_path_count - Return the number of paths supported by the device
+ *
+ * Some devices only have a main path, while other device have both a main path
+ * and a self path. This function returns the number of paths that this device
+ * has, based on the feature flags. It should be used insted of checking
+ * ARRAY_SIZE of capture_devs/resizer_devs.
+ */
+static inline unsigned int rkisp1_path_count(struct rkisp1_device *rkisp1)
+{
+ return rkisp1_has_feature(rkisp1, SELF_PATH) ? 2 : 1;
+}
+
/*
* rkisp1_sd_adjust_crop_rect - adjust a rectangle to fit into another rectangle.
*
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
index 8c1040ca02a3..67a5c84ce117 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
@@ -336,6 +336,7 @@ static const struct dev_pm_ops rkisp1_pm_ops = {
static int rkisp1_create_links(struct rkisp1_device *rkisp1)
{
+ unsigned int dev_count = rkisp1_path_count(rkisp1);
unsigned int i;
int ret;
@@ -351,7 +352,7 @@ static int rkisp1_create_links(struct rkisp1_device *rkisp1)
}
/* create ISP->RSZ->CAP links */
- for (i = 0; i < 2; i++) {
+ for (i = 0; i < dev_count; i++) {
struct media_entity *resizer =
&rkisp1->resizer_devs[i].sd.entity;
struct media_entity *capture =
@@ -483,7 +484,8 @@ static const struct rkisp1_info px30_isp_info = {
.isrs = px30_isp_isrs,
.isr_size = ARRAY_SIZE(px30_isp_isrs),
.isp_ver = RKISP1_V12,
- .features = RKISP1_FEATURE_MIPI_CSI2,
+ .features = RKISP1_FEATURE_MIPI_CSI2
+ | RKISP1_FEATURE_SELF_PATH,
};
static const char * const rk3399_isp_clks[] = {
@@ -502,7 +504,8 @@ static const struct rkisp1_info rk3399_isp_info = {
.isrs = rk3399_isp_isrs,
.isr_size = ARRAY_SIZE(rk3399_isp_isrs),
.isp_ver = RKISP1_V10,
- .features = RKISP1_FEATURE_MIPI_CSI2,
+ .features = RKISP1_FEATURE_MIPI_CSI2
+ | RKISP1_FEATURE_SELF_PATH,
};
static const struct of_device_id rkisp1_of_match[] = {
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c
index a8e377701302..dd77a31e6014 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c
@@ -631,6 +631,7 @@ static int rkisp1_rsz_s_stream(struct v4l2_subdev *sd, int enable)
struct rkisp1_device *rkisp1 = rsz->rkisp1;
struct rkisp1_capture *other = &rkisp1->capture_devs[rsz->id ^ 1];
enum rkisp1_shadow_regs_when when = RKISP1_SHADOW_REGS_SYNC;
+ bool has_self_path = rkisp1_has_feature(rkisp1, SELF_PATH);
struct v4l2_subdev_state *sd_state;
if (!enable) {
@@ -639,7 +640,7 @@ static int rkisp1_rsz_s_stream(struct v4l2_subdev *sd, int enable)
return 0;
}
- if (other->is_streaming)
+ if (has_self_path && other->is_streaming)
when = RKISP1_SHADOW_REGS_ASYNC;
sd_state = v4l2_subdev_lock_and_get_active_state(sd);
@@ -731,10 +732,11 @@ static int rkisp1_rsz_register(struct rkisp1_resizer *rsz)
int rkisp1_resizer_devs_register(struct rkisp1_device *rkisp1)
{
+ unsigned int dev_count = rkisp1_path_count(rkisp1);
unsigned int i;
int ret;
- for (i = 0; i < ARRAY_SIZE(rkisp1->resizer_devs); i++) {
+ for (i = 0; i < dev_count; i++) {
struct rkisp1_resizer *rsz = &rkisp1->resizer_devs[i];
rsz->rkisp1 = rkisp1;
--
Regards,
Laurent Pinchart
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v13 04/12] media: rkisp1: Support devices lacking dual crop
2024-02-18 20:43 [PATCH v13 00/12] media: rkisp1: Add support for i.MX8MP Laurent Pinchart
` (2 preceding siblings ...)
2024-02-18 20:43 ` [PATCH v13 03/12] media: rkisp1: Support devices lacking self path Laurent Pinchart
@ 2024-02-18 20:43 ` Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 05/12] dt-bindings: media: rkisp1: Add i.MX8MP ISP to compatible Laurent Pinchart
` (8 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Laurent Pinchart @ 2024-02-18 20:43 UTC (permalink / raw)
To: linux-media
Cc: Paul Elder, Adam Ford, Alexander Stein, Dafna Hirschfeld,
Heiko Stuebner, Helen Koike, Kieran Bingham, Tomi Valkeinen,
linux-rockchip
From: Paul Elder <paul.elder@ideasonboard.com>
Some versions of the ISP supported by the rkisp1 driver, such as the ISP
in the i.MX8MP, lack the dual crop registers and don't support cropping
at the resizer input. They instead rely on cropping in the Image
Stabilization module, at the output of the ISP, to modify the resizer
input size and implement digital zoom.
Add a dual crop feature flag to distinguish the versions of the ISP that
support dual crop from those that don't, and make sure that the sink
crop is set to the sink format when dual crop is not supported.
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
Changes since v12:
- Update comment in rkisp1_rsz_set_sink_crop()
Changes since v6:
- Remove mention of moving resizer input crop to image stabilizer from
commit message
- Make sure the sink crop is set to the sink format when dual crop is
not supported
---
.../media/platform/rockchip/rkisp1/rkisp1-common.h | 2 ++
drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c | 6 ++++--
.../media/platform/rockchip/rkisp1/rkisp1-resizer.c | 13 ++++++++-----
3 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
index 998fe45f5df3..857fea1d079b 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
@@ -112,6 +112,7 @@ enum rkisp1_isp_pad {
* @RKISP1_FEATURE_MIPI_CSI2: The ISP has an internal MIPI CSI-2 receiver
* @RKISP1_FEATURE_MAIN_STRIDE: The ISP supports configurable stride on the main path
* @RKISP1_FEATURE_SELF_PATH: The ISP has a self path
+ * @RKISP1_FEATURE_DUAL_CROP: The ISP has the dual crop block at the resizer input
*
* The ISP features are stored in a bitmask in &rkisp1_info.features and allow
* the driver to implement support for features present in some ISP versions
@@ -121,6 +122,7 @@ enum rkisp1_feature {
RKISP1_FEATURE_MIPI_CSI2 = BIT(0),
RKISP1_FEATURE_MAIN_STRIDE = BIT(1),
RKISP1_FEATURE_SELF_PATH = BIT(2),
+ RKISP1_FEATURE_DUAL_CROP = BIT(3),
};
#define rkisp1_has_feature(rkisp1, feature) \
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
index 67a5c84ce117..5a3ad2c3347e 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
@@ -485,7 +485,8 @@ static const struct rkisp1_info px30_isp_info = {
.isr_size = ARRAY_SIZE(px30_isp_isrs),
.isp_ver = RKISP1_V12,
.features = RKISP1_FEATURE_MIPI_CSI2
- | RKISP1_FEATURE_SELF_PATH,
+ | RKISP1_FEATURE_SELF_PATH
+ | RKISP1_FEATURE_DUAL_CROP,
};
static const char * const rk3399_isp_clks[] = {
@@ -505,7 +506,8 @@ static const struct rkisp1_info rk3399_isp_info = {
.isr_size = ARRAY_SIZE(rk3399_isp_isrs),
.isp_ver = RKISP1_V10,
.features = RKISP1_FEATURE_MIPI_CSI2
- | RKISP1_FEATURE_SELF_PATH,
+ | RKISP1_FEATURE_SELF_PATH
+ | RKISP1_FEATURE_DUAL_CROP,
};
static const struct of_device_id rkisp1_of_match[] = {
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c
index dd77a31e6014..6f3931ca5b51 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c
@@ -444,11 +444,12 @@ static void rkisp1_rsz_set_sink_crop(struct rkisp1_resizer *rsz,
sink_fmt = v4l2_subdev_state_get_format(sd_state, RKISP1_RSZ_PAD_SINK);
sink_crop = v4l2_subdev_state_get_crop(sd_state, RKISP1_RSZ_PAD_SINK);
- /* Not crop for MP bayer raw data */
+ /* Not crop for MP bayer raw data, or for devices lacking dual crop. */
mbus_info = rkisp1_mbus_info_get_by_code(sink_fmt->code);
- if (rsz->id == RKISP1_MAINPATH &&
- mbus_info->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
+ if ((rsz->id == RKISP1_MAINPATH &&
+ mbus_info->pixel_enc == V4L2_PIXEL_ENC_BAYER) ||
+ !rkisp1_has_feature(rsz->rkisp1, DUAL_CROP)) {
sink_crop->left = 0;
sink_crop->top = 0;
sink_crop->width = sink_fmt->width;
@@ -635,7 +636,8 @@ static int rkisp1_rsz_s_stream(struct v4l2_subdev *sd, int enable)
struct v4l2_subdev_state *sd_state;
if (!enable) {
- rkisp1_dcrop_disable(rsz, RKISP1_SHADOW_REGS_ASYNC);
+ if (rkisp1_has_feature(rkisp1, DUAL_CROP))
+ rkisp1_dcrop_disable(rsz, RKISP1_SHADOW_REGS_ASYNC);
rkisp1_rsz_disable(rsz, RKISP1_SHADOW_REGS_ASYNC);
return 0;
}
@@ -646,7 +648,8 @@ static int rkisp1_rsz_s_stream(struct v4l2_subdev *sd, int enable)
sd_state = v4l2_subdev_lock_and_get_active_state(sd);
rkisp1_rsz_config(rsz, sd_state, when);
- rkisp1_dcrop_config(rsz, sd_state);
+ if (rkisp1_has_feature(rkisp1, DUAL_CROP))
+ rkisp1_dcrop_config(rsz, sd_state);
v4l2_subdev_unlock_state(sd_state);
--
Regards,
Laurent Pinchart
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v13 05/12] dt-bindings: media: rkisp1: Add i.MX8MP ISP to compatible
2024-02-18 20:43 [PATCH v13 00/12] media: rkisp1: Add support for i.MX8MP Laurent Pinchart
` (3 preceding siblings ...)
2024-02-18 20:43 ` [PATCH v13 04/12] media: rkisp1: Support devices lacking dual crop Laurent Pinchart
@ 2024-02-18 20:43 ` Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 06/12] media: rkisp1: Add version enum for i.MX8MP ISP Laurent Pinchart
` (7 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Laurent Pinchart @ 2024-02-18 20:43 UTC (permalink / raw)
To: linux-media
Cc: Paul Elder, Adam Ford, Alexander Stein, Conor Dooley,
Dafna Hirschfeld, Heiko Stuebner, Helen Koike, Kieran Bingham,
Krzysztof Kozlowski, Rob Herring, Tomi Valkeinen, devicetree,
linux-rockchip
From: Paul Elder <paul.elder@ideasonboard.com>
The i.MX8MP ISP is compatbile with the rkisp1 driver. Add it to the list
of compatible strings. While at it, expand on the description of the
clocks to make it clear which clock in the i.MX8MP ISP they map to,
based on the names from the datasheet.
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Tested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
Changes since v1:
- Add fsl,blk-ctrl property
- Make iommus, phys and phy-names conditional on compatible
---
.../bindings/media/rockchip-isp1.yaml | 37 ++++++++++++++++---
1 file changed, 31 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/rockchip-isp1.yaml b/Documentation/devicetree/bindings/media/rockchip-isp1.yaml
index afcaa427d48b..6be00aca4181 100644
--- a/Documentation/devicetree/bindings/media/rockchip-isp1.yaml
+++ b/Documentation/devicetree/bindings/media/rockchip-isp1.yaml
@@ -16,6 +16,7 @@ description: |
properties:
compatible:
enum:
+ - fsl,imx8mp-isp
- rockchip,px30-cif-isp
- rockchip,rk3399-cif-isp
@@ -36,9 +37,9 @@ properties:
minItems: 3
items:
# isp0 and isp1
- - description: ISP clock
- - description: ISP AXI clock
- - description: ISP AHB clock
+ - description: ISP clock (for imx8mp, clk)
+ - description: ISP AXI clock (for imx8mp, m_hclk)
+ - description: ISP AHB clock (for imx8mp, hclk)
# only for isp1
- description: ISP Pixel clock
@@ -52,6 +53,13 @@ properties:
# only for isp1
- const: pclk
+ fsl,blk-ctrl:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+ description:
+ A phandle to the media block control for the ISP, followed by a cell
+ containing the index of the gasket.
+
iommus:
maxItems: 1
@@ -113,9 +121,6 @@ required:
- interrupts
- clocks
- clock-names
- - iommus
- - phys
- - phy-names
- power-domains
- ports
@@ -143,6 +148,26 @@ allOf:
required:
- interrupt-names
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8mp-isp
+ then:
+ properties:
+ iommus: false
+ phys: false
+ phy-names: false
+ required:
+ - fsl,blk-ctrl
+ else:
+ properties:
+ fsl,blk-ctrl: false
+ required:
+ - iommus
+ - phys
+ - phy-names
+
additionalProperties: false
examples:
--
Regards,
Laurent Pinchart
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v13 06/12] media: rkisp1: Add version enum for i.MX8MP ISP
2024-02-18 20:43 [PATCH v13 00/12] media: rkisp1: Add support for i.MX8MP Laurent Pinchart
` (4 preceding siblings ...)
2024-02-18 20:43 ` [PATCH v13 05/12] dt-bindings: media: rkisp1: Add i.MX8MP ISP to compatible Laurent Pinchart
@ 2024-02-18 20:43 ` Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 07/12] media: rkisp1: Configure gasket on i.MX8MP Laurent Pinchart
` (6 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Laurent Pinchart @ 2024-02-18 20:43 UTC (permalink / raw)
To: linux-media
Cc: Paul Elder, Adam Ford, Alexander Stein, Dafna Hirschfeld,
Heiko Stuebner, Helen Koike, Kieran Bingham, Tomi Valkeinen,
linux-rockchip
From: Paul Elder <paul.elder@ideasonboard.com>
The NXP i.MX8MP integrates an ISP8000Nano from VeriSilicon, which is a
derivative of the ISP found in earlier Rockchip SoCs. It isn't clear at
which exact point the two product lines have diverged, and there is no
public information regarding the version numbering scheme of the
ISP8000Nano. Nonetheless, this ISP is close enough to the V10 found in
the RK3399 to be supported by the same driver.
Add an entry for the ISP found in the NXP i.MX8MP to the version enum.
Given the lack of information on the version numbering scheme, and on
whether or not the version in the i.MX8MP is identical to other
ISP8000Nano versions or has been customized for the i.MX8MP, depart from
the number-based versions and name this new version V_IMX8MP.
Update comments for the other versions and for relevant parameters
blocks to clearly indicate the size of grids and histogram for the
different versions.
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
Changes since v12:
- Update comments
New in v12:
- Split out from "media: rkisp1: Add match data for i.MX8MP ISP"
- Changed the version enum name
---
include/uapi/linux/rkisp1-config.h | 50 ++++++++++++++++--------------
1 file changed, 27 insertions(+), 23 deletions(-)
diff --git a/include/uapi/linux/rkisp1-config.h b/include/uapi/linux/rkisp1-config.h
index 730673ecc63d..6eeaf8bf2362 100644
--- a/include/uapi/linux/rkisp1-config.h
+++ b/include/uapi/linux/rkisp1-config.h
@@ -175,16 +175,21 @@
/**
* enum rkisp1_cif_isp_version - ISP variants
*
- * @RKISP1_V10: used at least in rk3288 and rk3399
- * @RKISP1_V11: declared in the original vendor code, but not used
- * @RKISP1_V12: used at least in rk3326 and px30
- * @RKISP1_V13: used at least in rk1808
+ * @RKISP1_V10: Used at least in RK3288 and RK3399.
+ * @RKISP1_V11: Declared in the original vendor code, but not used. Same number
+ * of entries in grids and histogram as v10.
+ * @RKISP1_V12: Used at least in RK3326 and PX30.
+ * @RKISP1_V13: Used at least in RK1808. Same number of entries in grids and
+ * histogram as v12.
+ * @RKISP1_V_IMX8MP: Used in at least i.MX8MP. Same number of entries in grids
+ * and histogram as v10.
*/
enum rkisp1_cif_isp_version {
RKISP1_V10 = 10,
RKISP1_V11,
RKISP1_V12,
RKISP1_V13,
+ RKISP1_V_IMX8MP,
};
enum rkisp1_cif_isp_histogram_mode {
@@ -584,10 +589,9 @@ enum rkisp1_cif_isp_goc_mode {
* as is reported by the hw_revision field of the struct media_device_info
* that is returned by ioctl MEDIA_IOC_DEVICE_INFO.
*
- * Versions <= V11 have RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES_V10
- * entries, versions >= V12 have RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES_V12
- * entries. RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES is equal to the maximum
- * of the two.
+ * V10 has RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES_V10 entries, V12 has
+ * RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES_V12 entries.
+ * RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES is equal to the maximum of the two.
*/
struct rkisp1_cif_isp_goc_config {
__u32 mode;
@@ -607,10 +611,10 @@ struct rkisp1_cif_isp_goc_config {
* as is reported by the hw_revision field of the struct media_device_info
* that is returned by ioctl MEDIA_IOC_DEVICE_INFO.
*
- * Versions <= V11 have RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE_V10
- * entries, versions >= V12 have RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE_V12
- * entries. RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE is equal to the maximum
- * of the two.
+ * V10 has RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE_V10 entries, V12 has
+ * RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE_V12 entries.
+ * RKISP1_CIF_ISP_HISTOGRAM_WEIGHT_GRIDS_SIZE is equal to the maximum of the
+ * two.
*/
struct rkisp1_cif_isp_hst_config {
__u32 mode;
@@ -902,9 +906,9 @@ struct rkisp1_cif_isp_bls_meas_val {
* as is reported by the hw_revision field of the struct media_device_info
* that is returned by ioctl MEDIA_IOC_DEVICE_INFO.
*
- * Versions <= V11 have RKISP1_CIF_ISP_AE_MEAN_MAX_V10 entries,
- * versions >= V12 have RKISP1_CIF_ISP_AE_MEAN_MAX_V12 entries.
- * RKISP1_CIF_ISP_AE_MEAN_MAX is equal to the maximum of the two.
+ * V10 has RKISP1_CIF_ISP_AE_MEAN_MAX_V10 entries, V12 has
+ * RKISP1_CIF_ISP_AE_MEAN_MAX_V12 entries. RKISP1_CIF_ISP_AE_MEAN_MAX is equal
+ * to the maximum of the two.
*
* Image is divided into 5x5 blocks on V10 and 9x9 blocks on V12.
*/
@@ -944,21 +948,21 @@ struct rkisp1_cif_isp_af_stat {
* integer part.
*
* The window of the measurements area is divided to 5x5 sub-windows for
- * V10/V11 and to 9x9 sub-windows for V12. The histogram is then computed for
- * each sub-window independently and the final result is a weighted average of
- * the histogram measurements on all sub-windows. The window of the
- * measurements area and the weight of each sub-window are configurable using
+ * V10 and to 9x9 sub-windows for V12. The histogram is then computed for each
+ * sub-window independently and the final result is a weighted average of the
+ * histogram measurements on all sub-windows. The window of the measurements
+ * area and the weight of each sub-window are configurable using
* struct @rkisp1_cif_isp_hst_config.
*
- * The histogram contains 16 bins in V10/V11 and 32 bins in V12/V13.
+ * The histogram contains 16 bins in V10 and 32 bins in V12.
*
* The number of entries of @hist_bins depends on the hardware revision
* as is reported by the hw_revision field of the struct media_device_info
* that is returned by ioctl MEDIA_IOC_DEVICE_INFO.
*
- * Versions <= V11 have RKISP1_CIF_ISP_HIST_BIN_N_MAX_V10 entries,
- * versions >= V12 have RKISP1_CIF_ISP_HIST_BIN_N_MAX_V12 entries.
- * RKISP1_CIF_ISP_HIST_BIN_N_MAX is equal to the maximum of the two.
+ * V10 has RKISP1_CIF_ISP_HIST_BIN_N_MAX_V10 entries, V12 has
+ * RKISP1_CIF_ISP_HIST_BIN_N_MAX_V12 entries. RKISP1_CIF_ISP_HIST_BIN_N_MAX is
+ * equal to the maximum of the two.
*/
struct rkisp1_cif_isp_hist_stat {
__u32 hist_bins[RKISP1_CIF_ISP_HIST_BIN_N_MAX];
--
Regards,
Laurent Pinchart
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v13 07/12] media: rkisp1: Configure gasket on i.MX8MP
2024-02-18 20:43 [PATCH v13 00/12] media: rkisp1: Add support for i.MX8MP Laurent Pinchart
` (5 preceding siblings ...)
2024-02-18 20:43 ` [PATCH v13 06/12] media: rkisp1: Add version enum for i.MX8MP ISP Laurent Pinchart
@ 2024-02-18 20:43 ` Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 08/12] media: rkisp1: Support i.MX8MP's 34-bit DMA Laurent Pinchart
` (5 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Laurent Pinchart @ 2024-02-18 20:43 UTC (permalink / raw)
To: linux-media
Cc: Adam Ford, Alexander Stein, Dafna Hirschfeld, Heiko Stuebner,
Helen Koike, Kieran Bingham, Paul Elder, Tomi Valkeinen,
linux-rockchip
The i.MX8MP has a gasket between the CSI-2 receiver and the ISP.
Configure and enable it when starting the ISP, and disable it when
stopping.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
---
.../platform/rockchip/rkisp1/rkisp1-common.h | 5 +
.../platform/rockchip/rkisp1/rkisp1-dev.c | 16 +++
.../platform/rockchip/rkisp1/rkisp1-isp.c | 131 +++++++++++++++++-
3 files changed, 149 insertions(+), 3 deletions(-)
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
index 857fea1d079b..070317196aa1 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
@@ -24,6 +24,7 @@
#include "rkisp1-regs.h"
struct dentry;
+struct regmap;
/*
* flags on the 'direction' field in struct rkisp1_mbus_info' that indicate
@@ -444,6 +445,8 @@ struct rkisp1_debug {
* @dev: a pointer to the struct device
* @clk_size: number of clocks
* @clks: array of clocks
+ * @gasket: the gasket - i.MX8MP only
+ * @gasket_id: the gasket ID (0 or 1) - i.MX8MP only
* @v4l2_dev: v4l2_device variable
* @media_dev: media_device variable
* @notifier: a notifier to register on the v4l2-async API to be notified on the sensor
@@ -465,6 +468,8 @@ struct rkisp1_device {
struct device *dev;
unsigned int clk_size;
struct clk_bulk_data clks[RKISP1_MAX_BUS_CLK];
+ struct regmap *gasket;
+ unsigned int gasket_id;
struct v4l2_device v4l2_dev;
struct media_device media_dev;
struct v4l2_async_notifier notifier;
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
index 5a3ad2c3347e..885339159763 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
@@ -10,6 +10,7 @@
#include <linux/clk.h>
#include <linux/interrupt.h>
+#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_graph.h>
@@ -579,6 +580,21 @@ static int rkisp1_probe(struct platform_device *pdev)
return ret;
rkisp1->clk_size = info->clk_size;
+ if (info->isp_ver == RKISP1_V_IMX8MP) {
+ unsigned int id;
+
+ rkisp1->gasket = syscon_regmap_lookup_by_phandle_args(dev->of_node,
+ "fsl,blk-ctrl",
+ 1, &id);
+ if (IS_ERR(rkisp1->gasket)) {
+ ret = PTR_ERR(rkisp1->gasket);
+ dev_err(dev, "failed to get gasket: %d\n", ret);
+ return ret;
+ }
+
+ rkisp1->gasket_id = id;
+ }
+
pm_runtime_enable(&pdev->dev);
ret = pm_runtime_resume_and_get(&pdev->dev);
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
index f00873d31c42..f3552e1a88dd 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
@@ -10,6 +10,7 @@
#include <linux/iopoll.h>
#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
#include <linux/videodev2.h>
#include <linux/vmalloc.h>
@@ -53,6 +54,115 @@
* +---------------------------------------------------------+
*/
+/* -----------------------------------------------------------------------------
+ * Media block control (i.MX8MP only)
+ */
+
+#define ISP_DEWARP_CONTROL 0x0138
+
+#define ISP_DEWARP_CONTROL_MIPI_CSI2_HS_POLARITY BIT(22)
+#define ISP_DEWARP_CONTROL_MIPI_CSI2_VS_SEL_RISING (0 << 20)
+#define ISP_DEWARP_CONTROL_MIPI_CSI2_VS_SEL_NEGATIVE (1 << 20)
+#define ISP_DEWARP_CONTROL_MIPI_CSI2_VS_SEL_POSITIVE (2 << 20)
+#define ISP_DEWARP_CONTROL_MIPI_CSI2_VS_SEL_FALLING (3 << 20)
+#define ISP_DEWARP_CONTROL_MIPI_CSI2_VS_SEL_MASK GENMASK(21, 20)
+#define ISP_DEWARP_CONTROL_MIPI_ISP2_LEFT_JUST_MODE BIT(19)
+#define ISP_DEWARP_CONTROL_MIPI_ISP2_DATA_TYPE(dt) ((dt) << 13)
+#define ISP_DEWARP_CONTROL_MIPI_ISP2_DATA_TYPE_MASK GENMASK(18, 13)
+
+#define ISP_DEWARP_CONTROL_MIPI_CSI1_HS_POLARITY BIT(12)
+#define ISP_DEWARP_CONTROL_MIPI_CSI1_VS_SEL_RISING (0 << 10)
+#define ISP_DEWARP_CONTROL_MIPI_CSI1_VS_SEL_NEGATIVE (1 << 10)
+#define ISP_DEWARP_CONTROL_MIPI_CSI1_VS_SEL_POSITIVE (2 << 10)
+#define ISP_DEWARP_CONTROL_MIPI_CSI1_VS_SEL_FALLING (3 << 10)
+#define ISP_DEWARP_CONTROL_MIPI_CSI1_VS_SEL_MASK GENMASK(11, 10)
+#define ISP_DEWARP_CONTROL_MIPI_ISP1_LEFT_JUST_MODE BIT(9)
+#define ISP_DEWARP_CONTROL_MIPI_ISP1_DATA_TYPE(dt) ((dt) << 3)
+#define ISP_DEWARP_CONTROL_MIPI_ISP1_DATA_TYPE_MASK GENMASK(8, 3)
+
+#define ISP_DEWARP_CONTROL_GPR_ISP_1_DISABLE BIT(1)
+#define ISP_DEWARP_CONTROL_GPR_ISP_0_DISABLE BIT(0)
+
+static int rkisp1_gasket_enable(struct rkisp1_device *rkisp1,
+ struct media_pad *source)
+{
+ struct v4l2_subdev *source_sd;
+ struct v4l2_mbus_frame_desc fd;
+ unsigned int dt;
+ u32 mask;
+ u32 val;
+ int ret;
+
+ /*
+ * Configure and enable the gasket with the CSI-2 data type. Set the
+ * vsync polarity as active high, as that is what the ISP is configured
+ * to expect in ISP_ACQ_PROP. Enable left justification, as the i.MX8MP
+ * ISP has a 16-bit wide input and expects data to be left-aligned.
+ */
+
+ source_sd = media_entity_to_v4l2_subdev(source->entity);
+ ret = v4l2_subdev_call(source_sd, pad, get_frame_desc,
+ source->index, &fd);
+ if (ret) {
+ dev_err(rkisp1->dev,
+ "failed to get frame descriptor from '%s':%u: %d\n",
+ source_sd->name, 0, ret);
+ return ret;
+ }
+
+ if (fd.num_entries != 1) {
+ dev_err(rkisp1->dev, "invalid frame descriptor for '%s':%u\n",
+ source_sd->name, 0);
+ return -EINVAL;
+ }
+
+ dt = fd.entry[0].bus.csi2.dt;
+
+ if (rkisp1->gasket_id == 0) {
+ mask = ISP_DEWARP_CONTROL_MIPI_CSI1_HS_POLARITY
+ | ISP_DEWARP_CONTROL_MIPI_CSI1_VS_SEL_MASK
+ | ISP_DEWARP_CONTROL_MIPI_ISP1_LEFT_JUST_MODE
+ | ISP_DEWARP_CONTROL_MIPI_ISP1_DATA_TYPE_MASK
+ | ISP_DEWARP_CONTROL_GPR_ISP_0_DISABLE;
+ val = ISP_DEWARP_CONTROL_MIPI_CSI1_VS_SEL_POSITIVE
+ | ISP_DEWARP_CONTROL_MIPI_ISP1_LEFT_JUST_MODE
+ | ISP_DEWARP_CONTROL_MIPI_ISP1_DATA_TYPE(dt);
+ } else {
+ mask = ISP_DEWARP_CONTROL_MIPI_CSI2_HS_POLARITY
+ | ISP_DEWARP_CONTROL_MIPI_CSI2_VS_SEL_MASK
+ | ISP_DEWARP_CONTROL_MIPI_ISP2_LEFT_JUST_MODE
+ | ISP_DEWARP_CONTROL_MIPI_ISP2_DATA_TYPE_MASK
+ | ISP_DEWARP_CONTROL_GPR_ISP_1_DISABLE;
+ val = ISP_DEWARP_CONTROL_MIPI_CSI2_VS_SEL_POSITIVE
+ | ISP_DEWARP_CONTROL_MIPI_ISP2_LEFT_JUST_MODE
+ | ISP_DEWARP_CONTROL_MIPI_ISP2_DATA_TYPE(dt);
+ }
+
+ regmap_update_bits(rkisp1->gasket, ISP_DEWARP_CONTROL, mask, val);
+
+ return 0;
+}
+
+static void rkisp1_gasket_disable(struct rkisp1_device *rkisp1)
+{
+ u32 mask;
+ u32 val;
+
+ if (rkisp1->gasket_id == 1) {
+ mask = ISP_DEWARP_CONTROL_MIPI_ISP2_LEFT_JUST_MODE
+ | ISP_DEWARP_CONTROL_MIPI_ISP2_DATA_TYPE_MASK
+ | ISP_DEWARP_CONTROL_GPR_ISP_1_DISABLE;
+ val = ISP_DEWARP_CONTROL_GPR_ISP_1_DISABLE;
+ } else {
+ mask = ISP_DEWARP_CONTROL_MIPI_ISP1_LEFT_JUST_MODE
+ | ISP_DEWARP_CONTROL_MIPI_ISP1_DATA_TYPE_MASK
+ | ISP_DEWARP_CONTROL_GPR_ISP_0_DISABLE;
+ val = ISP_DEWARP_CONTROL_GPR_ISP_0_DISABLE;
+ }
+
+ regmap_update_bits(rkisp1->gasket, ISP_DEWARP_CONTROL, mask, val);
+}
+
/* ----------------------------------------------------------------------------
* Camera Interface registers configurations
*/
@@ -291,6 +401,9 @@ static void rkisp1_isp_stop(struct rkisp1_isp *isp)
RKISP1_CIF_VI_IRCL_MIPI_SW_RST |
RKISP1_CIF_VI_IRCL_ISP_SW_RST);
rkisp1_write(rkisp1, RKISP1_CIF_VI_IRCL, 0x0);
+
+ if (rkisp1->info->isp_ver == RKISP1_V_IMX8MP)
+ rkisp1_gasket_disable(rkisp1);
}
static void rkisp1_config_clk(struct rkisp1_isp *isp)
@@ -315,16 +428,24 @@ static void rkisp1_config_clk(struct rkisp1_isp *isp)
}
}
-static void rkisp1_isp_start(struct rkisp1_isp *isp,
- struct v4l2_subdev_state *sd_state)
+static int rkisp1_isp_start(struct rkisp1_isp *isp,
+ struct v4l2_subdev_state *sd_state,
+ struct media_pad *source)
{
struct rkisp1_device *rkisp1 = isp->rkisp1;
const struct v4l2_mbus_framefmt *src_fmt;
const struct rkisp1_mbus_info *src_info;
u32 val;
+ int ret;
rkisp1_config_clk(isp);
+ if (rkisp1->info->isp_ver == RKISP1_V_IMX8MP) {
+ ret = rkisp1_gasket_enable(rkisp1, source);
+ if (ret)
+ return ret;
+ }
+
/* Activate ISP */
val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL);
val |= RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD |
@@ -338,6 +459,8 @@ static void rkisp1_isp_start(struct rkisp1_isp *isp,
if (src_info->pixel_enc != V4L2_PIXEL_ENC_BAYER)
rkisp1_params_post_configure(&rkisp1->params);
+
+ return 0;
}
/* ----------------------------------------------------------------------------
@@ -848,7 +971,9 @@ static int rkisp1_isp_s_stream(struct v4l2_subdev *sd, int enable)
if (ret)
goto out_unlock;
- rkisp1_isp_start(isp, sd_state);
+ ret = rkisp1_isp_start(isp, sd_state, source_pad);
+ if (ret)
+ goto out_unlock;
ret = v4l2_subdev_call(rkisp1->source, video, s_stream, true);
if (ret) {
--
Regards,
Laurent Pinchart
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v13 08/12] media: rkisp1: Support i.MX8MP's 34-bit DMA
2024-02-18 20:43 [PATCH v13 00/12] media: rkisp1: Add support for i.MX8MP Laurent Pinchart
` (6 preceding siblings ...)
2024-02-18 20:43 ` [PATCH v13 07/12] media: rkisp1: Configure gasket on i.MX8MP Laurent Pinchart
@ 2024-02-18 20:43 ` Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 09/12] media: rkisp1: Add YC swap capability Laurent Pinchart
` (4 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Laurent Pinchart @ 2024-02-18 20:43 UTC (permalink / raw)
To: linux-media
Cc: Paul Elder, Adam Ford, Alexander Stein, Dafna Hirschfeld,
Heiko Stuebner, Helen Koike, Kieran Bingham, Tomi Valkeinen,
linux-rockchip
From: Paul Elder <paul.elder@ideasonboard.com>
On the ISP that is integrated in the i.MX8MP, DMA addresses have been
extended to 34 bits, with the 32 MSBs stored in the DMA address
registers and the 2 LSBs set to 0.
To support this:
- Shift the addresses to the right by 2 when writing to registers
- Set the dma mask to 34 bits
- Use dma_addr_t instead of u32 when storing the addresses
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
Changes since v12:
- Make dma_mask a u64
Changes since v5:
- Improve the commit message
Changes since v4:
- Squash in fix from Tomi:
- https://gitlab.com/ideasonboard/nxp/linux/-/commit/d6477fe673b1c0d05d12ae21d8db9a03b07e7fea
Changes since v2:
- Document the RKISP1_FEATURE_DMA_34BIT bit
- Use the rkisp1_has_feature() macro
---
.../platform/rockchip/rkisp1/rkisp1-capture.c | 20 ++++++++++---------
.../platform/rockchip/rkisp1/rkisp1-common.h | 4 +++-
.../platform/rockchip/rkisp1/rkisp1-dev.c | 8 ++++++++
3 files changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
index 7d56874c3106..50e86d8ff902 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
@@ -648,11 +648,13 @@ static void rkisp1_dummy_buf_destroy(struct rkisp1_capture *cap)
static void rkisp1_set_next_buf(struct rkisp1_capture *cap)
{
+ u8 shift = rkisp1_has_feature(cap->rkisp1, DMA_34BIT) ? 2 : 0;
+
cap->buf.curr = cap->buf.next;
cap->buf.next = NULL;
if (!list_empty(&cap->buf.queue)) {
- u32 *buff_addr;
+ dma_addr_t *buff_addr;
cap->buf.next = list_first_entry(&cap->buf.queue, struct rkisp1_buffer, queue);
list_del(&cap->buf.next->queue);
@@ -660,7 +662,7 @@ static void rkisp1_set_next_buf(struct rkisp1_capture *cap)
buff_addr = cap->buf.next->buff_addr;
rkisp1_write(cap->rkisp1, cap->config->mi.y_base_ad_init,
- buff_addr[RKISP1_PLANE_Y]);
+ buff_addr[RKISP1_PLANE_Y] >> shift);
/*
* In order to support grey format we capture
* YUV422 planar format from the camera and
@@ -669,17 +671,17 @@ static void rkisp1_set_next_buf(struct rkisp1_capture *cap)
if (cap->pix.cfg->fourcc == V4L2_PIX_FMT_GREY) {
rkisp1_write(cap->rkisp1,
cap->config->mi.cb_base_ad_init,
- cap->buf.dummy.dma_addr);
+ cap->buf.dummy.dma_addr >> shift);
rkisp1_write(cap->rkisp1,
cap->config->mi.cr_base_ad_init,
- cap->buf.dummy.dma_addr);
+ cap->buf.dummy.dma_addr >> shift);
} else {
rkisp1_write(cap->rkisp1,
cap->config->mi.cb_base_ad_init,
- buff_addr[RKISP1_PLANE_CB]);
+ buff_addr[RKISP1_PLANE_CB] >> shift);
rkisp1_write(cap->rkisp1,
cap->config->mi.cr_base_ad_init,
- buff_addr[RKISP1_PLANE_CR]);
+ buff_addr[RKISP1_PLANE_CR] >> shift);
}
} else {
/*
@@ -687,11 +689,11 @@ static void rkisp1_set_next_buf(struct rkisp1_capture *cap)
* throw data if there is no available buffer.
*/
rkisp1_write(cap->rkisp1, cap->config->mi.y_base_ad_init,
- cap->buf.dummy.dma_addr);
+ cap->buf.dummy.dma_addr >> shift);
rkisp1_write(cap->rkisp1, cap->config->mi.cb_base_ad_init,
- cap->buf.dummy.dma_addr);
+ cap->buf.dummy.dma_addr >> shift);
rkisp1_write(cap->rkisp1, cap->config->mi.cr_base_ad_init,
- cap->buf.dummy.dma_addr);
+ cap->buf.dummy.dma_addr >> shift);
}
/* Set plane offsets */
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
index 070317196aa1..0afee50b97b9 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
@@ -114,6 +114,7 @@ enum rkisp1_isp_pad {
* @RKISP1_FEATURE_MAIN_STRIDE: The ISP supports configurable stride on the main path
* @RKISP1_FEATURE_SELF_PATH: The ISP has a self path
* @RKISP1_FEATURE_DUAL_CROP: The ISP has the dual crop block at the resizer input
+ * @RKISP1_FEATURE_DMA_34BIT: The ISP uses 34-bit DMA addresses
*
* The ISP features are stored in a bitmask in &rkisp1_info.features and allow
* the driver to implement support for features present in some ISP versions
@@ -124,6 +125,7 @@ enum rkisp1_feature {
RKISP1_FEATURE_MAIN_STRIDE = BIT(1),
RKISP1_FEATURE_SELF_PATH = BIT(2),
RKISP1_FEATURE_DUAL_CROP = BIT(3),
+ RKISP1_FEATURE_DMA_34BIT = BIT(4),
};
#define rkisp1_has_feature(rkisp1, feature) \
@@ -239,7 +241,7 @@ struct rkisp1_vdev_node {
struct rkisp1_buffer {
struct vb2_v4l2_buffer vb;
struct list_head queue;
- u32 buff_addr[VIDEO_MAX_PLANES];
+ dma_addr_t buff_addr[VIDEO_MAX_PLANES];
};
/*
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
index 885339159763..ff4ba0682068 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
@@ -531,6 +531,7 @@ static int rkisp1_probe(struct platform_device *pdev)
struct rkisp1_device *rkisp1;
struct v4l2_device *v4l2_dev;
unsigned int i;
+ u64 dma_mask;
int ret, irq;
u32 cif_id;
@@ -544,6 +545,13 @@ static int rkisp1_probe(struct platform_device *pdev)
dev_set_drvdata(dev, rkisp1);
rkisp1->dev = dev;
+ dma_mask = rkisp1_has_feature(rkisp1, DMA_34BIT) ? DMA_BIT_MASK(34) :
+ DMA_BIT_MASK(32);
+
+ ret = dma_set_mask_and_coherent(dev, dma_mask);
+ if (ret)
+ return ret;
+
mutex_init(&rkisp1->stream_lock);
rkisp1->base_addr = devm_platform_ioremap_resource(pdev, 0);
--
Regards,
Laurent Pinchart
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v13 09/12] media: rkisp1: Add YC swap capability
2024-02-18 20:43 [PATCH v13 00/12] media: rkisp1: Add support for i.MX8MP Laurent Pinchart
` (7 preceding siblings ...)
2024-02-18 20:43 ` [PATCH v13 08/12] media: rkisp1: Support i.MX8MP's 34-bit DMA Laurent Pinchart
@ 2024-02-18 20:43 ` Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 10/12] media: rkisp1: Add UYVY as an output format Laurent Pinchart
` (3 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Laurent Pinchart @ 2024-02-18 20:43 UTC (permalink / raw)
To: linux-media
Cc: Paul Elder, Adam Ford, Alexander Stein, Dafna Hirschfeld,
Heiko Stuebner, Helen Koike, Kieran Bingham, Tomi Valkeinen,
linux-rockchip
From: Paul Elder <paul.elder@ideasonboard.com>
The ISP version in the i.MX8MP has an MI_OUTPUT_ALIGN_FORMAT register
that the rk3399 does not have. This register allows swapping bytes,
which can be used to implement UYVY from YUYV.
Add a flag to the format info in the list of formats supported by the
capture v4l2 devices, and update enum_fmt and s_fmt to take it into
account.
To signify the presence of this feature, reuse the MAIN_STRIDE feature
flag, as it is very likely that any ISP version that supports one of
these two features will also support the other.
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Tested-by: Adam Ford <aford173@gmail.com>
---
Changes since v6:
- Replace MI_OUTPUT_ALIGN feature flag with MAIN_STRIDE
---
.../platform/rockchip/rkisp1/rkisp1-capture.c | 26 ++++++++++++++-----
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
index 50e86d8ff902..33756b44a317 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
@@ -47,13 +47,15 @@ enum rkisp1_plane {
* @fourcc: pixel format
* @fmt_type: helper filed for pixel format
* @uv_swap: if cb cr swapped, for yuv
+ * @yc_swap: if y and cb/cr swapped, for yuv
* @write_format: defines how YCbCr self picture data is written to memory
* @output_format: defines sp output format
* @mbus: the mbus code on the src resizer pad that matches the pixel format
*/
struct rkisp1_capture_fmt_cfg {
u32 fourcc;
- u8 uv_swap;
+ u32 uv_swap : 1;
+ u32 yc_swap : 1;
u32 write_format;
u32 output_format;
u32 mbus;
@@ -1159,10 +1161,14 @@ rkisp1_fill_pixfmt(const struct rkisp1_capture *cap,
static const struct rkisp1_capture_fmt_cfg *
rkisp1_find_fmt_cfg(const struct rkisp1_capture *cap, const u32 pixelfmt)
{
+ bool yc_swap_support = rkisp1_has_feature(cap->rkisp1, MAIN_STRIDE);
unsigned int i;
for (i = 0; i < cap->config->fmt_size; i++) {
- if (cap->config->fmts[i].fourcc == pixelfmt)
+ const struct rkisp1_capture_fmt_cfg *fmt = &cap->config->fmts[i];
+
+ if (fmt->fourcc == pixelfmt &&
+ (!fmt->yc_swap || yc_swap_support))
return &cap->config->fmts[i];
}
return NULL;
@@ -1231,23 +1237,29 @@ static int rkisp1_enum_fmt_vid_cap_mplane(struct file *file, void *priv,
{
struct rkisp1_capture *cap = video_drvdata(file);
const struct rkisp1_capture_fmt_cfg *fmt = NULL;
+ bool yc_swap_support = rkisp1_has_feature(cap->rkisp1, MAIN_STRIDE);
unsigned int i, n = 0;
- if (!f->mbus_code) {
- if (f->index >= cap->config->fmt_size)
- return -EINVAL;
+ if (f->index >= cap->config->fmt_size)
+ return -EINVAL;
+ if (!f->mbus_code && yc_swap_support) {
fmt = &cap->config->fmts[f->index];
f->pixelformat = fmt->fourcc;
return 0;
}
for (i = 0; i < cap->config->fmt_size; i++) {
- if (cap->config->fmts[i].mbus != f->mbus_code)
+ fmt = &cap->config->fmts[i];
+
+ if (f->mbus_code && fmt->mbus != f->mbus_code)
+ continue;
+
+ if (!yc_swap_support && fmt->yc_swap)
continue;
if (n++ == f->index) {
- f->pixelformat = cap->config->fmts[i].fourcc;
+ f->pixelformat = fmt->fourcc;
return 0;
}
}
--
Regards,
Laurent Pinchart
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v13 10/12] media: rkisp1: Add UYVY as an output format
2024-02-18 20:43 [PATCH v13 00/12] media: rkisp1: Add support for i.MX8MP Laurent Pinchart
` (8 preceding siblings ...)
2024-02-18 20:43 ` [PATCH v13 09/12] media: rkisp1: Add YC swap capability Laurent Pinchart
@ 2024-02-18 20:43 ` Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 11/12] media: rkisp1: Fix endianness on raw streams on i.MX8MP Laurent Pinchart
` (2 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Laurent Pinchart @ 2024-02-18 20:43 UTC (permalink / raw)
To: linux-media
Cc: Paul Elder, Adam Ford, Alexander Stein, Dafna Hirschfeld,
Heiko Stuebner, Helen Koike, Kieran Bingham, Tomi Valkeinen,
linux-rockchip
From: Paul Elder <paul.elder@ideasonboard.com>
Add support for UYVY as an output format. The uv_swap bit in the
MI_XTD_FORMAT_CTRL register that is used for the NV formats does not
work for packed YUV formats. Thus, UYVY support is implemented via
byte-swapping. This method clearly does not work for implementing
support for YVYU and VYUY.
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Tested-by: Adam Ford <aford173@gmail.com>
---
Changes since v6:
- Replace MI_OUTPUT_FORMAT feature flag with MAIN_STRIDE
---
.../platform/rockchip/rkisp1/rkisp1-capture.c | 41 +++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
index 33756b44a317..0efdf8513de0 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
@@ -97,6 +97,12 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = {
.uv_swap = 0,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_UYVY,
+ .uv_swap = 0,
+ .yc_swap = 1,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
}, {
.fourcc = V4L2_PIX_FMT_YUV422P,
.uv_swap = 0,
@@ -231,6 +237,13 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_sp_fmts[] = {
.write_format = RKISP1_MI_CTRL_SP_WRITE_INT,
.output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_UYVY,
+ .uv_swap = 0,
+ .yc_swap = 1,
+ .write_format = RKISP1_MI_CTRL_SP_WRITE_INT,
+ .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
}, {
.fourcc = V4L2_PIX_FMT_YUV422P,
.uv_swap = 0,
@@ -464,6 +477,20 @@ static void rkisp1_mp_config(struct rkisp1_capture *cap)
rkisp1_write(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL, reg);
}
+ /*
+ * U/V swapping with the MI_XTD_FORMAT_CTRL register only works for
+ * NV12/NV21 and NV16/NV61, so instead use byte swap to support UYVY.
+ * YVYU and VYUY cannot be supported with this method.
+ */
+ if (rkisp1_has_feature(rkisp1, MAIN_STRIDE)) {
+ reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT);
+ if (cap->pix.cfg->yc_swap)
+ reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES;
+ else
+ reg &= ~RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES;
+ rkisp1_write(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT, reg);
+ }
+
rkisp1_mi_config_ctrl(cap);
reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL);
@@ -507,6 +534,20 @@ static void rkisp1_sp_config(struct rkisp1_capture *cap)
rkisp1_write(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL, reg);
}
+ /*
+ * U/V swapping with the MI_XTD_FORMAT_CTRL register only works for
+ * NV12/NV21 and NV16/NV61, so instead use byte swap to support UYVY.
+ * YVYU and VYUY cannot be supported with this method.
+ */
+ if (rkisp1_has_feature(rkisp1, MAIN_STRIDE)) {
+ reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT);
+ if (cap->pix.cfg->yc_swap)
+ reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_SP_BYTE_SWAP_BYTES;
+ else
+ reg &= ~RKISP1_CIF_OUTPUT_ALIGN_FORMAT_SP_BYTE_SWAP_BYTES;
+ rkisp1_write(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT, reg);
+ }
+
rkisp1_mi_config_ctrl(cap);
mi_ctrl = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL);
--
Regards,
Laurent Pinchart
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v13 11/12] media: rkisp1: Fix endianness on raw streams on i.MX8MP
2024-02-18 20:43 [PATCH v13 00/12] media: rkisp1: Add support for i.MX8MP Laurent Pinchart
` (9 preceding siblings ...)
2024-02-18 20:43 ` [PATCH v13 10/12] media: rkisp1: Add UYVY as an output format Laurent Pinchart
@ 2024-02-18 20:43 ` Laurent Pinchart
2024-02-19 9:56 ` Paul Elder
2024-02-19 12:54 ` [PATCH v13.1 " Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 12/12] media: rkisp1: Add match data for i.MX8MP ISP Laurent Pinchart
2024-02-19 8:42 ` [PATCH v13 00/12] media: rkisp1: Add support for i.MX8MP Alexander Stein
12 siblings, 2 replies; 17+ messages in thread
From: Laurent Pinchart @ 2024-02-18 20:43 UTC (permalink / raw)
To: linux-media
Cc: Paul Elder, Adam Ford, Alexander Stein, Dafna Hirschfeld,
Heiko Stuebner, Helen Koike, Kieran Bingham, Tomi Valkeinen,
linux-rockchip
From: Paul Elder <paul.elder@ideasonboard.com>
The i.MX8MP has extra register fields in the memory interface control
register for setting the output format, which work with the output
alignment format register for byte-swapping and LSB/MSB alignment.
With processed and 8-bit raw streams, it doesn't cause any problems to
not set these, but with raw streams of higher bit depth the endianness
is swapped and the data is not aligned properly.
Add support for setting these registers and plumb them in to fix this.
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
Changes since v12:
- Merge the output_format_mp and output_format_sp fields
- Set the MP output format in rkisp1_mp_config()
- Fix typo in commit message
Changes since v6:
- replace MP_OUTPUT_FORMAT feature flag with MAIN_STRIDE
New in v6
---
.../platform/rockchip/rkisp1/rkisp1-capture.c | 52 +++++++++++++++++--
.../platform/rockchip/rkisp1/rkisp1-regs.h | 8 +++
2 files changed, 56 insertions(+), 4 deletions(-)
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
index 0efdf8513de0..accc16ad1432 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
@@ -48,14 +48,17 @@ enum rkisp1_plane {
* @fmt_type: helper filed for pixel format
* @uv_swap: if cb cr swapped, for yuv
* @yc_swap: if y and cb/cr swapped, for yuv
+ * @byte_swap: if byte pairs are swapped, for raw
* @write_format: defines how YCbCr self picture data is written to memory
- * @output_format: defines sp output format
+ * @output_format: defines the output format (RKISP1_CIF_MI_INIT_MP_OUTPUT_* for
+ * the main path and RKISP1_MI_CTRL_SP_OUTPUT_* for the self path)
* @mbus: the mbus code on the src resizer pad that matches the pixel format
*/
struct rkisp1_capture_fmt_cfg {
u32 fourcc;
u32 uv_swap : 1;
u32 yc_swap : 1;
+ u32 byte_swap : 1;
u32 write_format;
u32 output_format;
u32 mbus;
@@ -96,42 +99,50 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = {
.fourcc = V4L2_PIX_FMT_YUYV,
.uv_swap = 0,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
}, {
.fourcc = V4L2_PIX_FMT_UYVY,
.uv_swap = 0,
.yc_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
}, {
.fourcc = V4L2_PIX_FMT_YUV422P,
.uv_swap = 0,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
}, {
.fourcc = V4L2_PIX_FMT_NV16,
.uv_swap = 0,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
}, {
.fourcc = V4L2_PIX_FMT_NV61,
.uv_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
}, {
.fourcc = V4L2_PIX_FMT_NV16M,
.uv_swap = 0,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
}, {
.fourcc = V4L2_PIX_FMT_NV61M,
.uv_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
}, {
.fourcc = V4L2_PIX_FMT_YVU422M,
.uv_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
},
/* yuv400 */
@@ -139,6 +150,7 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = {
.fourcc = V4L2_PIX_FMT_GREY,
.uv_swap = 0,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV400,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
},
/* yuv420 */
@@ -146,81 +158,107 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = {
.fourcc = V4L2_PIX_FMT_NV21,
.uv_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
.mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
}, {
.fourcc = V4L2_PIX_FMT_NV12,
.uv_swap = 0,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
.mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
}, {
.fourcc = V4L2_PIX_FMT_NV21M,
.uv_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
.mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
}, {
.fourcc = V4L2_PIX_FMT_NV12M,
.uv_swap = 0,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
.mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
}, {
.fourcc = V4L2_PIX_FMT_YUV420,
.uv_swap = 0,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
.mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
}, {
.fourcc = V4L2_PIX_FMT_YVU420,
.uv_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
.mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
},
/* raw */
{
.fourcc = V4L2_PIX_FMT_SRGGB8,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
.mbus = MEDIA_BUS_FMT_SRGGB8_1X8,
}, {
.fourcc = V4L2_PIX_FMT_SGRBG8,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
.mbus = MEDIA_BUS_FMT_SGRBG8_1X8,
}, {
.fourcc = V4L2_PIX_FMT_SGBRG8,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
.mbus = MEDIA_BUS_FMT_SGBRG8_1X8,
}, {
.fourcc = V4L2_PIX_FMT_SBGGR8,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
.mbus = MEDIA_BUS_FMT_SBGGR8_1X8,
}, {
.fourcc = V4L2_PIX_FMT_SRGGB10,
+ .byte_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
.mbus = MEDIA_BUS_FMT_SRGGB10_1X10,
}, {
.fourcc = V4L2_PIX_FMT_SGRBG10,
+ .byte_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
.mbus = MEDIA_BUS_FMT_SGRBG10_1X10,
}, {
.fourcc = V4L2_PIX_FMT_SGBRG10,
+ .byte_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
.mbus = MEDIA_BUS_FMT_SGBRG10_1X10,
}, {
.fourcc = V4L2_PIX_FMT_SBGGR10,
+ .byte_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
.mbus = MEDIA_BUS_FMT_SBGGR10_1X10,
}, {
.fourcc = V4L2_PIX_FMT_SRGGB12,
+ .byte_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
.mbus = MEDIA_BUS_FMT_SRGGB12_1X12,
}, {
.fourcc = V4L2_PIX_FMT_SGRBG12,
+ .byte_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
.mbus = MEDIA_BUS_FMT_SGRBG12_1X12,
}, {
.fourcc = V4L2_PIX_FMT_SGBRG12,
+ .byte_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
.mbus = MEDIA_BUS_FMT_SGBRG12_1X12,
}, {
.fourcc = V4L2_PIX_FMT_SBGGR12,
+ .byte_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
.mbus = MEDIA_BUS_FMT_SBGGR12_1X12,
},
};
@@ -484,10 +522,12 @@ static void rkisp1_mp_config(struct rkisp1_capture *cap)
*/
if (rkisp1_has_feature(rkisp1, MAIN_STRIDE)) {
reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT);
- if (cap->pix.cfg->yc_swap)
+ if (cap->pix.cfg->yc_swap || cap->pix.cfg->byte_swap)
reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES;
else
reg &= ~RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES;
+
+ reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_LSB_ALIGNMENT;
rkisp1_write(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT, reg);
}
@@ -557,6 +597,8 @@ static void rkisp1_sp_config(struct rkisp1_capture *cap)
cap->pix.cfg->output_format |
RKISP1_CIF_MI_SP_AUTOUPDATE_ENABLE;
rkisp1_write(rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl);
+
+ rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT, cap->pix.cfg->output_format);
}
static void rkisp1_mp_disable(struct rkisp1_capture *cap)
@@ -943,6 +985,7 @@ static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap)
struct rkisp1_device *rkisp1 = cap->rkisp1;
struct rkisp1_capture *other = &rkisp1->capture_devs[cap->id ^ 1];
bool has_self_path = rkisp1_has_feature(rkisp1, SELF_PATH);
+ u32 reg;
cap->ops->set_data_path(cap);
cap->ops->config(cap);
@@ -962,8 +1005,9 @@ static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap)
*/
if (!has_self_path || !other->is_streaming) {
/* force cfg update */
- rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT,
- RKISP1_CIF_MI_INIT_SOFT_UPD);
+ reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_INIT);
+ reg |= RKISP1_CIF_MI_INIT_SOFT_UPD;
+ rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT, reg);
rkisp1_set_next_buf(cap);
}
spin_unlock_irq(&cap->buf.lock);
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
index 3b19c8411360..762243016f05 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
@@ -144,6 +144,14 @@
/* MI_INIT */
#define RKISP1_CIF_MI_INIT_SKIP BIT(2)
#define RKISP1_CIF_MI_INIT_SOFT_UPD BIT(4)
+#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV400 (0 << 5)
+#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420 (1 << 5)
+#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422 (2 << 5)
+#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV444 (3 << 5)
+#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12 (4 << 5)
+#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8 (5 << 5)
+#define RKISP1_CIF_MI_INIT_MP_OUTPUT_JPEG (6 << 5)
+#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10 (7 << 5)
/* MI_CTRL_SHD */
#define RKISP1_CIF_MI_CTRL_SHD_MP_IN_ENABLED BIT(0)
--
Regards,
Laurent Pinchart
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v13 12/12] media: rkisp1: Add match data for i.MX8MP ISP
2024-02-18 20:43 [PATCH v13 00/12] media: rkisp1: Add support for i.MX8MP Laurent Pinchart
` (10 preceding siblings ...)
2024-02-18 20:43 ` [PATCH v13 11/12] media: rkisp1: Fix endianness on raw streams on i.MX8MP Laurent Pinchart
@ 2024-02-18 20:43 ` Laurent Pinchart
2024-02-19 8:42 ` [PATCH v13 00/12] media: rkisp1: Add support for i.MX8MP Alexander Stein
12 siblings, 0 replies; 17+ messages in thread
From: Laurent Pinchart @ 2024-02-18 20:43 UTC (permalink / raw)
To: linux-media
Cc: Paul Elder, Adam Ford, Alexander Stein, Dafna Hirschfeld,
Heiko Stuebner, Helen Koike, Kieran Bingham, Tomi Valkeinen,
linux-rockchip
From: Paul Elder <paul.elder@ideasonboard.com>
Add match data to the rkisp1 driver to match the i.MX8MP ISP.
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
Changes since v6:
- Move out adding the version enum
---
.../platform/rockchip/rkisp1/rkisp1-dev.c | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
index ff4ba0682068..e6cd4b8604bc 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
@@ -511,6 +511,26 @@ static const struct rkisp1_info rk3399_isp_info = {
| RKISP1_FEATURE_DUAL_CROP,
};
+static const char * const imx8mp_isp_clks[] = {
+ "isp",
+ "hclk",
+ "aclk",
+};
+
+static const struct rkisp1_isr_data imx8mp_isp_isrs[] = {
+ { NULL, rkisp1_isr, BIT(RKISP1_IRQ_ISP) | BIT(RKISP1_IRQ_MI) },
+};
+
+static const struct rkisp1_info imx8mp_isp_info = {
+ .clks = imx8mp_isp_clks,
+ .clk_size = ARRAY_SIZE(imx8mp_isp_clks),
+ .isrs = imx8mp_isp_isrs,
+ .isr_size = ARRAY_SIZE(imx8mp_isp_isrs),
+ .isp_ver = RKISP1_V_IMX8MP,
+ .features = RKISP1_FEATURE_MAIN_STRIDE
+ | RKISP1_FEATURE_DMA_34BIT,
+};
+
static const struct of_device_id rkisp1_of_match[] = {
{
.compatible = "rockchip,px30-cif-isp",
@@ -520,6 +540,10 @@ static const struct of_device_id rkisp1_of_match[] = {
.compatible = "rockchip,rk3399-cif-isp",
.data = &rk3399_isp_info,
},
+ {
+ .compatible = "fsl,imx8mp-isp",
+ .data = &imx8mp_isp_info,
+ },
{},
};
MODULE_DEVICE_TABLE(of, rkisp1_of_match);
--
Regards,
Laurent Pinchart
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v13 00/12] media: rkisp1: Add support for i.MX8MP
2024-02-18 20:43 [PATCH v13 00/12] media: rkisp1: Add support for i.MX8MP Laurent Pinchart
` (11 preceding siblings ...)
2024-02-18 20:43 ` [PATCH v13 12/12] media: rkisp1: Add match data for i.MX8MP ISP Laurent Pinchart
@ 2024-02-19 8:42 ` Alexander Stein
12 siblings, 0 replies; 17+ messages in thread
From: Alexander Stein @ 2024-02-19 8:42 UTC (permalink / raw)
To: linux-media, Laurent Pinchart
Cc: Adam Ford, Conor Dooley, Dafna Hirschfeld, Heiko Stuebner,
Helen Koike, Kieran Bingham, Krzysztof Kozlowski, Paul Elder,
Rob Herring, Tomi Valkeinen, devicetree, linux-rockchip
Hi Laurent,
thanks for the update.
Am Sonntag, 18. Februar 2024, 21:43:38 CET schrieb Laurent Pinchart:
> Hello,
>
> This series extends the rkisp1 driver to support the ISP found in the
> NXP i.MX8MP SoC.
>
> The ISP IP cores in the Rockchip RK3399 (known as the "Rockchip ISP1")
> and in the NXP i.MX8MP have the same origin, and have slightly diverged
> over time as they are now independently developed (afaik) by Rockchip
> and VeriSilicon. The latter is marketed under the name "ISP8000Nano",
> and is close enough to the RK3399 ISP that it can easily be supported by
> the same driver.
>
> This version of the series specifically has been tested on a Polyhex
> Debix model A with an IMX219 camera sensor (Raspberry Pi cam v2).
>
> See individual patches for a detailed description of changes compared to
> v12.
>
> This should hopefully be the last version, I plan to send a pull request
> in a few days, in time for v6.9.
Still works on my platform TQMa8MPQL/MBa8MPxL + IMX327 using libcamera for 1080p + SRGGB10 debayering. For the missing commits:
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> Laurent Pinchart (2):
> media: rkisp1: Add and use rkisp1_has_feature() macro
> media: rkisp1: Configure gasket on i.MX8MP
>
> Paul Elder (10):
> media: rkisp1: Support setting memory stride for main path
> media: rkisp1: Support devices lacking self path
> media: rkisp1: Support devices lacking dual crop
> dt-bindings: media: rkisp1: Add i.MX8MP ISP to compatible
> media: rkisp1: Add version enum for i.MX8MP ISP
> media: rkisp1: Support i.MX8MP's 34-bit DMA
> media: rkisp1: Add YC swap capability
> media: rkisp1: Add UYVY as an output format
> media: rkisp1: Fix endianness on raw streams on i.MX8MP
> media: rkisp1: Add match data for i.MX8MP ISP
>
> .../bindings/media/rockchip-isp1.yaml | 37 +++-
> .../platform/rockchip/rkisp1/rkisp1-capture.c | 180 ++++++++++++++----
> .../platform/rockchip/rkisp1/rkisp1-common.h | 35 +++-
> .../platform/rockchip/rkisp1/rkisp1-dev.c | 71 ++++++-
> .../platform/rockchip/rkisp1/rkisp1-isp.c | 131 ++++++++++++-
> .../platform/rockchip/rkisp1/rkisp1-regs.h | 35 ++++
> .../platform/rockchip/rkisp1/rkisp1-resizer.c | 19 +-
> include/uapi/linux/rkisp1-config.h | 50 ++---
> 8 files changed, 472 insertions(+), 86 deletions(-)
>
>
> base-commit: e0b8eb0f6d652981bfd9ba7c619c9d81ed087ad0
>
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v13 11/12] media: rkisp1: Fix endianness on raw streams on i.MX8MP
2024-02-18 20:43 ` [PATCH v13 11/12] media: rkisp1: Fix endianness on raw streams on i.MX8MP Laurent Pinchart
@ 2024-02-19 9:56 ` Paul Elder
2024-02-19 10:29 ` Laurent Pinchart
2024-02-19 12:54 ` [PATCH v13.1 " Laurent Pinchart
1 sibling, 1 reply; 17+ messages in thread
From: Paul Elder @ 2024-02-19 9:56 UTC (permalink / raw)
To: Laurent Pinchart
Cc: linux-media, Adam Ford, Alexander Stein, Dafna Hirschfeld,
Heiko Stuebner, Helen Koike, Kieran Bingham, Tomi Valkeinen,
linux-rockchip
Hi Laurent,
On Sun, Feb 18, 2024 at 10:43:49PM +0200, Laurent Pinchart wrote:
> From: Paul Elder <paul.elder@ideasonboard.com>
>
> The i.MX8MP has extra register fields in the memory interface control
> register for setting the output format, which work with the output
> alignment format register for byte-swapping and LSB/MSB alignment.
>
> With processed and 8-bit raw streams, it doesn't cause any problems to
> not set these, but with raw streams of higher bit depth the endianness
> is swapped and the data is not aligned properly.
>
> Add support for setting these registers and plumb them in to fix this.
>
> Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> Changes since v12:
>
> - Merge the output_format_mp and output_format_sp fields
> - Set the MP output format in rkisp1_mp_config()
> - Fix typo in commit message
>
> Changes since v6:
>
> - replace MP_OUTPUT_FORMAT feature flag with MAIN_STRIDE
>
> New in v6
> ---
> .../platform/rockchip/rkisp1/rkisp1-capture.c | 52 +++++++++++++++++--
> .../platform/rockchip/rkisp1/rkisp1-regs.h | 8 +++
> 2 files changed, 56 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> index 0efdf8513de0..accc16ad1432 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> @@ -48,14 +48,17 @@ enum rkisp1_plane {
> * @fmt_type: helper filed for pixel format
> * @uv_swap: if cb cr swapped, for yuv
> * @yc_swap: if y and cb/cr swapped, for yuv
> + * @byte_swap: if byte pairs are swapped, for raw
> * @write_format: defines how YCbCr self picture data is written to memory
> - * @output_format: defines sp output format
> + * @output_format: defines the output format (RKISP1_CIF_MI_INIT_MP_OUTPUT_* for
> + * the main path and RKISP1_MI_CTRL_SP_OUTPUT_* for the self path)
> * @mbus: the mbus code on the src resizer pad that matches the pixel format
> */
> struct rkisp1_capture_fmt_cfg {
> u32 fourcc;
> u32 uv_swap : 1;
> u32 yc_swap : 1;
> + u32 byte_swap : 1;
> u32 write_format;
> u32 output_format;
> u32 mbus;
> @@ -96,42 +99,50 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = {
> .fourcc = V4L2_PIX_FMT_YUYV,
> .uv_swap = 0,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> }, {
> .fourcc = V4L2_PIX_FMT_UYVY,
> .uv_swap = 0,
> .yc_swap = 1,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> }, {
> .fourcc = V4L2_PIX_FMT_YUV422P,
> .uv_swap = 0,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> }, {
> .fourcc = V4L2_PIX_FMT_NV16,
> .uv_swap = 0,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> }, {
> .fourcc = V4L2_PIX_FMT_NV61,
> .uv_swap = 1,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> }, {
> .fourcc = V4L2_PIX_FMT_NV16M,
> .uv_swap = 0,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> }, {
> .fourcc = V4L2_PIX_FMT_NV61M,
> .uv_swap = 1,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> }, {
> .fourcc = V4L2_PIX_FMT_YVU422M,
> .uv_swap = 1,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> },
> /* yuv400 */
> @@ -139,6 +150,7 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = {
> .fourcc = V4L2_PIX_FMT_GREY,
> .uv_swap = 0,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV400,
> .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> },
> /* yuv420 */
> @@ -146,81 +158,107 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = {
> .fourcc = V4L2_PIX_FMT_NV21,
> .uv_swap = 1,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
> .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> }, {
> .fourcc = V4L2_PIX_FMT_NV12,
> .uv_swap = 0,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
> .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> }, {
> .fourcc = V4L2_PIX_FMT_NV21M,
> .uv_swap = 1,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
> .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> }, {
> .fourcc = V4L2_PIX_FMT_NV12M,
> .uv_swap = 0,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
> .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> }, {
> .fourcc = V4L2_PIX_FMT_YUV420,
> .uv_swap = 0,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
> .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> }, {
> .fourcc = V4L2_PIX_FMT_YVU420,
> .uv_swap = 1,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
> .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> },
> /* raw */
> {
> .fourcc = V4L2_PIX_FMT_SRGGB8,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
> .mbus = MEDIA_BUS_FMT_SRGGB8_1X8,
> }, {
> .fourcc = V4L2_PIX_FMT_SGRBG8,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
> .mbus = MEDIA_BUS_FMT_SGRBG8_1X8,
> }, {
> .fourcc = V4L2_PIX_FMT_SGBRG8,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
> .mbus = MEDIA_BUS_FMT_SGBRG8_1X8,
> }, {
> .fourcc = V4L2_PIX_FMT_SBGGR8,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
> .mbus = MEDIA_BUS_FMT_SBGGR8_1X8,
> }, {
> .fourcc = V4L2_PIX_FMT_SRGGB10,
> + .byte_swap = 1,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
> .mbus = MEDIA_BUS_FMT_SRGGB10_1X10,
> }, {
> .fourcc = V4L2_PIX_FMT_SGRBG10,
> + .byte_swap = 1,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
> .mbus = MEDIA_BUS_FMT_SGRBG10_1X10,
> }, {
> .fourcc = V4L2_PIX_FMT_SGBRG10,
> + .byte_swap = 1,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
> .mbus = MEDIA_BUS_FMT_SGBRG10_1X10,
> }, {
> .fourcc = V4L2_PIX_FMT_SBGGR10,
> + .byte_swap = 1,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
> .mbus = MEDIA_BUS_FMT_SBGGR10_1X10,
> }, {
> .fourcc = V4L2_PIX_FMT_SRGGB12,
> + .byte_swap = 1,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
> .mbus = MEDIA_BUS_FMT_SRGGB12_1X12,
> }, {
> .fourcc = V4L2_PIX_FMT_SGRBG12,
> + .byte_swap = 1,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
> .mbus = MEDIA_BUS_FMT_SGRBG12_1X12,
> }, {
> .fourcc = V4L2_PIX_FMT_SGBRG12,
> + .byte_swap = 1,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
> .mbus = MEDIA_BUS_FMT_SGBRG12_1X12,
> }, {
> .fourcc = V4L2_PIX_FMT_SBGGR12,
> + .byte_swap = 1,
> .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
> .mbus = MEDIA_BUS_FMT_SBGGR12_1X12,
> },
> };
> @@ -484,10 +522,12 @@ static void rkisp1_mp_config(struct rkisp1_capture *cap)
> */
> if (rkisp1_has_feature(rkisp1, MAIN_STRIDE)) {
> reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT);
> - if (cap->pix.cfg->yc_swap)
> + if (cap->pix.cfg->yc_swap || cap->pix.cfg->byte_swap)
> reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES;
> else
> reg &= ~RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES;
> +
> + reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_LSB_ALIGNMENT;
> rkisp1_write(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT, reg);
> }
>
> @@ -557,6 +597,8 @@ static void rkisp1_sp_config(struct rkisp1_capture *cap)
> cap->pix.cfg->output_format |
> RKISP1_CIF_MI_SP_AUTOUPDATE_ENABLE;
> rkisp1_write(rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl);
> +
> + rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT, cap->pix.cfg->output_format);
I think you're missing the analogous register setting for the main path.
Paul
> }
>
> static void rkisp1_mp_disable(struct rkisp1_capture *cap)
> @@ -943,6 +985,7 @@ static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap)
> struct rkisp1_device *rkisp1 = cap->rkisp1;
> struct rkisp1_capture *other = &rkisp1->capture_devs[cap->id ^ 1];
> bool has_self_path = rkisp1_has_feature(rkisp1, SELF_PATH);
> + u32 reg;
>
> cap->ops->set_data_path(cap);
> cap->ops->config(cap);
> @@ -962,8 +1005,9 @@ static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap)
> */
> if (!has_self_path || !other->is_streaming) {
> /* force cfg update */
> - rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT,
> - RKISP1_CIF_MI_INIT_SOFT_UPD);
> + reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_INIT);
> + reg |= RKISP1_CIF_MI_INIT_SOFT_UPD;
> + rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT, reg);
> rkisp1_set_next_buf(cap);
> }
> spin_unlock_irq(&cap->buf.lock);
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> index 3b19c8411360..762243016f05 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> @@ -144,6 +144,14 @@
> /* MI_INIT */
> #define RKISP1_CIF_MI_INIT_SKIP BIT(2)
> #define RKISP1_CIF_MI_INIT_SOFT_UPD BIT(4)
> +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV400 (0 << 5)
> +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420 (1 << 5)
> +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422 (2 << 5)
> +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV444 (3 << 5)
> +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12 (4 << 5)
> +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8 (5 << 5)
> +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_JPEG (6 << 5)
> +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10 (7 << 5)
>
> /* MI_CTRL_SHD */
> #define RKISP1_CIF_MI_CTRL_SHD_MP_IN_ENABLED BIT(0)
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v13 11/12] media: rkisp1: Fix endianness on raw streams on i.MX8MP
2024-02-19 9:56 ` Paul Elder
@ 2024-02-19 10:29 ` Laurent Pinchart
0 siblings, 0 replies; 17+ messages in thread
From: Laurent Pinchart @ 2024-02-19 10:29 UTC (permalink / raw)
To: Paul Elder
Cc: linux-media, Adam Ford, Alexander Stein, Dafna Hirschfeld,
Heiko Stuebner, Helen Koike, Kieran Bingham, Tomi Valkeinen,
linux-rockchip
On Mon, Feb 19, 2024 at 06:56:59PM +0900, Paul Elder wrote:
> On Sun, Feb 18, 2024 at 10:43:49PM +0200, Laurent Pinchart wrote:
> > From: Paul Elder <paul.elder@ideasonboard.com>
> >
> > The i.MX8MP has extra register fields in the memory interface control
> > register for setting the output format, which work with the output
> > alignment format register for byte-swapping and LSB/MSB alignment.
> >
> > With processed and 8-bit raw streams, it doesn't cause any problems to
> > not set these, but with raw streams of higher bit depth the endianness
> > is swapped and the data is not aligned properly.
> >
> > Add support for setting these registers and plumb them in to fix this.
> >
> > Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > ---
> > Changes since v12:
> >
> > - Merge the output_format_mp and output_format_sp fields
> > - Set the MP output format in rkisp1_mp_config()
> > - Fix typo in commit message
> >
> > Changes since v6:
> >
> > - replace MP_OUTPUT_FORMAT feature flag with MAIN_STRIDE
> >
> > New in v6
> > ---
> > .../platform/rockchip/rkisp1/rkisp1-capture.c | 52 +++++++++++++++++--
> > .../platform/rockchip/rkisp1/rkisp1-regs.h | 8 +++
> > 2 files changed, 56 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> > index 0efdf8513de0..accc16ad1432 100644
> > --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> > +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> > @@ -48,14 +48,17 @@ enum rkisp1_plane {
> > * @fmt_type: helper filed for pixel format
> > * @uv_swap: if cb cr swapped, for yuv
> > * @yc_swap: if y and cb/cr swapped, for yuv
> > + * @byte_swap: if byte pairs are swapped, for raw
> > * @write_format: defines how YCbCr self picture data is written to memory
> > - * @output_format: defines sp output format
> > + * @output_format: defines the output format (RKISP1_CIF_MI_INIT_MP_OUTPUT_* for
> > + * the main path and RKISP1_MI_CTRL_SP_OUTPUT_* for the self path)
> > * @mbus: the mbus code on the src resizer pad that matches the pixel format
> > */
> > struct rkisp1_capture_fmt_cfg {
> > u32 fourcc;
> > u32 uv_swap : 1;
> > u32 yc_swap : 1;
> > + u32 byte_swap : 1;
> > u32 write_format;
> > u32 output_format;
> > u32 mbus;
> > @@ -96,42 +99,50 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = {
> > .fourcc = V4L2_PIX_FMT_YUYV,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_UYVY,
> > .uv_swap = 0,
> > .yc_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_YUV422P,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV16,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV61,
> > .uv_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV16M,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV61M,
> > .uv_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_YVU422M,
> > .uv_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > },
> > /* yuv400 */
> > @@ -139,6 +150,7 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = {
> > .fourcc = V4L2_PIX_FMT_GREY,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV400,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > },
> > /* yuv420 */
> > @@ -146,81 +158,107 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = {
> > .fourcc = V4L2_PIX_FMT_NV21,
> > .uv_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
> > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV12,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
> > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV21M,
> > .uv_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
> > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV12M,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
> > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_YUV420,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
> > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_YVU420,
> > .uv_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
> > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> > },
> > /* raw */
> > {
> > .fourcc = V4L2_PIX_FMT_SRGGB8,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
> > .mbus = MEDIA_BUS_FMT_SRGGB8_1X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SGRBG8,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
> > .mbus = MEDIA_BUS_FMT_SGRBG8_1X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SGBRG8,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
> > .mbus = MEDIA_BUS_FMT_SGBRG8_1X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SBGGR8,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
> > .mbus = MEDIA_BUS_FMT_SBGGR8_1X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SRGGB10,
> > + .byte_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
> > .mbus = MEDIA_BUS_FMT_SRGGB10_1X10,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SGRBG10,
> > + .byte_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
> > .mbus = MEDIA_BUS_FMT_SGRBG10_1X10,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SGBRG10,
> > + .byte_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
> > .mbus = MEDIA_BUS_FMT_SGBRG10_1X10,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SBGGR10,
> > + .byte_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
> > .mbus = MEDIA_BUS_FMT_SBGGR10_1X10,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SRGGB12,
> > + .byte_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
> > .mbus = MEDIA_BUS_FMT_SRGGB12_1X12,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SGRBG12,
> > + .byte_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
> > .mbus = MEDIA_BUS_FMT_SGRBG12_1X12,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SGBRG12,
> > + .byte_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
> > .mbus = MEDIA_BUS_FMT_SGBRG12_1X12,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SBGGR12,
> > + .byte_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> > + .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
> > .mbus = MEDIA_BUS_FMT_SBGGR12_1X12,
> > },
> > };
> > @@ -484,10 +522,12 @@ static void rkisp1_mp_config(struct rkisp1_capture *cap)
> > */
> > if (rkisp1_has_feature(rkisp1, MAIN_STRIDE)) {
> > reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT);
> > - if (cap->pix.cfg->yc_swap)
> > + if (cap->pix.cfg->yc_swap || cap->pix.cfg->byte_swap)
> > reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES;
> > else
> > reg &= ~RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES;
> > +
> > + reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_LSB_ALIGNMENT;
> > rkisp1_write(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT, reg);
> > }
> >
> > @@ -557,6 +597,8 @@ static void rkisp1_sp_config(struct rkisp1_capture *cap)
> > cap->pix.cfg->output_format |
> > RKISP1_CIF_MI_SP_AUTOUPDATE_ENABLE;
> > rkisp1_write(rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl);
> > +
> > + rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT, cap->pix.cfg->output_format);
>
> I think you're missing the analogous register setting for the main path.
How did this end up in rkisp1_sp_config() instead of
rkisp1_mp_config()... Thanks for catching my mistake. I'll send a new
version of this patch.
> > }
> >
> > static void rkisp1_mp_disable(struct rkisp1_capture *cap)
> > @@ -943,6 +985,7 @@ static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap)
> > struct rkisp1_device *rkisp1 = cap->rkisp1;
> > struct rkisp1_capture *other = &rkisp1->capture_devs[cap->id ^ 1];
> > bool has_self_path = rkisp1_has_feature(rkisp1, SELF_PATH);
> > + u32 reg;
> >
> > cap->ops->set_data_path(cap);
> > cap->ops->config(cap);
> > @@ -962,8 +1005,9 @@ static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap)
> > */
> > if (!has_self_path || !other->is_streaming) {
> > /* force cfg update */
> > - rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT,
> > - RKISP1_CIF_MI_INIT_SOFT_UPD);
> > + reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_INIT);
> > + reg |= RKISP1_CIF_MI_INIT_SOFT_UPD;
> > + rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT, reg);
> > rkisp1_set_next_buf(cap);
> > }
> > spin_unlock_irq(&cap->buf.lock);
> > diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> > index 3b19c8411360..762243016f05 100644
> > --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> > +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> > @@ -144,6 +144,14 @@
> > /* MI_INIT */
> > #define RKISP1_CIF_MI_INIT_SKIP BIT(2)
> > #define RKISP1_CIF_MI_INIT_SOFT_UPD BIT(4)
> > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV400 (0 << 5)
> > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420 (1 << 5)
> > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422 (2 << 5)
> > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV444 (3 << 5)
> > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12 (4 << 5)
> > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8 (5 << 5)
> > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_JPEG (6 << 5)
> > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10 (7 << 5)
> >
> > /* MI_CTRL_SHD */
> > #define RKISP1_CIF_MI_CTRL_SHD_MP_IN_ENABLED BIT(0)
--
Regards,
Laurent Pinchart
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v13.1 11/12] media: rkisp1: Fix endianness on raw streams on i.MX8MP
2024-02-18 20:43 ` [PATCH v13 11/12] media: rkisp1: Fix endianness on raw streams on i.MX8MP Laurent Pinchart
2024-02-19 9:56 ` Paul Elder
@ 2024-02-19 12:54 ` Laurent Pinchart
1 sibling, 0 replies; 17+ messages in thread
From: Laurent Pinchart @ 2024-02-19 12:54 UTC (permalink / raw)
To: linux-media
Cc: Paul Elder, Adam Ford, Alexander Stein, Dafna Hirschfeld,
Heiko Stuebner, Helen Koike, Kieran Bingham, Tomi Valkeinen,
linux-rockchip
From: Paul Elder <paul.elder@ideasonboard.com>
The i.MX8MP has extra register fields in the memory interface control
register for setting the output format, which work with the output
alignment format register for byte-swapping and LSB/MSB alignment.
With processed and 8-bit raw streams, it doesn't cause any problems to
not set these, but with raw streams of higher bit depth the endianness
is swapped and the data is not aligned properly.
Add support for setting these registers and plumb them in to fix this.
While at it, reflow a comment related to the forced configuration
update.
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
Changes since v13:
- Really set the MP output format in rkisp1_mp_config()
- Update configuration update logic in rkisp1_cap_stream_enable()
- Reflow comment
Changes since v12:
- Merge the output_format_mp and output_format_sp fields
- Set the MP output format in rkisp1_mp_config()
- Fix typo in commit message
Changes since v6:
- replace MP_OUTPUT_FORMAT feature flag with MAIN_STRIDE
New in v6
---
.../platform/rockchip/rkisp1/rkisp1-capture.c | 88 ++++++++++++++++---
.../platform/rockchip/rkisp1/rkisp1-regs.h | 9 ++
2 files changed, 85 insertions(+), 12 deletions(-)
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
index 0efdf8513de0..9e0e69052096 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
@@ -48,14 +48,17 @@ enum rkisp1_plane {
* @fmt_type: helper filed for pixel format
* @uv_swap: if cb cr swapped, for yuv
* @yc_swap: if y and cb/cr swapped, for yuv
+ * @byte_swap: if byte pairs are swapped, for raw
* @write_format: defines how YCbCr self picture data is written to memory
- * @output_format: defines sp output format
+ * @output_format: defines the output format (RKISP1_CIF_MI_INIT_MP_OUTPUT_* for
+ * the main path and RKISP1_MI_CTRL_SP_OUTPUT_* for the self path)
* @mbus: the mbus code on the src resizer pad that matches the pixel format
*/
struct rkisp1_capture_fmt_cfg {
u32 fourcc;
u32 uv_swap : 1;
u32 yc_swap : 1;
+ u32 byte_swap : 1;
u32 write_format;
u32 output_format;
u32 mbus;
@@ -96,42 +99,50 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = {
.fourcc = V4L2_PIX_FMT_YUYV,
.uv_swap = 0,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
}, {
.fourcc = V4L2_PIX_FMT_UYVY,
.uv_swap = 0,
.yc_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
}, {
.fourcc = V4L2_PIX_FMT_YUV422P,
.uv_swap = 0,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
}, {
.fourcc = V4L2_PIX_FMT_NV16,
.uv_swap = 0,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
}, {
.fourcc = V4L2_PIX_FMT_NV61,
.uv_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
}, {
.fourcc = V4L2_PIX_FMT_NV16M,
.uv_swap = 0,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
}, {
.fourcc = V4L2_PIX_FMT_NV61M,
.uv_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
}, {
.fourcc = V4L2_PIX_FMT_YVU422M,
.uv_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
},
/* yuv400 */
@@ -139,6 +150,7 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = {
.fourcc = V4L2_PIX_FMT_GREY,
.uv_swap = 0,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV400,
.mbus = MEDIA_BUS_FMT_YUYV8_2X8,
},
/* yuv420 */
@@ -146,81 +158,107 @@ static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = {
.fourcc = V4L2_PIX_FMT_NV21,
.uv_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
.mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
}, {
.fourcc = V4L2_PIX_FMT_NV12,
.uv_swap = 0,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
.mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
}, {
.fourcc = V4L2_PIX_FMT_NV21M,
.uv_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
.mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
}, {
.fourcc = V4L2_PIX_FMT_NV12M,
.uv_swap = 0,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
.mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
}, {
.fourcc = V4L2_PIX_FMT_YUV420,
.uv_swap = 0,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
.mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
}, {
.fourcc = V4L2_PIX_FMT_YVU420,
.uv_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
.mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
},
/* raw */
{
.fourcc = V4L2_PIX_FMT_SRGGB8,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
.mbus = MEDIA_BUS_FMT_SRGGB8_1X8,
}, {
.fourcc = V4L2_PIX_FMT_SGRBG8,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
.mbus = MEDIA_BUS_FMT_SGRBG8_1X8,
}, {
.fourcc = V4L2_PIX_FMT_SGBRG8,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
.mbus = MEDIA_BUS_FMT_SGBRG8_1X8,
}, {
.fourcc = V4L2_PIX_FMT_SBGGR8,
.write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
.mbus = MEDIA_BUS_FMT_SBGGR8_1X8,
}, {
.fourcc = V4L2_PIX_FMT_SRGGB10,
+ .byte_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
.mbus = MEDIA_BUS_FMT_SRGGB10_1X10,
}, {
.fourcc = V4L2_PIX_FMT_SGRBG10,
+ .byte_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
.mbus = MEDIA_BUS_FMT_SGRBG10_1X10,
}, {
.fourcc = V4L2_PIX_FMT_SGBRG10,
+ .byte_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
.mbus = MEDIA_BUS_FMT_SGBRG10_1X10,
}, {
.fourcc = V4L2_PIX_FMT_SBGGR10,
+ .byte_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
.mbus = MEDIA_BUS_FMT_SBGGR10_1X10,
}, {
.fourcc = V4L2_PIX_FMT_SRGGB12,
+ .byte_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
.mbus = MEDIA_BUS_FMT_SRGGB12_1X12,
}, {
.fourcc = V4L2_PIX_FMT_SGRBG12,
+ .byte_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
.mbus = MEDIA_BUS_FMT_SGRBG12_1X12,
}, {
.fourcc = V4L2_PIX_FMT_SGBRG12,
+ .byte_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
.mbus = MEDIA_BUS_FMT_SGBRG12_1X12,
}, {
.fourcc = V4L2_PIX_FMT_SBGGR12,
+ .byte_swap = 1,
.write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
.mbus = MEDIA_BUS_FMT_SBGGR12_1X12,
},
};
@@ -484,11 +522,16 @@ static void rkisp1_mp_config(struct rkisp1_capture *cap)
*/
if (rkisp1_has_feature(rkisp1, MAIN_STRIDE)) {
reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT);
- if (cap->pix.cfg->yc_swap)
+ if (cap->pix.cfg->yc_swap || cap->pix.cfg->byte_swap)
reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES;
else
reg &= ~RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES;
+
+ reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_LSB_ALIGNMENT;
rkisp1_write(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT, reg);
+
+ rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT,
+ cap->pix.cfg->output_format);
}
rkisp1_mi_config_ctrl(cap);
@@ -951,19 +994,40 @@ static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap)
spin_lock_irq(&cap->buf.lock);
rkisp1_set_next_buf(cap);
cap->ops->enable(cap);
- /* It's safe to configure ACTIVE and SHADOW registers for the
- * first stream. While when the second is starting, do NOT
- * force update because it also updates the first one.
+
+ /*
+ * It's safe to configure ACTIVE and SHADOW registers for the first
+ * stream. While when the second is starting, do NOT force update
+ * because it also updates the first one.
*
- * The latter case would drop one more buffer(that is 2) since
- * there's no buffer in a shadow register when the second FE received.
- * This's also required because the second FE maybe corrupt
- * especially when run at 120fps.
+ * The latter case would drop one more buffer(that is 2) since there's
+ * no buffer in a shadow register when the second FE received. This's
+ * also required because the second FE maybe corrupt especially when
+ * run at 120fps.
*/
if (!has_self_path || !other->is_streaming) {
- /* force cfg update */
- rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT,
- RKISP1_CIF_MI_INIT_SOFT_UPD);
+ u32 reg;
+
+ /*
+ * Force cfg update.
+ *
+ * The ISP8000 (implementing the MAIN_STRIDE feature) as a
+ * mp_output_format field in the CIF_MI_INIT register that must
+ * be preserved. It can be read back, but it is not clear what
+ * other register bits will return. Mask them out.
+ *
+ * On Rockchip platforms, the CIF_MI_INIT register is marked as
+ * write-only and reads as zeros. We can skip reading it.
+ */
+ if (rkisp1_has_feature(rkisp1, MAIN_STRIDE))
+ reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_INIT)
+ & RKISP1_CIF_MI_INIT_MP_OUTPUT_MASK;
+ else
+ reg = 0;
+
+ reg |= RKISP1_CIF_MI_INIT_SOFT_UPD;
+ rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT, reg);
+
rkisp1_set_next_buf(cap);
}
spin_unlock_irq(&cap->buf.lock);
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
index 3b19c8411360..fccf4c17ee8d 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
@@ -144,6 +144,15 @@
/* MI_INIT */
#define RKISP1_CIF_MI_INIT_SKIP BIT(2)
#define RKISP1_CIF_MI_INIT_SOFT_UPD BIT(4)
+#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV400 (0 << 5)
+#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420 (1 << 5)
+#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422 (2 << 5)
+#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV444 (3 << 5)
+#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12 (4 << 5)
+#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8 (5 << 5)
+#define RKISP1_CIF_MI_INIT_MP_OUTPUT_JPEG (6 << 5)
+#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10 (7 << 5)
+#define RKISP1_CIF_MI_INIT_MP_OUTPUT_MASK (15 << 5)
/* MI_CTRL_SHD */
#define RKISP1_CIF_MI_CTRL_SHD_MP_IN_ENABLED BIT(0)
--
Regards,
Laurent Pinchart
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 17+ messages in thread
end of thread, other threads:[~2024-02-19 12:54 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-02-18 20:43 [PATCH v13 00/12] media: rkisp1: Add support for i.MX8MP Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 01/12] media: rkisp1: Add and use rkisp1_has_feature() macro Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 02/12] media: rkisp1: Support setting memory stride for main path Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 03/12] media: rkisp1: Support devices lacking self path Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 04/12] media: rkisp1: Support devices lacking dual crop Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 05/12] dt-bindings: media: rkisp1: Add i.MX8MP ISP to compatible Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 06/12] media: rkisp1: Add version enum for i.MX8MP ISP Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 07/12] media: rkisp1: Configure gasket on i.MX8MP Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 08/12] media: rkisp1: Support i.MX8MP's 34-bit DMA Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 09/12] media: rkisp1: Add YC swap capability Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 10/12] media: rkisp1: Add UYVY as an output format Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 11/12] media: rkisp1: Fix endianness on raw streams on i.MX8MP Laurent Pinchart
2024-02-19 9:56 ` Paul Elder
2024-02-19 10:29 ` Laurent Pinchart
2024-02-19 12:54 ` [PATCH v13.1 " Laurent Pinchart
2024-02-18 20:43 ` [PATCH v13 12/12] media: rkisp1: Add match data for i.MX8MP ISP Laurent Pinchart
2024-02-19 8:42 ` [PATCH v13 00/12] media: rkisp1: Add support for i.MX8MP Alexander Stein
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