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* [PATCH v4] dt-bindings: clock: via,vt8500: Convert to DT Schema
@ 2026-05-24 15:10 Udaya Kiran Challa
  2026-05-30  7:35 ` Krzysztof Kozlowski
  0 siblings, 1 reply; 4+ messages in thread
From: Udaya Kiran Challa @ 2026-05-24 15:10 UTC (permalink / raw)
  To: mturquette, sboyd, robh, krzk+dt, conor+dt
  Cc: skhan, me, linux-rtc, devicetree, linux-kernel,
	Udaya Kiran Challa

Convert the VIA/Wondermedia VT8500 and Wondermedia WM8xxx series SoCs clock
controller binding from the legacy text format to DT schema.

Signed-off-by: Udaya Kiran Challa <challauday369@gmail.com>
---
Changelog:
Changes since v3
- Add schema select matching for via,vt8500-pmc
- Allow hyphen in node names under patternProperties
- Add dependentRequired validation for enable-reg/enable-bit
- Fix example validation against PMC schema

Link to v3:https://lore.kernel.org/all/20260524111813.39810-1-challauday369@gmail.com/

Changes since v2:
- Drop redundant description for clocks
- Disable reg property for device clocks
- Fix schema hierarchy to match actual DTS structure

Link to v2:https://lore.kernel.org/all/20260521170810.19702-1-challauday369@gmail.com/

Changes since v1:
- Add default value for divisor-mask
- Add required properties compatible and model
- Fix example node name
- Update example size cells and reg value

Link to v1:https://lore.kernel.org/all/20260520025131.17772-1-challauday369@gmail.com/
---
 .../bindings/clock/via,vt8500-clock.yaml      | 209 ++++++++++++++++++
 .../devicetree/bindings/clock/vt8500.txt      |  74 -------
 2 files changed, 209 insertions(+), 74 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/via,vt8500-clock.yaml
 delete mode 100644 Documentation/devicetree/bindings/clock/vt8500.txt

diff --git a/Documentation/devicetree/bindings/clock/via,vt8500-clock.yaml b/Documentation/devicetree/bindings/clock/via,vt8500-clock.yaml
new file mode 100644
index 000000000000..51a68df6c2f3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/via,vt8500-clock.yaml
@@ -0,0 +1,209 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/via,vt8500-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: VIA/Wondermedia VT8500 Clock Controller
+
+maintainers:
+  - Michael Turquette <mturquette@baylibre.com>
+  - Stephen Boyd <sboyd@kernel.org>
+
+description:
+  Clock controller bindings for VIA/Wondermedia VT8500 and Wondermedia WM8xxx
+  series SoCs.
+
+select:
+  properties:
+    compatible:
+      const: via,vt8500-pmc
+
+  required:
+    - compatible
+
+properties:
+  compatible:
+    const: via,vt8500-pmc
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    type: object
+    additionalProperties: true
+
+    properties:
+      "#address-cells":
+        const: 1
+
+      "#size-cells":
+        const: 0
+
+    required:
+      - "#address-cells"
+      - "#size-cells"
+
+    patternProperties:
+      "^[a-z0-9-]+(@[0-9a-f]+)?$":
+        type: object
+
+        properties:
+          compatible:
+            enum:
+              - via,vt8500-pll-clock
+              - wm,wm8650-pll-clock
+              - wm,wm8750-pll-clock
+              - wm,wm8850-pll-clock
+              - via,vt8500-device-clock
+
+          reg:
+            maxItems: 1
+            description:
+              Offset of the PLL register within the PMC register space.
+
+          clocks:
+            maxItems: 1
+
+          "#clock-cells":
+            const: 0
+
+          enable-reg:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            description:
+              Offset of the clock enable register within the PMC
+              register space.
+
+          enable-bit:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            maximum: 31
+            description:
+              Bit index controlling clock enable.
+
+          divisor-reg:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            description:
+              Offset of the clock divisor register within the PMC
+              register space.
+
+          divisor-mask:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            default: 0x1f
+            description:
+              Bitmask describing the divisor field inside divisor-reg.
+
+        dependentRequired:
+          enable-reg:
+            - enable-bit
+
+          enable-bit:
+            - enable-reg
+
+        required:
+          - compatible
+          - "#clock-cells"
+
+        allOf:
+          - if:
+              properties:
+                compatible:
+                  enum:
+                    - via,vt8500-pll-clock
+                    - wm,wm8650-pll-clock
+                    - wm,wm8750-pll-clock
+                    - wm,wm8850-pll-clock
+            then:
+              required:
+                - reg
+                - clocks
+
+          - if:
+              properties:
+                compatible:
+                  const: via,vt8500-device-clock
+            then:
+              properties:
+                reg: false
+
+              required:
+                - clocks
+
+              anyOf:
+                - required:
+                    - enable-reg
+                    - enable-bit
+
+                - required:
+                    - divisor-reg
+
+        additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    pmc@d8130000 {
+        compatible = "via,vt8500-pmc";
+        reg = <0xd8130000 0x1000>;
+
+        clocks {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            ref24: ref24M {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <24000000>;
+            };
+
+            ref25: ref25M {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <25000000>;
+            };
+
+            plla: clock@200 {
+                compatible = "wm,wm8650-pll-clock";
+                #clock-cells = <0>;
+                clocks = <&ref25>;
+                reg = <0x200>;
+            };
+
+            pllb: clock@204 {
+                compatible = "wm,wm8650-pll-clock";
+                #clock-cells = <0>;
+                clocks = <&ref25>;
+                reg = <0x204>;
+            };
+
+            clkarm: arm {
+                compatible = "via,vt8500-device-clock";
+                #clock-cells = <0>;
+                clocks = <&plla>;
+                divisor-reg = <0x300>;
+            };
+
+            clkuart0: uart0 {
+                compatible = "via,vt8500-device-clock";
+                #clock-cells = <0>;
+                clocks = <&ref24>;
+                enable-reg = <0x250>;
+                enable-bit = <1>;
+            };
+
+            clksdhc: sdhc {
+                compatible = "via,vt8500-device-clock";
+                #clock-cells = <0>;
+                clocks = <&pllb>;
+                divisor-reg = <0x328>;
+                divisor-mask = <0x3f>;
+                enable-reg = <0x254>;
+                enable-bit = <18>;
+            };
+        };
+    };
diff --git a/Documentation/devicetree/bindings/clock/vt8500.txt b/Documentation/devicetree/bindings/clock/vt8500.txt
deleted file mode 100644
index 91d71cc0314a..000000000000
--- a/Documentation/devicetree/bindings/clock/vt8500.txt
+++ /dev/null
@@ -1,74 +0,0 @@
-Device Tree Clock bindings for arch-vt8500
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible : shall be one of the following:
-	"via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
-	"wm,wm8650-pll-clock" - for a WM8650 PLL clock
-	"wm,wm8750-pll-clock" - for a WM8750 PLL clock
-	"wm,wm8850-pll-clock" - for a WM8850 PLL clock
-	"via,vt8500-device-clock" - for a VT/WM device clock
-
-Required properties for PLL clocks:
-- reg : shall be the control register offset from PMC base for the pll clock.
-- clocks : shall be the input parent clock phandle for the clock. This should
-	be the reference clock.
-- #clock-cells : from common clock binding; shall be set to 0.
-
-Required properties for device clocks:
-- clocks : shall be the input parent clock phandle for the clock. This should
-	be a pll output.
-- #clock-cells : from common clock binding; shall be set to 0.
-
-
-Device Clocks
-
-Device clocks are required to have one or both of the following sets of
-properties:
-
-
-Gated device clocks:
-
-Required properties:
-- enable-reg : shall be the register offset from PMC base for the enable
-	register.
-- enable-bit : shall be the bit within enable-reg to enable/disable the clock.
-
-
-Divisor device clocks:
-
-Required property:
-- divisor-reg : shall be the register offset from PMC base for the divisor
-	register.
-Optional property:
-- divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
-	if not specified.
-
-
-For example:
-
-ref25: ref25M {
-	#clock-cells = <0>;
-	compatible = "fixed-clock";
-	clock-frequency = <25000000>;
-};
-
-plla: plla {
-	#clock-cells = <0>;
-	compatible = "wm,wm8650-pll-clock";
-	clocks = <&ref25>;
-	reg = <0x200>;
-};
-
-sdhc: sdhc {
-	#clock-cells = <0>;
-	compatible = "via,vt8500-device-clock";
-	clocks = <&pllb>;
-	divisor-reg = <0x328>;
-	divisor-mask = <0x3f>;
-	enable-reg = <0x254>;
-	enable-bit = <18>;
-};
-- 
2.43.0


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2026-05-24 15:10 [PATCH v4] dt-bindings: clock: via,vt8500: Convert to DT Schema Udaya Kiran Challa
2026-05-30  7:35 ` Krzysztof Kozlowski
2026-05-31 16:49   ` Uday Kiran
2026-06-01 11:44     ` Krzysztof Kozlowski

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