[PATCH V1 0/3] ufs: ufs-qcom: Fixes and optimizations for Qualcomm UFS platform

[PATCH V1 0/3] ufs: ufs-qcom: Fixes and optimizations for Qualcomm UFS platform

[Nitin Rawat]

This patch series introduces few fixes and performance optimizations
for the Qualcomm UFS host controller driver to improve performance
and to align with Qualcomm UFS hardware programming sequence.

The series addresses three key areas:

1. Enhanced interrupt handling through CPU affinity optimization.
2. Hardware programming sequence alignment for UFS controller v6.2
3. Performance tuning for sequential read workloads.

Nitin Rawat (3):
  ufs: ufs-qcom: Add UFS ESI CPU affinity support
  ufs: ufs-qcom: Align programming sequence for UFS controller v6.2
  ufs: ufs-qcom: Fix sequential read variance

 drivers/ufs/host/ufs-qcom.c | 63 ++++++++++++++++++++++++++++++++++---
 drivers/ufs/host/ufs-qcom.h |  1 +
 2 files changed, 60 insertions(+), 4 deletions(-)

--
2.34.1

[PATCH V1 1/3] ufs: ufs-qcom: Add UFS ESI CPU affinity support

[Nitin Rawat]

Add Enhanced Shared Interrupt (ESI) CPU affinity support to improve
UFS performance on Qualcomm platforms.

By Default, the IRQ core route interrupts to a limited number of
cores while other cores remain idle. This patch enables dynamic
interrupt affinity adjustment for better performance tuning by
distributing ESI interrupts across all online CPUs in round-robin
fashion.

This reduces CPU contention and enables better performance optimization
on Qualcomm UFS controllers by utilizing all available online CPUs.

Signed-off-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
---
 drivers/ufs/host/ufs-qcom.c | 50 +++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 8ebee0cc5313..c43bb75d208c 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -2070,6 +2070,55 @@ static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data)
 	return IRQ_HANDLED;
 }

+/**
+ * ufs_qcom_set_esi_affinity - Set CPU affinity hints for ESI interrupts
+ * @hba: UFS host controller instance
+ *
+ * Sets CPU affinity hints for ESI interrupts to distribute them across
+ * online CPUs for better performance in round-robin fashion.
+ */
+static void ufs_qcom_set_esi_affinity(struct ufs_hba *hba)
+{
+	struct msi_desc *desc;
+	int ret, i = 0, nr_irqs = 0;
+	const cpumask_t *mask;
+	int cpu;
+
+	__msi_lock_descs(hba->dev);
+	/* Count the number of MSI descriptors */
+	msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) {
+		nr_irqs++;
+	}
+	__msi_unlock_descs(hba->dev);
+
+	if (nr_irqs == 0)
+		return;
+
+	__msi_lock_descs(hba->dev);
+	/* Set affinity hints for each interrupt in round-robin fashion */
+	msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) {
+		if (i >= nr_irqs)
+			break;
+
+		/* Distribute interrupts across online CPUs in round-robin */
+		cpu = cpumask_nth(i % num_online_cpus(), cpu_online_mask);
+		mask = get_cpu_mask(cpu);
+		if (!cpumask_subset(mask, cpu_online_mask)) {
+			dev_err(hba->dev, "Invalid CPU %d in map, using online CPUs\n",
+				cpu);
+			mask = cpu_online_mask;
+		}
+
+		ret = irq_set_affinity_hint(desc->irq, mask);
+		if (ret < 0)
+			dev_err(hba->dev, "Failed to set affinity hint to CPU %d for ESI IRQ %d, err = %d\n",
+				cpu, desc->irq, ret);
+
+		i++;
+	}
+	__msi_unlock_descs(hba->dev);
+}
+
 static int ufs_qcom_config_esi(struct ufs_hba *hba)
 {
 	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
@@ -2122,6 +2171,7 @@ static int ufs_qcom_config_esi(struct ufs_hba *hba)
 			    REG_UFS_CFG3);
 	}
 	ufshcd_mcq_enable_esi(hba);
+	ufs_qcom_set_esi_affinity(hba);
 	host->esi_enabled = true;
 	return 0;
 }
--
2.34.1

[PATCH V1 2/3] ufs: ufs-qcom: Align programming sequence for UFS controller v6.2

[Nitin Rawat]

UFS controller v6.2 requires bit 31 in the spare configuration register
to be set for high-speed link startup mode, as per the Hardware
Programming Guide (HPG).

The spare register value is read during host driver initialization but
gets cleared after UFS reset. To align with the UFS v6.2 programming
sequence, preserve the spare register value during initialization and
restore it during link startup to ensure proper high-speed mode

Signed-off-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
---
 drivers/ufs/host/ufs-qcom.c | 11 ++++++++---
 drivers/ufs/host/ufs-qcom.h |  1 +
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index c43bb75d208c..ab5aed241913 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -686,6 +686,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up, unsign
 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
 					enum ufs_notify_change_status status)
 {
+	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 	int err = 0;

 	switch (status) {
@@ -708,6 +709,10 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
 		 */
 		err = ufshcd_disable_host_tx_lcc(hba);

+		/* Update REG_UFS_DEBUG_SPARE_CFG to set HS-LSS mode in link startup */
+		if (host->hw_ver.major == 0x6 && host->hw_ver.minor == 0x2)
+			ufshcd_writel(hba, host->spare_cfg,
+				      REG_UFS_DEBUG_SPARE_CFG);
 		break;
 	default:
 		break;
@@ -1084,7 +1089,7 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
 static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
 {
 	struct ufs_host_params *host_params = &host->host_params;
-	u32 val, dev_major;
+	u32 dev_major;

 	/*
 	 * Default to powering up the PHY to the max gear possible, which is
@@ -1103,8 +1108,8 @@ static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
 		 */
 		host->phy_gear = UFS_HS_G2;
 	} else if (host->hw_ver.major >= 0x5) {
-		val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG);
-		dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val);
+		host->spare_cfg = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG);
+		dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, host->spare_cfg);

 		/*
 		 * Since the UFS device version is populated, let's remove the
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 380d02333d38..d09ef7f44305 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -308,6 +308,7 @@ struct ufs_qcom_host {
 	u32 phy_gear;

 	bool esi_enabled;
+	u32 spare_cfg;
 };

 struct ufs_qcom_drvdata {
--
2.34.1

[PATCH V1 3/3] ufs: ufs-qcom: Fix sequential read variance

[Nitin Rawat]

The current devfreq downdifferential threshold of 5% causes overly
aggressive frequency downscaling, leading to performance degradation
sometimes during sequential read workloads.

Update the UFS devfreq downdifferential threshold to 65.
This widens the hysteresis window and prevents overly aggressive
downscaling, ensuring that frequency is maintained for loads above 5%
and scaling down occurs only when utilization falls below this level,
while scale-up still triggers above the 70% threshold.

Signed-off-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
---
 drivers/ufs/host/ufs-qcom.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index ab5aed241913..5ef810b95b72 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -1962,7 +1962,7 @@ static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
 	p->polling_ms = 60;
 	p->timer = DEVFREQ_TIMER_DELAYED;
 	d->upthreshold = 70;
-	d->downdifferential = 5;
+	d->downdifferential = 65;

 	hba->clk_scaling.suspend_on_no_request = true;
 }
--
2.34.1

Re: [PATCH V1 2/3] ufs: ufs-qcom: Align programming sequence for UFS controller v6.2

[Konrad Dybcio]

On 1/22/26 3:13 PM, Nitin Rawat wrote:
> UFS controller v6.2 requires bit 31 in the spare configuration register
> to be set for high-speed link startup mode, as per the Hardware
> Programming Guide (HPG).

Please stick a "Qualcomm" before mentioning UFS controller v6.2, I
don't think that is immediately obvious without looking at the code..

> The spare register value is read during host driver initialization but
> gets cleared after UFS reset. To align with the UFS v6.2 programming
> sequence, preserve the spare register value during initialization and
> restore it during link startup to ensure proper high-speed mode

I believe you're supposed to write the value yourself, depending on the
state of the controller, it's 0 at reset.

> Signed-off-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
> ---
>  drivers/ufs/host/ufs-qcom.c | 11 ++++++++---
>  drivers/ufs/host/ufs-qcom.h |  1 +
>  2 files changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index c43bb75d208c..ab5aed241913 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -686,6 +686,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up, unsign
>  static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
>  					enum ufs_notify_change_status status)
>  {
> +	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
>  	int err = 0;
> 
>  	switch (status) {
> @@ -708,6 +709,10 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
>  		 */
>  		err = ufshcd_disable_host_tx_lcc(hba);
> 
> +		/* Update REG_UFS_DEBUG_SPARE_CFG to set HS-LSS mode in link startup */

"HS/LS"?

> +		if (host->hw_ver.major == 0x6 && host->hw_ver.minor == 0x2)
> +			ufshcd_writel(hba, host->spare_cfg,
> +				      REG_UFS_DEBUG_SPARE_CFG);

Is that a "only on v6.2", or "starting with v6.2"?

Also, I see that this register has more than just this one field, with
the previous question in mind, I think a rmw would be desired here

Konrad

Re: [PATCH V1 3/3] ufs: ufs-qcom: Fix sequential read variance

[Konrad Dybcio]

On 1/22/26 3:13 PM, Nitin Rawat wrote:
> The current devfreq downdifferential threshold of 5% causes overly
> aggressive frequency downscaling, leading to performance degradation
> sometimes during sequential read workloads.
> 
> Update the UFS devfreq downdifferential threshold to 65.
> This widens the hysteresis window and prevents overly aggressive
> downscaling, ensuring that frequency is maintained for loads above 5%
> and scaling down occurs only when utilization falls below this level,
> while scale-up still triggers above the 70% threshold.
> 
> Signed-off-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
> ---
>  drivers/ufs/host/ufs-qcom.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index ab5aed241913..5ef810b95b72 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -1962,7 +1962,7 @@ static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
>  	p->polling_ms = 60;
>  	p->timer = DEVFREQ_TIMER_DELAYED;
>  	d->upthreshold = 70;
> -	d->downdifferential = 5;
> +	d->downdifferential = 65;

FWIW I see this is the value that's been shipping on android for 
quite a while 

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH V1 1/3] ufs: ufs-qcom: Add UFS ESI CPU affinity support

[Bart Van Assche]

On 1/22/26 6:13 AM, Nitin Rawat wrote:
> +static void ufs_qcom_set_esi_affinity(struct ufs_hba *hba)
> +{
> +	struct msi_desc *desc;
> +	int ret, i = 0, nr_irqs = 0;
> +	const cpumask_t *mask;
> +	int cpu;
> +
> +	__msi_lock_descs(hba->dev);
> +	/* Count the number of MSI descriptors */
> +	msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) {
> +		nr_irqs++;
> +	}
> +	__msi_unlock_descs(hba->dev);
> +
> +	if (nr_irqs == 0)
> +		return;
> +
> +	__msi_lock_descs(hba->dev);
> +	/* Set affinity hints for each interrupt in round-robin fashion */
> +	msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) {
> +		if (i >= nr_irqs)
> +			break;
> +
> +		/* Distribute interrupts across online CPUs in round-robin */
> +		cpu = cpumask_nth(i % num_online_cpus(), cpu_online_mask);
> +		mask = get_cpu_mask(cpu);
> +		if (!cpumask_subset(mask, cpu_online_mask)) {
> +			dev_err(hba->dev, "Invalid CPU %d in map, using online CPUs\n",
> +				cpu);
> +			mask = cpu_online_mask;
> +		}
> +
> +		ret = irq_set_affinity_hint(desc->irq, mask);
> +		if (ret < 0)
> +			dev_err(hba->dev, "Failed to set affinity hint to CPU %d for ESI IRQ %d, err = %d\n",
> +				cpu, desc->irq, ret);
> +
> +		i++;
> +	}
> +	__msi_unlock_descs(hba->dev);
> +}

Why an entirely new function for setting interrupt affinity? Why isn't
irq_create_affinity_masks() good enough? Are you aware that
devm_platform_get_irqs_affinity() calls irq_create_affinity_masks()?

Thanks,

Bart.

Re: [PATCH V1 2/3] ufs: ufs-qcom: Align programming sequence for UFS controller v6.2

[Nitin Rawat]

On 1/22/2026 8:39 PM, Konrad Dybcio wrote:
> On 1/22/26 3:13 PM, Nitin Rawat wrote:
>> UFS controller v6.2 requires bit 31 in the spare configuration register
>> to be set for high-speed link startup mode, as per the Hardware
>> Programming Guide (HPG).

Hi Konrad,

I've revived this patch. Sorry for the delayed response. Thanks for your 
previous comments on this patch.

> 
> Please stick a "Qualcomm" before mentioning UFS controller v6.2, I
> don't think that is immediately obvious without looking at the code..
> 
>> The spare register value is read during host driver initialization but
>> gets cleared after UFS reset. To align with the UFS v6.2 programming
>> sequence, preserve the spare register value during initialization and
>> restore it during link startup to ensure proper high-speed mode
> 
> I believe you're supposed to write the value yourself, depending on the
> state of the controller, it's 0 at reset.

The link startup mode (HS LSS - high-speed link startup, or LS LSS - 
low-speed link startup) is decided during the boot stage based on a 
bootconfig GPIO. This selection is carried forward through the secondary 
stage bootloaders and finally to HLOS via this register.

This register is only configured by the bootloader — no kernel code 
writes other fields to it. The kernel reads it during initialization to 
capture the configured link startup mode, and restores it after UFS 
reset (which clears the register to 0) so that the bootloader's 
selection is preserved for link startup.



> 
>> Signed-off-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
>> ---
>>   drivers/ufs/host/ufs-qcom.c | 11 ++++++++---
>>   drivers/ufs/host/ufs-qcom.h |  1 +
>>   2 files changed, 9 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>> index c43bb75d208c..ab5aed241913 100644
>> --- a/drivers/ufs/host/ufs-qcom.c
>> +++ b/drivers/ufs/host/ufs-qcom.c
>> @@ -686,6 +686,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up, unsign
>>   static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
>>   					enum ufs_notify_change_status status)
>>   {
>> +	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
>>   	int err = 0;
>>
>>   	switch (status) {
>> @@ -708,6 +709,10 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
>>   		 */
>>   		err = ufshcd_disable_host_tx_lcc(hba);
>>
>> +		/* Update REG_UFS_DEBUG_SPARE_CFG to set HS-LSS mode in link startup */
> 
> "HS/LS"?

I've Change wording ("HS/LS" instead of "HS-LSS") in next patchset.

> 
>> +		if (host->hw_ver.major == 0x6 && host->hw_ver.minor == 0x2)
>> +			ufshcd_writel(hba, host->spare_cfg,
>> +				      REG_UFS_DEBUG_SPARE_CFG);
> 
> Is that a "only on v6.2", or "starting with v6.2"?

I've Change version check from "only v6.2" to "starting with v6.2" in 
next patchset.


> 
> Also, I see that this register has more than just this one field, with
> the previous question in mind, I think a rmw would be desired here

I'm using ufshcd_writel since this register is only configured by the 
bootloader and no kernel code writes other fields to it, ufshcd_writel 
is sufficient as there are no kernel written bits to preserve via rmw.

Thanks,
Nitin

> 
> Konrad