Re: [PATCH V2] serial: exar: Preserve FCTR[5] bit in pci_xr17v35x_setup()

[Matthew Howell <matthew.howell@sealevel.com>]

On Wed, 2024-02-21 at 16:16 -0500, Matthew Howell wrote:
> Allows the use of the EN485 hardware pin by preserving the value of
> FCTR[5] in pci_xr17v35x_setup().
> 
> Per the XR17V35X datasheet, the EN485 hardware pin works by setting
> FCTR[5] when the pin is active. pci_xr17v35x_setup() prevented the use
> of EN485 because it overwrote the FCTR register.
> 
> Signed-off-by: Matthew Howell <matthew.howell@sealevel.com>
> ---
> V1 -> V2
> Fixed wordwrap in diff
> 
> diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/8250_exar.c
> index 23366f868..97711606f 100644
> --- a/drivers/tty/serial/8250/8250_exar.c
> +++ b/drivers/tty/serial/8250/8250_exar.c
> @@ -596,6 +596,7 @@ pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
>  	unsigned int baud = 7812500;
>  	u8 __iomem *p;
>  	int ret;
> +	u8 en485mask;
>  
>  	port->port.uartclk = baud * 16;
>  	port->port.rs485_config = platform->rs485_config;
> @@ -618,7 +619,8 @@ pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
>  	p = port->port.membase;
>  
>  	writeb(0x00, p + UART_EXAR_8XMODE);
> -	writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
> +	en485mask = readb(p + UART_EXAR_FCTR) & UART_FCTR_EXAR_485;
> +	writeb(UART_FCTR_EXAR_TRGD | en485mask, p + UART_EXAR_FCTR);
>  	writeb(128, p + UART_EXAR_TXTRG);
>  	writeb(128, p + UART_EXAR_RXTRG);
>  
> 

Hi,

Just wanted to follow-up on this to see if anyone has had a time to
review the above submission? Please let me know if there are any issues
/ anything I need to do.

Thanks,
Matthew Howell