From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Matthew Howell <matthew.howell@sealevel.com>
Cc: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
"linux-serial@vger.kernel.org" <linux-serial@vger.kernel.org>,
Darren Beeson <darren.beeson@sealevel.com>,
Jeff Baldwin <jeff.baldwin@sealevel.com>,
Ryan Wenglarz <ryan.wenglarz@sealevel.com>
Subject: Re: [PATCH V2] serial: exar: Preserve FCTR[5] bit in pci_xr17v35x_setup()
Date: Mon, 8 Apr 2024 20:25:28 +0300 (EEST) [thread overview]
Message-ID: <db3d5156-5ba7-e3e0-42c8-37f9d4f5efcb@linux.intel.com> (raw)
In-Reply-To: <74b591e8-c8b1-7a9b-e2ea-c375f3d712c2@linux.intel.com>
[-- Attachment #1: Type: text/plain, Size: 2037 bytes --]
On Mon, 8 Apr 2024, Ilpo Järvinen wrote:
> On Mon, 8 Apr 2024, Matthew Howell wrote:
>
> > On Wed, 2024-02-21 at 16:16 -0500, Matthew Howell wrote:
> > > Allows the use of the EN485 hardware pin by preserving the value of
> > > FCTR[5] in pci_xr17v35x_setup().
> > >
> > > Per the XR17V35X datasheet, the EN485 hardware pin works by setting
> > > FCTR[5] when the pin is active. pci_xr17v35x_setup() prevented the use
> > > of EN485 because it overwrote the FCTR register.
> > >
> > > Signed-off-by: Matthew Howell <matthew.howell@sealevel.com>
> > > ---
> > > V1 -> V2
> > > Fixed wordwrap in diff
> > >
> > > diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/8250_exar.c
> > > index 23366f868..97711606f 100644
> > > --- a/drivers/tty/serial/8250/8250_exar.c
> > > +++ b/drivers/tty/serial/8250/8250_exar.c
> > > @@ -596,6 +596,7 @@ pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
> > > unsigned int baud = 7812500;
> > > u8 __iomem *p;
> > > int ret;
> > > + u8 en485mask;
> > >
> > > port->port.uartclk = baud * 16;
> > > port->port.rs485_config = platform->rs485_config;
> > > @@ -618,7 +619,8 @@ pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
> > > p = port->port.membase;
> > >
> > > writeb(0x00, p + UART_EXAR_8XMODE);
> > > - writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
> > > + en485mask = readb(p + UART_EXAR_FCTR) & UART_FCTR_EXAR_485;
> > > + writeb(UART_FCTR_EXAR_TRGD | en485mask, p + UART_EXAR_FCTR);
> > > writeb(128, p + UART_EXAR_TXTRG);
> > > writeb(128, p + UART_EXAR_RXTRG);
>
> Why you need to read rs485 state from the register? It should be available
> in ->rs485.flags & SER_RS485_ENABLED.
>
> pci_fastcom335_setup() seems to have the same problem? Path small part
I meant "That small part ..."
> seems to be common code anyway which should be moved into helper, only the
> trigger threshold seems to differ which can be given in a parameter.
>
>
--
i.
next prev parent reply other threads:[~2024-04-08 17:25 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-21 21:06 [PATCH V1] serial: exar: Preserve FCTR[5] bit in pci_xr17v35x_setup() Matthew Howell
2024-02-21 21:16 ` [PATCH V2] " Matthew Howell
2024-02-21 22:58 ` andy.shevchenko
2024-04-09 13:01 ` Matthew Howell
2024-04-08 13:11 ` Matthew Howell
2024-04-08 14:56 ` gregkh
2024-04-09 12:33 ` Matthew Howell
2024-04-08 16:48 ` Ilpo Järvinen
2024-04-08 17:25 ` Ilpo Järvinen [this message]
2024-04-08 20:27 ` Matthew Howell
2024-04-10 13:49 ` Ilpo Järvinen
2024-04-10 16:20 ` Matthew Howell
2024-04-11 8:27 ` Ilpo Järvinen
2024-04-11 17:01 ` Matthew Howell
2024-04-11 20:44 ` Matthew Howell
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